xref: /openbmc/u-boot/include/configs/MPC8349ITX.h (revision 284170309cab2006e7730c65454458680921b16a)
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
25 
26  Memory map:
27 
28  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
34  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
35  0xF001_0000-0xF001_FFFF Local bus expansion slot
36  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
39 
40  I2C address list:
41 						Align.	Board
42  Bus	Addr	Part No.	Description	Length	Location
43  ----------------------------------------------------------------
44  I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
45 
46  I2C1	0x20	PCF8574		I2C Expander	0	U8
47  I2C1	0x21	PCF8574		I2C Expander	0	U10
48  I2C1	0x38	PCF8574A	I2C Expander	0	U8
49  I2C1	0x39	PCF8574A	I2C Expander	0	U10
50  I2C1	0x51	(DDR)		DDR EEPROM	1	U1
51  I2C1	0x68	DS1339		RTC		1	U68
52 
53  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
54 */
55 
56 #ifndef __CONFIG_H
57 #define __CONFIG_H
58 
59 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
60 #define CONFIG_SYS_LOWBOOT
61 #endif
62 
63 /*
64  * High Level Configuration Options
65  */
66 #define CONFIG_MPC83xx		1
67 #define CONFIG_MPC834x		/* MPC834x family (8343, 8347, 8349) */
68 #define CONFIG_MPC8349		/* MPC8349 specific */
69 
70 #ifndef CONFIG_SYS_TEXT_BASE
71 #define CONFIG_SYS_TEXT_BASE	0xFEF00000
72 #endif
73 
74 #define CONFIG_SYS_IMMR		0xE0000000	/* The IMMR is relocated to here */
75 
76 #define CONFIG_MISC_INIT_F
77 #define CONFIG_MISC_INIT_R
78 
79 /*
80  * On-board devices
81  */
82 
83 #ifdef CONFIG_MPC8349ITX
84 #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
85 #define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
86 #define CONFIG_SATA_SIL3114	/* SIL3114 SATA controller */
87 #define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
88 #endif
89 
90 #define CONFIG_PCI
91 #define CONFIG_RTC_DS1337
92 #define CONFIG_HARD_I2C
93 #define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
94 
95 /*
96  * Device configurations
97  */
98 
99 /* I2C */
100 #ifdef CONFIG_HARD_I2C
101 
102 #define CONFIG_FSL_I2C
103 #define CONFIG_I2C_MULTI_BUS
104 #define CONFIG_SYS_I2C_OFFSET		0x3000
105 #define CONFIG_SYS_I2C2_OFFSET		0x3100
106 #define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
107 #define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */
108 
109 #define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
110 #define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
111 #define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
112 #define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
113 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
114 #define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
115 #define SPD_EEPROM_ADDRESS	0x51	/* I2C1, DDR */
116 
117 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
118 #define CONFIG_SYS_I2C_SLAVE		0x7F
119 
120 /* Don't probe these addresses: */
121 #define CONFIG_SYS_I2C_NOPROBES	{{1, CONFIG_SYS_I2C_8574_ADDR1}, \
122 				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
123 				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
124 				 {1, CONFIG_SYS_I2C_8574A_ADDR2}}
125 /* Bit definitions for the 8574[A] I2C expander */
126 #define I2C_8574_REVISION	0x03	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
127 #define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
128 #define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
129 #define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
130 #define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
131 
132 #undef CONFIG_SOFT_I2C
133 
134 #endif
135 
136 /* Compact Flash */
137 #ifdef CONFIG_COMPACT_FLASH
138 
139 #define CONFIG_SYS_IDE_MAXBUS		1
140 #define CONFIG_SYS_IDE_MAXDEVICE	1
141 
142 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
143 #define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
144 #define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
145 #define CONFIG_SYS_ATA_REG_OFFSET	0
146 #define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
147 #define CONFIG_SYS_ATA_STRIDE		2
148 
149 #define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
150 
151 #endif
152 
153 /*
154  * SATA
155  */
156 #ifdef CONFIG_SATA_SIL3114
157 
158 #define CONFIG_SYS_SATA_MAX_DEVICE      4
159 #define CONFIG_LIBATA
160 #define CONFIG_LBA48
161 
162 #endif
163 
164 #ifdef CONFIG_SYS_USB_HOST
165 /*
166  * Support USB
167  */
168 #define CONFIG_CMD_USB
169 #define CONFIG_USB_STORAGE
170 #define CONFIG_USB_EHCI
171 #define CONFIG_USB_EHCI_FSL
172 
173 /* Current USB implementation supports the only USB controller,
174  * so we have to choose between the MPH or the DR ones */
175 #if 1
176 #define CONFIG_HAS_FSL_MPH_USB
177 #else
178 #define CONFIG_HAS_FSL_DR_USB
179 #endif
180 
181 #endif
182 
183 /*
184  * DDR Setup
185  */
186 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
187 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
188 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
189 #define CONFIG_SYS_83XX_DDR_USES_CS0
190 #define CONFIG_SYS_MEMTEST_START	0x1000		/* memtest region */
191 #define CONFIG_SYS_MEMTEST_END		0x2000
192 
193 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
194 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
195 
196 #define CONFIG_VERY_BIG_RAM
197 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
198 
199 #ifdef CONFIG_HARD_I2C
200 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
201 #endif
202 
203 #ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
204     #define CONFIG_SYS_DDR_SIZE	256		/* Mb */
205     #define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
206 
207     #define CONFIG_SYS_DDR_TIMING_1	0x26242321
208     #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
209 #endif
210 
211 /*
212  *Flash on the Local Bus
213  */
214 
215 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
216 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
217 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
218 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #define CONFIG_SYS_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
220 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
221 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
222 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
223 
224 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
225 boards, we say we have two, but don't display a message if we find only one. */
226 #define CONFIG_SYS_FLASH_QUIET_TEST
227 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
228 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
229 #define CONFIG_SYS_FLASH_SIZE		16		/* FLASH size in MB */
230 #define CONFIG_SYS_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
231 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
232 
233 /* Vitesse 7385 */
234 
235 #ifdef CONFIG_VSC7385_ENET
236 
237 #define CONFIG_TSEC2
238 
239 /* The flash address and size of the VSC7385 firmware image */
240 #define CONFIG_VSC7385_IMAGE		0xFEFFE000
241 #define CONFIG_VSC7385_IMAGE_SIZE	8192
242 
243 #endif
244 
245 /*
246  * BRx, ORx, LBLAWBARx, and LBLAWARx
247  */
248 
249 /* Flash */
250 
251 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
252 #define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
253 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
254 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
255 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
256 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
257 
258 /* Vitesse 7385 */
259 
260 #define CONFIG_SYS_VSC7385_BASE	0xF8000000
261 
262 #ifdef CONFIG_VSC7385_ENET
263 
264 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
265 #define CONFIG_SYS_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
266 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
267 				OR_GPCM_EHTR | OR_GPCM_EAD)
268 
269 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_VSC7385_BASE
270 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
271 
272 #endif
273 
274 /* LED */
275 
276 #define CONFIG_SYS_LED_BASE		0xF9000000
277 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
278 #define CONFIG_SYS_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
279 				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
280 				OR_GPCM_EHTR | OR_GPCM_EAD)
281 
282 /* Compact Flash */
283 
284 #ifdef CONFIG_COMPACT_FLASH
285 
286 #define CONFIG_SYS_CF_BASE		0xF0000000
287 
288 #define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
289 #define CONFIG_SYS_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
290 
291 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CF_BASE
292 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
293 
294 #endif
295 
296 /*
297  * U-Boot memory configuration
298  */
299 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
300 
301 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
302 #define CONFIG_SYS_RAMBOOT
303 #else
304 #undef	CONFIG_SYS_RAMBOOT
305 #endif
306 
307 #define CONFIG_SYS_INIT_RAM_LOCK
308 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
309 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
310 
311 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
312 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
313 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
314 
315 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
316 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
317 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
318 
319 /*
320  * Local Bus LCRR and LBCR regs
321  *    LCRR:  DLL bypass, Clock divider is 4
322  * External Local Bus rate is
323  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
324  */
325 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
326 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
327 #define CONFIG_SYS_LBC_LBCR	0x00000000
328 
329 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
330 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
331 
332 /*
333  * Serial Port
334  */
335 #define CONFIG_CONS_INDEX	1
336 #define CONFIG_SYS_NS16550
337 #define CONFIG_SYS_NS16550_SERIAL
338 #define CONFIG_SYS_NS16550_REG_SIZE	1
339 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
340 
341 #define CONFIG_SYS_BAUDRATE_TABLE  \
342 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
343 
344 #define CONFIG_CONSOLE		ttyS0
345 #define CONFIG_BAUDRATE		115200
346 
347 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
348 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
349 
350 /* pass open firmware flat tree */
351 #define CONFIG_OF_LIBFDT	1
352 #define CONFIG_OF_BOARD_SETUP	1
353 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
354 
355 /*
356  * PCI
357  */
358 #ifdef CONFIG_PCI
359 
360 #define CONFIG_MPC83XX_PCI2
361 
362 /*
363  * General PCI
364  * Addresses are mapped 1-1.
365  */
366 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
367 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
368 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
369 #define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
370 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
371 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
372 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
373 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
374 #define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */
375 
376 #ifdef CONFIG_MPC83XX_PCI2
377 #define CONFIG_SYS_PCI2_MEM_BASE	(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
378 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
379 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
380 #define CONFIG_SYS_PCI2_MMIO_BASE	(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
381 #define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
382 #define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
383 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
384 #define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
385 #define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */
386 #endif
387 
388 #define CONFIG_NET_MULTI
389 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
390 
391 #ifndef CONFIG_PCI_PNP
392     #define PCI_ENET0_IOADDR	0x00000000
393     #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
394     #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
395 #endif
396 
397 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
398 
399 #endif
400 
401 #define CONFIG_PCI_66M
402 #ifdef CONFIG_PCI_66M
403 #define CONFIG_83XX_CLKIN	66666666	/* in Hz */
404 #else
405 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
406 #endif
407 
408 /* TSEC */
409 
410 #ifdef CONFIG_TSEC_ENET
411 
412 #define CONFIG_NET_MULTI
413 #define CONFIG_MII
414 #define CONFIG_PHY_GIGE		/* In case CONFIG_CMD_MII is specified */
415 
416 #define CONFIG_TSEC1
417 
418 #ifdef CONFIG_TSEC1
419 #define CONFIG_HAS_ETH0
420 #define CONFIG_TSEC1_NAME  "TSEC0"
421 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
422 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
423 #define TSEC1_PHYIDX		0
424 #define TSEC1_FLAGS		TSEC_GIGABIT
425 #endif
426 
427 #ifdef CONFIG_TSEC2
428 #define CONFIG_HAS_ETH1
429 #define CONFIG_TSEC2_NAME  "TSEC1"
430 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
431 
432 #define TSEC2_PHY_ADDR		4
433 #define TSEC2_PHYIDX		0
434 #define TSEC2_FLAGS		TSEC_GIGABIT
435 #endif
436 
437 #define CONFIG_ETHPRIME		"Freescale TSEC"
438 
439 #endif
440 
441 /*
442  * Environment
443  */
444 #define CONFIG_ENV_OVERWRITE
445 
446 #ifndef CONFIG_SYS_RAMBOOT
447   #define CONFIG_ENV_IS_IN_FLASH
448   #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
449   #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
450   #define CONFIG_ENV_SIZE		0x2000
451 #else
452   #define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
453   #undef  CONFIG_FLASH_CFI_DRIVER
454   #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
455   #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
456   #define CONFIG_ENV_SIZE		0x2000
457 #endif
458 
459 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
460 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
461 
462 /*
463  * BOOTP options
464  */
465 #define CONFIG_BOOTP_BOOTFILESIZE
466 #define CONFIG_BOOTP_BOOTPATH
467 #define CONFIG_BOOTP_GATEWAY
468 #define CONFIG_BOOTP_HOSTNAME
469 
470 
471 /*
472  * Command line configuration.
473  */
474 #include <config_cmd_default.h>
475 
476 #define CONFIG_CMD_CACHE
477 #define CONFIG_CMD_DATE
478 #define CONFIG_CMD_IRQ
479 #define CONFIG_CMD_NET
480 #define CONFIG_CMD_PING
481 #define CONFIG_CMD_DHCP
482 #define CONFIG_CMD_SDRAM
483 
484 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
485     || defined(CONFIG_USB_STORAGE)
486     #define CONFIG_DOS_PARTITION
487     #define CONFIG_CMD_FAT
488     #define CONFIG_SUPPORT_VFAT
489 #endif
490 
491 #ifdef CONFIG_COMPACT_FLASH
492     #define CONFIG_CMD_IDE
493 #endif
494 
495 #ifdef CONFIG_SATA_SIL3114
496     #define CONFIG_CMD_SATA
497 #endif
498 
499 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
500     #define CONFIG_CMD_EXT2
501 #endif
502 
503 #ifdef CONFIG_PCI
504     #define CONFIG_CMD_PCI
505 #endif
506 
507 #ifdef CONFIG_HARD_I2C
508     #define CONFIG_CMD_I2C
509 #endif
510 
511 /* Watchdog */
512 #undef CONFIG_WATCHDOG		/* watchdog disabled */
513 
514 /*
515  * Miscellaneous configurable options
516  */
517 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
518 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
519 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
520 #define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */
521 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
522 
523 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
524 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
525 
526 #ifdef CONFIG_MPC8349ITX
527 #define CONFIG_SYS_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
528 #else
529 #define CONFIG_SYS_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
530 #endif
531 
532 #if defined(CONFIG_CMD_KGDB)
533     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
534 #else
535     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
536 #endif
537 
538 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
539 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
540 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
541 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
542 
543 /*
544  * For booting Linux, the board info and command line data
545  * have to be in the first 256 MB of memory, since this is
546  * the maximum mapped by the Linux kernel during initialization.
547  */
548 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
549 
550 #define CONFIG_SYS_HRCW_LOW (\
551 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
552 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
553 	HRCWL_CSB_TO_CLKIN_4X1 |\
554 	HRCWL_VCO_1X2 |\
555 	HRCWL_CORE_TO_CSB_2X1)
556 
557 #ifdef CONFIG_SYS_LOWBOOT
558 #define CONFIG_SYS_HRCW_HIGH (\
559 	HRCWH_PCI_HOST |\
560 	HRCWH_32_BIT_PCI |\
561 	HRCWH_PCI1_ARBITER_ENABLE |\
562 	HRCWH_PCI2_ARBITER_ENABLE |\
563 	HRCWH_CORE_ENABLE |\
564 	HRCWH_FROM_0X00000100 |\
565 	HRCWH_BOOTSEQ_DISABLE |\
566 	HRCWH_SW_WATCHDOG_DISABLE |\
567 	HRCWH_ROM_LOC_LOCAL_16BIT |\
568 	HRCWH_TSEC1M_IN_GMII |\
569 	HRCWH_TSEC2M_IN_GMII )
570 #else
571 #define CONFIG_SYS_HRCW_HIGH (\
572 	HRCWH_PCI_HOST |\
573 	HRCWH_32_BIT_PCI |\
574 	HRCWH_PCI1_ARBITER_ENABLE |\
575 	HRCWH_PCI2_ARBITER_ENABLE |\
576 	HRCWH_CORE_ENABLE |\
577 	HRCWH_FROM_0XFFF00100 |\
578 	HRCWH_BOOTSEQ_DISABLE |\
579 	HRCWH_SW_WATCHDOG_DISABLE |\
580 	HRCWH_ROM_LOC_LOCAL_16BIT |\
581 	HRCWH_TSEC1M_IN_GMII |\
582 	HRCWH_TSEC2M_IN_GMII )
583 #endif
584 
585 /*
586  * System performance
587  */
588 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
589 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
590 #define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
591 #define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
592 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
593 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
594 #define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
595 #define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */
596 
597 /*
598  * System IO Config
599  */
600 #define CONFIG_SYS_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
601 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)	/* USB DR as device + USB MPH as host */
602 
603 #define CONFIG_SYS_HID0_INIT	0x00000000
604 #define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_INSTRUCTION_CACHE
605 
606 #define CONFIG_SYS_HID2	HID2_HBE
607 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
608 
609 /* DDR  */
610 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
611 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
612 
613 /* PCI  */
614 #ifdef CONFIG_PCI
615 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
616 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
617 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
618 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
619 #else
620 #define CONFIG_SYS_IBAT1L	0
621 #define CONFIG_SYS_IBAT1U	0
622 #define CONFIG_SYS_IBAT2L	0
623 #define CONFIG_SYS_IBAT2U	0
624 #endif
625 
626 #ifdef CONFIG_MPC83XX_PCI2
627 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
628 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
629 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
630 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
631 #else
632 #define CONFIG_SYS_IBAT3L	0
633 #define CONFIG_SYS_IBAT3U	0
634 #define CONFIG_SYS_IBAT4L	0
635 #define CONFIG_SYS_IBAT4U	0
636 #endif
637 
638 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
639 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
640 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
641 
642 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
643 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
644 				 BATL_GUARDEDSTORAGE)
645 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
646 
647 #define CONFIG_SYS_IBAT7L	0
648 #define CONFIG_SYS_IBAT7U	0
649 
650 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
651 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
652 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
653 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
654 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
655 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
656 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
657 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
658 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
659 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
660 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
661 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
662 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
663 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
664 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
665 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
666 
667 #if defined(CONFIG_CMD_KGDB)
668 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
669 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
670 #endif
671 
672 
673 /*
674  * Environment Configuration
675  */
676 #define CONFIG_ENV_OVERWRITE
677 
678 #define CONFIG_NETDEV		eth0
679 
680 #ifdef CONFIG_MPC8349ITX
681 #define CONFIG_HOSTNAME		mpc8349emitx
682 #else
683 #define CONFIG_HOSTNAME		mpc8349emitxgp
684 #endif
685 
686 /* Default path and filenames */
687 #define CONFIG_ROOTPATH		/nfsroot/rootfs
688 #define CONFIG_BOOTFILE		uImage
689 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
690 
691 #ifdef CONFIG_MPC8349ITX
692 #define CONFIG_FDTFILE		mpc8349emitx.dtb
693 #else
694 #define CONFIG_FDTFILE		mpc8349emitxgp.dtb
695 #endif
696 
697 #define CONFIG_BOOTDELAY	6
698 
699 #define XMK_STR(x)	#x
700 #define MK_STR(x)	XMK_STR(x)
701 
702 #define CONFIG_BOOTARGS \
703 	"root=/dev/nfs rw" \
704 	" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
705 	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":"	\
706 		MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
707 		MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
708 	" console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
709 
710 #define CONFIG_EXTRA_ENV_SETTINGS \
711 	"console=" MK_STR(CONFIG_CONSOLE) "\0"				\
712 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
713 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
714 	"tftpflash=tftpboot $loadaddr $uboot; "				\
715 		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
716 		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
717 		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
718 		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
719 		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
720 	"fdtaddr=780000\0"						\
721 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
722 
723 #define CONFIG_NFSBOOTCOMMAND						\
724 	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
725 	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
726 	" console=$console,$baudrate $othbootargs; "			\
727 	"tftp $loadaddr $bootfile;"					\
728 	"tftp $fdtaddr $fdtfile;"					\
729 	"bootm $loadaddr - $fdtaddr"
730 
731 #define CONFIG_RAMBOOTCOMMAND						\
732 	"setenv bootargs root=/dev/ram rw"				\
733 	" console=$console,$baudrate $othbootargs; "			\
734 	"tftp $ramdiskaddr $ramdiskfile;"				\
735 	"tftp $loadaddr $bootfile;"					\
736 	"tftp $fdtaddr $fdtfile;"					\
737 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
738 
739 #undef MK_STR
740 #undef XMK_STR
741 
742 #endif
743