12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 247a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 347a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 367a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 377a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 387a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 597a78f148STimur Tabi #if (TEXT_BASE == 0xFE000000) 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 617a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 662c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 672ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 682ad6b513STimur Tabi 696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 702ad6b513STimur Tabi 7189c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 7289c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 737a78f148STimur Tabi 7489c7784eSTimur Tabi /* 7589c7784eSTimur Tabi * On-board devices 7689c7784eSTimur Tabi */ 777a78f148STimur Tabi 787a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 792ad6b513STimur Tabi #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 8089c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 81c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 82c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 837a78f148STimur Tabi #endif 847a78f148STimur Tabi 857a78f148STimur Tabi #define CONFIG_PCI 862ad6b513STimur Tabi #define CONFIG_RTC_DS1337 877a78f148STimur Tabi #define CONFIG_HARD_I2C 887a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 897a78f148STimur Tabi 907a78f148STimur Tabi /* 917a78f148STimur Tabi * Device configurations 927a78f148STimur Tabi */ 932ad6b513STimur Tabi 942ad6b513STimur Tabi /* I2C */ 952ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 962ad6b513STimur Tabi 97be5e6181STimur Tabi #define CONFIG_FSL_I2C 982ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 102b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 1032ad6b513STimur Tabi 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 110be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1112ad6b513STimur Tabi 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 1142ad6b513STimur Tabi 1152ad6b513STimur Tabi /* Don't probe these addresses: */ 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2}} 1202ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 1212ad6b513STimur Tabi #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 1222ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1232ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1242ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1252ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1262ad6b513STimur Tabi 1272ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1282ad6b513STimur Tabi 1292ad6b513STimur Tabi #endif 1302ad6b513STimur Tabi 1317a78f148STimur Tabi /* Compact Flash */ 1322ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1332ad6b513STimur Tabi 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1362ad6b513STimur Tabi 1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1432ad6b513STimur Tabi 1442ad6b513STimur Tabi #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 1452ad6b513STimur Tabi 146c9e34fe2SValeriy Glushkov #endif 147c9e34fe2SValeriy Glushkov 148c9e34fe2SValeriy Glushkov /* 149c9e34fe2SValeriy Glushkov * SATA 150c9e34fe2SValeriy Glushkov */ 151c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 152c9e34fe2SValeriy Glushkov 153c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 154c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 155c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1562ad6b513STimur Tabi 1577a78f148STimur Tabi #endif 1582ad6b513STimur Tabi 159c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 160c31e1326SValeriy Glushkov /* 161c31e1326SValeriy Glushkov * Support USB 162c31e1326SValeriy Glushkov */ 163c31e1326SValeriy Glushkov #define CONFIG_CMD_USB 164c31e1326SValeriy Glushkov #define CONFIG_USB_STORAGE 165c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 166c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 167c31e1326SValeriy Glushkov 168c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 169c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 170c31e1326SValeriy Glushkov #if 1 171c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 172c31e1326SValeriy Glushkov #else 173c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 174c31e1326SValeriy Glushkov #endif 175c31e1326SValeriy Glushkov 176c31e1326SValeriy Glushkov #endif 177c31e1326SValeriy Glushkov 1787a78f148STimur Tabi /* 1797a78f148STimur Tabi * DDR Setup 1807a78f148STimur Tabi */ 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1877a78f148STimur Tabi 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 189507e2d79SJoe D'Abbraccio DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 190f64702b7STimur Tabi 191b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 192b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 193b7be63abSValeriy Glushkov 1947a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 1957a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1967a78f148STimur Tabi #endif 1977a78f148STimur Tabi 1987a78f148STimur Tabi #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 2017a78f148STimur Tabi 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 2047a78f148STimur Tabi #endif 2057a78f148STimur Tabi 2067a78f148STimur Tabi /* 2077a78f148STimur Tabi *Flash on the Local Bus 2087a78f148STimur Tabi */ 2097a78f148STimur Tabi 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 21100b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2187a78f148STimur Tabi 2197a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2207a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2277a78f148STimur Tabi 22889c7784eSTimur Tabi /* Vitesse 7385 */ 22989c7784eSTimur Tabi 23089c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 23189c7784eSTimur Tabi 23289c7784eSTimur Tabi #define CONFIG_TSEC2 23389c7784eSTimur Tabi 23489c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 23589c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 23689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 23789c7784eSTimur Tabi 23889c7784eSTimur Tabi #endif 23989c7784eSTimur Tabi 2407a78f148STimur Tabi /* 2417a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2427a78f148STimur Tabi */ 2437a78f148STimur Tabi 2447a78f148STimur Tabi /* Flash */ 2457a78f148STimur Tabi 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 248f9023afbSAnton Vorontsov OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 2497a78f148STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 2506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 2527a78f148STimur Tabi 2537a78f148STimur Tabi /* Vitesse 7385 */ 2547a78f148STimur Tabi 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2567a78f148STimur Tabi 25789c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 25889c7784eSTimur Tabi 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 2617a78f148STimur Tabi OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 2627a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2637a78f148STimur Tabi 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2667a78f148STimur Tabi 2677a78f148STimur Tabi #endif 2687a78f148STimur Tabi 2697a78f148STimur Tabi /* LED */ 2707a78f148STimur Tabi 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 2747a78f148STimur Tabi OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 2757a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2767a78f148STimur Tabi 2777a78f148STimur Tabi /* Compact Flash */ 2787a78f148STimur Tabi 2797a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2807a78f148STimur Tabi 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 2827a78f148STimur Tabi 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2857a78f148STimur Tabi 2866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 2887a78f148STimur Tabi 2897a78f148STimur Tabi #endif 2907a78f148STimur Tabi 2917a78f148STimur Tabi /* 2927a78f148STimur Tabi * U-Boot memory configuration 2937a78f148STimur Tabi */ 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 2952ad6b513STimur Tabi 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 2982ad6b513STimur Tabi #else 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3002ad6b513STimur Tabi #endif 3012ad6b513STimur Tabi 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 3052ad6b513STimur Tabi 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3092ad6b513STimur Tabi 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 3114a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 3126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 3132ad6b513STimur Tabi 3142ad6b513STimur Tabi /* 3152ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3162ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3172ad6b513STimur Tabi * External Local Bus rate is 3182ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3192ad6b513STimur Tabi */ 320*c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 321*c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3232ad6b513STimur Tabi 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 3262ad6b513STimur Tabi 3272ad6b513STimur Tabi /* 3282ad6b513STimur Tabi * Serial Port 3292ad6b513STimur Tabi */ 3302ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3312ad6b513STimur Tabi #undef CONFIG_SERIAL_SOFTWARE_FIFO 3326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3362ad6b513STimur Tabi 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3382ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3392ad6b513STimur Tabi 3408a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3417a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3427a78f148STimur Tabi 3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3452ad6b513STimur Tabi 346bf0b542dSKim Phillips /* pass open firmware flat tree */ 34735cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 3485b8bc606SKim Phillips #define CONFIG_OF_BOARD_SETUP 1 3495b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3502ad6b513STimur Tabi 3517a78f148STimur Tabi /* 3527a78f148STimur Tabi * PCI 3537a78f148STimur Tabi */ 3542ad6b513STimur Tabi #ifdef CONFIG_PCI 3552ad6b513STimur Tabi 3562ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3572ad6b513STimur Tabi 3582ad6b513STimur Tabi /* 3592ad6b513STimur Tabi * General PCI 3602ad6b513STimur Tabi * Addresses are mapped 1-1. 3612ad6b513STimur Tabi */ 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3712ad6b513STimur Tabi 3722ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 3822ad6b513STimur Tabi #endif 3832ad6b513STimur Tabi 3842ad6b513STimur Tabi #define CONFIG_NET_MULTI 3852ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3862ad6b513STimur Tabi 3872ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3882ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 3902ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3912ad6b513STimur Tabi #endif 3922ad6b513STimur Tabi 3932ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3942ad6b513STimur Tabi 3952ad6b513STimur Tabi #endif 3962ad6b513STimur Tabi 3977a78f148STimur Tabi #define PCI_66M 3987a78f148STimur Tabi #ifdef PCI_66M 3997a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4007a78f148STimur Tabi #else 4017a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4027a78f148STimur Tabi #endif 4037a78f148STimur Tabi 4042ad6b513STimur Tabi /* TSEC */ 4052ad6b513STimur Tabi 4062ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4072ad6b513STimur Tabi 4082ad6b513STimur Tabi #define CONFIG_NET_MULTI 4092ad6b513STimur Tabi #define CONFIG_MII 410659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4112ad6b513STimur Tabi 412255a3577SKim Phillips #define CONFIG_TSEC1 4132ad6b513STimur Tabi 414255a3577SKim Phillips #ifdef CONFIG_TSEC1 41510327dc5SAndy Fleming #define CONFIG_HAS_ETH0 416255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4182ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4192ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4203a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4212ad6b513STimur Tabi #endif 4222ad6b513STimur Tabi 423255a3577SKim Phillips #ifdef CONFIG_TSEC2 4247a78f148STimur Tabi #define CONFIG_HAS_ETH1 425255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 42789c7784eSTimur Tabi 4282ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4292ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4303a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4312ad6b513STimur Tabi #endif 4322ad6b513STimur Tabi 4332ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4342ad6b513STimur Tabi 4352ad6b513STimur Tabi #endif 4362ad6b513STimur Tabi 4372ad6b513STimur Tabi /* 4382ad6b513STimur Tabi * Environment 4392ad6b513STimur Tabi */ 4407a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4417a78f148STimur Tabi 4426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4435a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 4446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4450e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4460e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4472ad6b513STimur Tabi #else 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 44900b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 45093f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4520e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4532ad6b513STimur Tabi #endif 4542ad6b513STimur Tabi 4552ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4572ad6b513STimur Tabi 4588ea5499aSJon Loeliger /* 459659e2f67SJon Loeliger * BOOTP options 460659e2f67SJon Loeliger */ 461659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 462659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 463659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 464659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 465659e2f67SJon Loeliger 466659e2f67SJon Loeliger 467659e2f67SJon Loeliger /* 4688ea5499aSJon Loeliger * Command line configuration. 4698ea5499aSJon Loeliger */ 4708ea5499aSJon Loeliger #include <config_cmd_default.h> 4718ea5499aSJon Loeliger 4728ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 4738ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4748ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 4758ea5499aSJon Loeliger #define CONFIG_CMD_NET 4768ea5499aSJon Loeliger #define CONFIG_CMD_PING 477b7be63abSValeriy Glushkov #define CONFIG_CMD_DHCP 4788ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 4792ad6b513STimur Tabi 480c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 481c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 482c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 483c9e34fe2SValeriy Glushkov #define CONFIG_CMD_FAT 484c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 485c9e34fe2SValeriy Glushkov #endif 486c9e34fe2SValeriy Glushkov 4872ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 4888ea5499aSJon Loeliger #define CONFIG_CMD_IDE 489c9e34fe2SValeriy Glushkov #endif 490c9e34fe2SValeriy Glushkov 491c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 492c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 493c31e1326SValeriy Glushkov #endif 494c31e1326SValeriy Glushkov 495c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 496c9e34fe2SValeriy Glushkov #define CONFIG_CMD_EXT2 4972ad6b513STimur Tabi #endif 4982ad6b513STimur Tabi 4992ad6b513STimur Tabi #ifdef CONFIG_PCI 5008ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5012ad6b513STimur Tabi #endif 5022ad6b513STimur Tabi 5032ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 5048ea5499aSJon Loeliger #define CONFIG_CMD_I2C 5052ad6b513STimur Tabi #endif 5062ad6b513STimur Tabi 5072ad6b513STimur Tabi /* Watchdog */ 5082ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5092ad6b513STimur Tabi 5102ad6b513STimur Tabi /* 5112ad6b513STimur Tabi * Miscellaneous configurable options 5122ad6b513STimur Tabi */ 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5147a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 5166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 5177a78f148STimur Tabi 5186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 51905f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5207a78f148STimur Tabi 5217a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5237a78f148STimur Tabi #else 5246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 5257a78f148STimur Tabi #endif 5262ad6b513STimur Tabi 5278ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5292ad6b513STimur Tabi #else 5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5312ad6b513STimur Tabi #endif 5322ad6b513STimur Tabi 5336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 5366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 5372ad6b513STimur Tabi 5382ad6b513STimur Tabi /* 5392ad6b513STimur Tabi * For booting Linux, the board info and command line data 5402ad6b513STimur Tabi * have to be in the first 8 MB of memory, since this is 5412ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5422ad6b513STimur Tabi */ 5436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 5442ad6b513STimur Tabi 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5462ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5472ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5482ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5492ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5502ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5512ad6b513STimur Tabi 5526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5542ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5557a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5562ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5577a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5582ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5592ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5602ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5612ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5622ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5632ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5642ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5652ad6b513STimur Tabi #else 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5672ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5682ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5692ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5707a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5712ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5722ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5732ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5742ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5752ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5762ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5772ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5782ad6b513STimur Tabi #endif 5792ad6b513STimur Tabi 5807a78f148STimur Tabi /* 5817a78f148STimur Tabi * System performance 5827a78f148STimur Tabi */ 5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 589c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 590c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 5912ad6b513STimur Tabi 5927a78f148STimur Tabi /* 5937a78f148STimur Tabi * System IO Config 5947a78f148STimur Tabi */ 5956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 596c31e1326SValeriy Glushkov #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */ 5972ad6b513STimur Tabi 5986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT 6002ad6b513STimur Tabi 6016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 60231d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6032ad6b513STimur Tabi 6047a78f148STimur Tabi /* DDR */ 6056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6072ad6b513STimur Tabi 6087a78f148STimur Tabi /* PCI */ 6092ad6b513STimur Tabi #ifdef CONFIG_PCI 6106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6142ad6b513STimur Tabi #else 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6192ad6b513STimur Tabi #endif 6202ad6b513STimur Tabi 6212ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6262ad6b513STimur Tabi #else 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 6286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 6312ad6b513STimur Tabi #endif 6322ad6b513STimur Tabi 6332ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 6362ad6b513STimur Tabi 6372ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 638c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 639c1230980SScott Wood BATL_GUARDEDSTORAGE) 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 6412ad6b513STimur Tabi 6426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6442ad6b513STimur Tabi 6456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 6612ad6b513STimur Tabi 6622ad6b513STimur Tabi /* 6632ad6b513STimur Tabi * Internal Definitions 6642ad6b513STimur Tabi * 6652ad6b513STimur Tabi * Boot Flags 6662ad6b513STimur Tabi */ 6672ad6b513STimur Tabi #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 6682ad6b513STimur Tabi #define BOOTFLAG_WARM 0x02 /* Software reboot */ 6692ad6b513STimur Tabi 6708ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 6712ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6722ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 6732ad6b513STimur Tabi #endif 6742ad6b513STimur Tabi 6752ad6b513STimur Tabi 6762ad6b513STimur Tabi /* 6772ad6b513STimur Tabi * Environment Configuration 6782ad6b513STimur Tabi */ 6792ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6802ad6b513STimur Tabi 68189c7784eSTimur Tabi #ifdef CONFIG_HAS_ETH0 6822ad6b513STimur Tabi #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 6832ad6b513STimur Tabi #endif 6842ad6b513STimur Tabi 68589c7784eSTimur Tabi #ifdef CONFIG_HAS_ETH1 6862ad6b513STimur Tabi #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 6872ad6b513STimur Tabi #endif 6882ad6b513STimur Tabi 689bf0b542dSKim Phillips #define CONFIG_IPADDR 192.168.1.253 690bf0b542dSKim Phillips #define CONFIG_SERVERIP 192.168.1.1 691bf0b542dSKim Phillips #define CONFIG_GATEWAYIP 192.168.1.1 6922ad6b513STimur Tabi #define CONFIG_NETMASK 255.255.252.0 69398883332STimur Tabi #define CONFIG_NETDEV eth0 6942ad6b513STimur Tabi 6957a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6962ad6b513STimur Tabi #define CONFIG_HOSTNAME mpc8349emitx 6977a78f148STimur Tabi #else 6987a78f148STimur Tabi #define CONFIG_HOSTNAME mpc8349emitxgp 6997a78f148STimur Tabi #endif 7007a78f148STimur Tabi 7017a78f148STimur Tabi /* Default path and filenames */ 702bf0b542dSKim Phillips #define CONFIG_ROOTPATH /nfsroot/rootfs 703bf0b542dSKim Phillips #define CONFIG_BOOTFILE uImage 7047a78f148STimur Tabi #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 7052ad6b513STimur Tabi 7067a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 7077a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitx.dtb 7082ad6b513STimur Tabi #else 7097a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitxgp.dtb 7102ad6b513STimur Tabi #endif 7112ad6b513STimur Tabi 71205f91a65SKim Phillips #define CONFIG_BOOTDELAY 6 7137a78f148STimur Tabi 7142ad6b513STimur Tabi #define XMK_STR(x) #x 7152ad6b513STimur Tabi #define MK_STR(x) XMK_STR(x) 7162ad6b513STimur Tabi 71798883332STimur Tabi #define CONFIG_BOOTARGS \ 71898883332STimur Tabi "root=/dev/nfs rw" \ 71998883332STimur Tabi " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 72098883332STimur Tabi " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 72198883332STimur Tabi MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 72298883332STimur Tabi MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 7238a364f09SNikita V. Youshchenko " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 72498883332STimur Tabi 7252ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 7268a364f09SNikita V. Youshchenko "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 72798883332STimur Tabi "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 7287a78f148STimur Tabi "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 7297a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 7307a78f148STimur Tabi "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 7317a78f148STimur Tabi "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 7327a78f148STimur Tabi "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 7337a78f148STimur Tabi "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 7347a78f148STimur Tabi "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 73505f91a65SKim Phillips "fdtaddr=780000\0" \ 7367a78f148STimur Tabi "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 737bf0b542dSKim Phillips 738bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 7397a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 740bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 7417a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 742bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 743bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 744bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 745bf0b542dSKim Phillips 746bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 747bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 7487a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 749bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 750bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 751bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 752bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 7532ad6b513STimur Tabi 7542ad6b513STimur Tabi #undef MK_STR 7552ad6b513STimur Tabi #undef XMK_STR 7562ad6b513STimur Tabi 7572ad6b513STimur Tabi #endif 758