12ad6b513STimur Tabi /* 22ad6b513STimur Tabi * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 247a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 347a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 367a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 377a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 387a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 597a78f148STimur Tabi #if (TEXT_BASE == 0xFE000000) 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 617a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 662ad6b513STimur Tabi #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 672ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 682ad6b513STimur Tabi 696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 702ad6b513STimur Tabi 7189c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 7289c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 737a78f148STimur Tabi 7489c7784eSTimur Tabi /* 7589c7784eSTimur Tabi * On-board devices 7689c7784eSTimur Tabi */ 777a78f148STimur Tabi 787a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 792ad6b513STimur Tabi #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 8089c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 81c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 827a78f148STimur Tabi #endif 837a78f148STimur Tabi 847a78f148STimur Tabi #define CONFIG_PCI 852ad6b513STimur Tabi #define CONFIG_RTC_DS1337 867a78f148STimur Tabi #define CONFIG_HARD_I2C 877a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 887a78f148STimur Tabi 897a78f148STimur Tabi /* 907a78f148STimur Tabi * Device configurations 917a78f148STimur Tabi */ 922ad6b513STimur Tabi 932ad6b513STimur Tabi /* I2C */ 942ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 952ad6b513STimur Tabi 96be5e6181STimur Tabi #define CONFIG_FSL_I2C 972ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 982ad6b513STimur Tabi #define CONFIG_I2C_CMD_TREE 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 102b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 1032ad6b513STimur Tabi 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 110be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1112ad6b513STimur Tabi 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 1142ad6b513STimur Tabi 1152ad6b513STimur Tabi /* Don't probe these addresses: */ 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2}} 1202ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 1212ad6b513STimur Tabi #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 1222ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1232ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1242ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1252ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1262ad6b513STimur Tabi 1272ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1282ad6b513STimur Tabi 1292ad6b513STimur Tabi #endif 1302ad6b513STimur Tabi 1317a78f148STimur Tabi /* Compact Flash */ 1322ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1332ad6b513STimur Tabi 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1362ad6b513STimur Tabi 1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1432ad6b513STimur Tabi 1442ad6b513STimur Tabi #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 1452ad6b513STimur Tabi 146c9e34fe2SValeriy Glushkov #endif 147c9e34fe2SValeriy Glushkov 148c9e34fe2SValeriy Glushkov /* 149c9e34fe2SValeriy Glushkov * SATA 150c9e34fe2SValeriy Glushkov */ 151c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 152c9e34fe2SValeriy Glushkov 153c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 154c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 155c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1562ad6b513STimur Tabi 1577a78f148STimur Tabi #endif 1582ad6b513STimur Tabi 1597a78f148STimur Tabi /* 1607a78f148STimur Tabi * DDR Setup 1617a78f148STimur Tabi */ 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1687a78f148STimur Tabi 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 170507e2d79SJoe D'Abbraccio DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 171f64702b7STimur Tabi 172b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 173b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 174b7be63abSValeriy Glushkov 1757a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 1767a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1777a78f148STimur Tabi #endif 1787a78f148STimur Tabi 1797a78f148STimur Tabi #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 1827a78f148STimur Tabi 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1857a78f148STimur Tabi #endif 1867a78f148STimur Tabi 1877a78f148STimur Tabi /* 1887a78f148STimur Tabi *Flash on the Local Bus 1897a78f148STimur Tabi */ 1907a78f148STimur Tabi 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 19200b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 1997a78f148STimur Tabi 2007a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2017a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2087a78f148STimur Tabi 20989c7784eSTimur Tabi /* Vitesse 7385 */ 21089c7784eSTimur Tabi 21189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 21289c7784eSTimur Tabi 21389c7784eSTimur Tabi #define CONFIG_TSEC2 21489c7784eSTimur Tabi 21589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 21689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 21789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 21889c7784eSTimur Tabi 21989c7784eSTimur Tabi #endif 22089c7784eSTimur Tabi 2217a78f148STimur Tabi /* 2227a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2237a78f148STimur Tabi */ 2247a78f148STimur Tabi 2257a78f148STimur Tabi /* Flash */ 2267a78f148STimur Tabi 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 229f9023afbSAnton Vorontsov OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 2307a78f148STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 2337a78f148STimur Tabi 2347a78f148STimur Tabi /* Vitesse 7385 */ 2357a78f148STimur Tabi 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2377a78f148STimur Tabi 23889c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 23989c7784eSTimur Tabi 2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 2427a78f148STimur Tabi OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 2437a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2447a78f148STimur Tabi 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2477a78f148STimur Tabi 2487a78f148STimur Tabi #endif 2497a78f148STimur Tabi 2507a78f148STimur Tabi /* LED */ 2517a78f148STimur Tabi 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 2546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 2557a78f148STimur Tabi OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 2567a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2577a78f148STimur Tabi 2587a78f148STimur Tabi /* Compact Flash */ 2597a78f148STimur Tabi 2607a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2617a78f148STimur Tabi 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 2637a78f148STimur Tabi 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2667a78f148STimur Tabi 2676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 2686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 2697a78f148STimur Tabi 2707a78f148STimur Tabi #endif 2717a78f148STimur Tabi 2727a78f148STimur Tabi /* 2737a78f148STimur Tabi * U-Boot memory configuration 2747a78f148STimur Tabi */ 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 2762ad6b513STimur Tabi 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 2792ad6b513STimur Tabi #else 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 2812ad6b513STimur Tabi #endif 2822ad6b513STimur Tabi 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 2856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 2862ad6b513STimur Tabi 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 2886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 2902ad6b513STimur Tabi 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 2942ad6b513STimur Tabi 2952ad6b513STimur Tabi /* 2962ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 2972ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 2982ad6b513STimur Tabi * External Local Bus rate is 2992ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3002ad6b513STimur Tabi */ 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3032ad6b513STimur Tabi 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 3062ad6b513STimur Tabi 3072ad6b513STimur Tabi /* 3082ad6b513STimur Tabi * Serial Port 3092ad6b513STimur Tabi */ 3102ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3112ad6b513STimur Tabi #undef CONFIG_SERIAL_SOFTWARE_FIFO 3126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3162ad6b513STimur Tabi 3176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3182ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3192ad6b513STimur Tabi 3208a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3217a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3227a78f148STimur Tabi 3236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3252ad6b513STimur Tabi 326bf0b542dSKim Phillips /* pass open firmware flat tree */ 32735cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 3285b8bc606SKim Phillips #define CONFIG_OF_BOARD_SETUP 1 3295b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3302ad6b513STimur Tabi 3317a78f148STimur Tabi /* 3327a78f148STimur Tabi * PCI 3337a78f148STimur Tabi */ 3342ad6b513STimur Tabi #ifdef CONFIG_PCI 3352ad6b513STimur Tabi 3362ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3372ad6b513STimur Tabi 3382ad6b513STimur Tabi /* 3392ad6b513STimur Tabi * General PCI 3402ad6b513STimur Tabi * Addresses are mapped 1-1. 3412ad6b513STimur Tabi */ 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3512ad6b513STimur Tabi 3522ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 3566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 3616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 3622ad6b513STimur Tabi #endif 3632ad6b513STimur Tabi 3642ad6b513STimur Tabi #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 3652ad6b513STimur Tabi 3662ad6b513STimur Tabi #define CONFIG_NET_MULTI 3672ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3682ad6b513STimur Tabi 3692ad6b513STimur Tabi #ifdef CONFIG_RTL8139 3702ad6b513STimur Tabi /* This macro is used by RTL8139 but not defined in PPC architecture */ 3712ad6b513STimur Tabi #define KSEG1ADDR(x) (x) 3722ad6b513STimur Tabi #endif 3732ad6b513STimur Tabi 3742ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3752ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 3772ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3782ad6b513STimur Tabi #endif 3792ad6b513STimur Tabi 3802ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3812ad6b513STimur Tabi 3822ad6b513STimur Tabi #endif 3832ad6b513STimur Tabi 3847a78f148STimur Tabi #define PCI_66M 3857a78f148STimur Tabi #ifdef PCI_66M 3867a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 3877a78f148STimur Tabi #else 3887a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 3897a78f148STimur Tabi #endif 3907a78f148STimur Tabi 3912ad6b513STimur Tabi /* TSEC */ 3922ad6b513STimur Tabi 3932ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 3942ad6b513STimur Tabi 3952ad6b513STimur Tabi #define CONFIG_NET_MULTI 3962ad6b513STimur Tabi #define CONFIG_MII 397659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 3982ad6b513STimur Tabi 399255a3577SKim Phillips #define CONFIG_TSEC1 4002ad6b513STimur Tabi 401255a3577SKim Phillips #ifdef CONFIG_TSEC1 40210327dc5SAndy Fleming #define CONFIG_HAS_ETH0 403255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4052ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4062ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4073a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4082ad6b513STimur Tabi #endif 4092ad6b513STimur Tabi 410255a3577SKim Phillips #ifdef CONFIG_TSEC2 4117a78f148STimur Tabi #define CONFIG_HAS_ETH1 412255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 41489c7784eSTimur Tabi 4152ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4162ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4173a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4182ad6b513STimur Tabi #endif 4192ad6b513STimur Tabi 4202ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4212ad6b513STimur Tabi 4222ad6b513STimur Tabi #endif 4232ad6b513STimur Tabi 4242ad6b513STimur Tabi /* 4252ad6b513STimur Tabi * Environment 4262ad6b513STimur Tabi */ 4277a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4287a78f148STimur Tabi 4296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4305a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 4316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4320e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4330e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4342ad6b513STimur Tabi #else 4356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 43600b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 43793f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4390e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4402ad6b513STimur Tabi #endif 4412ad6b513STimur Tabi 4422ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4442ad6b513STimur Tabi 4458ea5499aSJon Loeliger /* 446659e2f67SJon Loeliger * BOOTP options 447659e2f67SJon Loeliger */ 448659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 449659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 450659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 451659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 452659e2f67SJon Loeliger 453659e2f67SJon Loeliger 454659e2f67SJon Loeliger /* 4558ea5499aSJon Loeliger * Command line configuration. 4568ea5499aSJon Loeliger */ 4578ea5499aSJon Loeliger #include <config_cmd_default.h> 4588ea5499aSJon Loeliger 4598ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 4608ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4618ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 4628ea5499aSJon Loeliger #define CONFIG_CMD_NET 4638ea5499aSJon Loeliger #define CONFIG_CMD_PING 464b7be63abSValeriy Glushkov #define CONFIG_CMD_DHCP 4658ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 4662ad6b513STimur Tabi 467c9e34fe2SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) 468c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 469c9e34fe2SValeriy Glushkov #define CONFIG_CMD_FAT 470c9e34fe2SValeriy Glushkov #endif 471c9e34fe2SValeriy Glushkov 4722ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 4738ea5499aSJon Loeliger #define CONFIG_CMD_IDE 474c9e34fe2SValeriy Glushkov #endif 475c9e34fe2SValeriy Glushkov 476c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 477c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 478c9e34fe2SValeriy Glushkov #define CONFIG_CMD_EXT2 4792ad6b513STimur Tabi #endif 4802ad6b513STimur Tabi 4812ad6b513STimur Tabi #ifdef CONFIG_PCI 4828ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4832ad6b513STimur Tabi #endif 4842ad6b513STimur Tabi 4852ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 4868ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4872ad6b513STimur Tabi #endif 4882ad6b513STimur Tabi 4892ad6b513STimur Tabi /* Watchdog */ 4902ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 4912ad6b513STimur Tabi 4922ad6b513STimur Tabi /* 4932ad6b513STimur Tabi * Miscellaneous configurable options 4942ad6b513STimur Tabi */ 4956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4967a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 4976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 4986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 4997a78f148STimur Tabi 5006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 501b2115757SKim Phillips #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 5027a78f148STimur Tabi 5037a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 5046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5057a78f148STimur Tabi #else 5066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 5077a78f148STimur Tabi #endif 5082ad6b513STimur Tabi 5098ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5112ad6b513STimur Tabi #else 5126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5132ad6b513STimur Tabi #endif 5142ad6b513STimur Tabi 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 5166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 5176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 5186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 5192ad6b513STimur Tabi 5202ad6b513STimur Tabi /* 5212ad6b513STimur Tabi * For booting Linux, the board info and command line data 5222ad6b513STimur Tabi * have to be in the first 8 MB of memory, since this is 5232ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5242ad6b513STimur Tabi */ 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 5262ad6b513STimur Tabi 5276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5282ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5292ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5302ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5312ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5322ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5332ad6b513STimur Tabi 5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5362ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5377a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5382ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5397a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5402ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5412ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5422ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5432ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5442ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5452ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5462ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5472ad6b513STimur Tabi #else 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5492ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5502ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5512ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5527a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5532ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5542ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5552ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5562ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5572ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5582ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5592ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5602ad6b513STimur Tabi #endif 5612ad6b513STimur Tabi 5627a78f148STimur Tabi /* 5637a78f148STimur Tabi * System performance 5647a78f148STimur Tabi */ 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 5712ad6b513STimur Tabi 5727a78f148STimur Tabi /* 5737a78f148STimur Tabi * System IO Config 5747a78f148STimur Tabi */ 5756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 5772ad6b513STimur Tabi 5786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT 5802ad6b513STimur Tabi 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 58231d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 5832ad6b513STimur Tabi 5847a78f148STimur Tabi /* DDR */ 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5872ad6b513STimur Tabi 5887a78f148STimur Tabi /* PCI */ 5892ad6b513STimur Tabi #ifdef CONFIG_PCI 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5942ad6b513STimur Tabi #else 5956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 5966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 5976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 5986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 5992ad6b513STimur Tabi #endif 6002ad6b513STimur Tabi 6012ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 6026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6062ad6b513STimur Tabi #else 6076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 6086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 6096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 6106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 6112ad6b513STimur Tabi #endif 6122ad6b513STimur Tabi 6132ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 6146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 6162ad6b513STimur Tabi 6172ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 618*c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 619*c1230980SScott Wood BATL_GUARDEDSTORAGE) 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 6212ad6b513STimur Tabi 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6242ad6b513STimur Tabi 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 6412ad6b513STimur Tabi 6422ad6b513STimur Tabi /* 6432ad6b513STimur Tabi * Internal Definitions 6442ad6b513STimur Tabi * 6452ad6b513STimur Tabi * Boot Flags 6462ad6b513STimur Tabi */ 6472ad6b513STimur Tabi #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 6482ad6b513STimur Tabi #define BOOTFLAG_WARM 0x02 /* Software reboot */ 6492ad6b513STimur Tabi 6508ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 6512ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6522ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 6532ad6b513STimur Tabi #endif 6542ad6b513STimur Tabi 6552ad6b513STimur Tabi 6562ad6b513STimur Tabi /* 6572ad6b513STimur Tabi * Environment Configuration 6582ad6b513STimur Tabi */ 6592ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6602ad6b513STimur Tabi 66189c7784eSTimur Tabi #ifdef CONFIG_HAS_ETH0 6622ad6b513STimur Tabi #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 6632ad6b513STimur Tabi #endif 6642ad6b513STimur Tabi 66589c7784eSTimur Tabi #ifdef CONFIG_HAS_ETH1 6662ad6b513STimur Tabi #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 6672ad6b513STimur Tabi #endif 6682ad6b513STimur Tabi 669bf0b542dSKim Phillips #define CONFIG_IPADDR 192.168.1.253 670bf0b542dSKim Phillips #define CONFIG_SERVERIP 192.168.1.1 671bf0b542dSKim Phillips #define CONFIG_GATEWAYIP 192.168.1.1 6722ad6b513STimur Tabi #define CONFIG_NETMASK 255.255.252.0 67398883332STimur Tabi #define CONFIG_NETDEV eth0 6742ad6b513STimur Tabi 6757a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6762ad6b513STimur Tabi #define CONFIG_HOSTNAME mpc8349emitx 6777a78f148STimur Tabi #else 6787a78f148STimur Tabi #define CONFIG_HOSTNAME mpc8349emitxgp 6797a78f148STimur Tabi #endif 6807a78f148STimur Tabi 6817a78f148STimur Tabi /* Default path and filenames */ 682bf0b542dSKim Phillips #define CONFIG_ROOTPATH /nfsroot/rootfs 683bf0b542dSKim Phillips #define CONFIG_BOOTFILE uImage 6847a78f148STimur Tabi #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 6852ad6b513STimur Tabi 6867a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6877a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitx.dtb 6882ad6b513STimur Tabi #else 6897a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitxgp.dtb 6902ad6b513STimur Tabi #endif 6912ad6b513STimur Tabi 6927a78f148STimur Tabi #define CONFIG_BOOTDELAY 0 6937a78f148STimur Tabi 6942ad6b513STimur Tabi #define XMK_STR(x) #x 6952ad6b513STimur Tabi #define MK_STR(x) XMK_STR(x) 6962ad6b513STimur Tabi 69798883332STimur Tabi #define CONFIG_BOOTARGS \ 69898883332STimur Tabi "root=/dev/nfs rw" \ 69998883332STimur Tabi " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 70098883332STimur Tabi " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 70198883332STimur Tabi MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 70298883332STimur Tabi MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 7038a364f09SNikita V. Youshchenko " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 70498883332STimur Tabi 7052ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 7068a364f09SNikita V. Youshchenko "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 70798883332STimur Tabi "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 7087a78f148STimur Tabi "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 7097a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 7107a78f148STimur Tabi "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 7117a78f148STimur Tabi "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 7127a78f148STimur Tabi "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 7137a78f148STimur Tabi "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 7147a78f148STimur Tabi "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 715bf0b542dSKim Phillips "fdtaddr=400000\0" \ 7167a78f148STimur Tabi "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 717bf0b542dSKim Phillips 718bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 7197a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 720bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 7217a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 722bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 723bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 724bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 725bf0b542dSKim Phillips 726bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 727bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 7287a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 729bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 730bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 731bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 732bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 7332ad6b513STimur Tabi 7342ad6b513STimur Tabi #undef MK_STR 7352ad6b513STimur Tabi #undef XMK_STR 7362ad6b513STimur Tabi 7372ad6b513STimur Tabi #endif 738