12ad6b513STimur Tabi /* 22ad6b513STimur Tabi * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 242ad6b513STimur Tabi MPC8349E-mITX board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 342ad6b513STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 362ad6b513STimur Tabi 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 372ad6b513STimur Tabi 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) 382ad6b513STimur Tabi 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 442ad6b513STimur Tabi I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 462ad6b513STimur Tabi I2C2 0x20 PCF8574 I2C Expander 0 U8 472ad6b513STimur Tabi I2C2 0x21 PCF8574 I2C Expander 0 U10 482ad6b513STimur Tabi I2C2 0x38 PCF8574A I2C Expander 0 U8 492ad6b513STimur Tabi I2C2 0x39 PCF8574A I2C Expander 0 U10 502ad6b513STimur Tabi I2C2 0x51 (DDR) DDR EEPROM 1 U1 512ad6b513STimur Tabi I2C2 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 592ad6b513STimur Tabi #undef DEBUG 602ad6b513STimur Tabi 612ad6b513STimur Tabi /* 622ad6b513STimur Tabi * High Level Configuration Options 632ad6b513STimur Tabi */ 642ad6b513STimur Tabi #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 652ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 662ad6b513STimur Tabi 672ad6b513STimur Tabi #define CONFIG_PCI 682ad6b513STimur Tabi 692ad6b513STimur Tabi #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 702ad6b513STimur Tabi #define CONFIG_RTC_DS1337 712ad6b513STimur Tabi 722ad6b513STimur Tabi /* I2C */ 732ad6b513STimur Tabi #define CONFIG_HARD_I2C 742ad6b513STimur Tabi 752ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 762ad6b513STimur Tabi 772ad6b513STimur Tabi #define CONFIG_MISC_INIT_F 782ad6b513STimur Tabi #define CONFIG_MISC_INIT_R 792ad6b513STimur Tabi 802ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 812ad6b513STimur Tabi #define CONFIG_I2C_CMD_TREE 822ad6b513STimur Tabi #define CFG_I2C_OFFSET 0x3000 832ad6b513STimur Tabi #define CFG_I2C2_OFFSET 0x3100 84*9ca880a2STimur Tabi #define CFG_SPD_BUS_NUM 2 852ad6b513STimur Tabi 862ad6b513STimur Tabi #define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ 872ad6b513STimur Tabi #define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ 882ad6b513STimur Tabi #define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */ 892ad6b513STimur Tabi #define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */ 902ad6b513STimur Tabi #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */ 912ad6b513STimur Tabi #define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/ 922ad6b513STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */ 932ad6b513STimur Tabi 942ad6b513STimur Tabi #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 952ad6b513STimur Tabi #define CFG_I2C_SLAVE 0x7F 962ad6b513STimur Tabi 972ad6b513STimur Tabi /* Don't probe these addresses: */ 982ad6b513STimur Tabi #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ 992ad6b513STimur Tabi {1, CFG_I2C_8574_ADDR2}, \ 1002ad6b513STimur Tabi {1, CFG_I2C_8574A_ADDR1}, \ 1012ad6b513STimur Tabi {1, CFG_I2C_8574A_ADDR2}} 1022ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 1032ad6b513STimur Tabi #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 1042ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1052ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1062ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1072ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1082ad6b513STimur Tabi 1092ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1102ad6b513STimur Tabi 1112ad6b513STimur Tabi #endif 1122ad6b513STimur Tabi 1132ad6b513STimur Tabi #define CONFIG_TSEC_ENET /* tsec ethernet support */ 1142ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 1152ad6b513STimur Tabi 1162ad6b513STimur Tabi #define PCI_66M 1172ad6b513STimur Tabi #ifdef PCI_66M 1182ad6b513STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 1192ad6b513STimur Tabi #else 1202ad6b513STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 1212ad6b513STimur Tabi #endif 1222ad6b513STimur Tabi 1232ad6b513STimur Tabi #ifndef CONFIG_SYS_CLK_FREQ 1242ad6b513STimur Tabi #ifdef PCI_66M 1252ad6b513STimur Tabi #define CONFIG_SYS_CLK_FREQ 66666666 1262ad6b513STimur Tabi #else 1272ad6b513STimur Tabi #define CONFIG_SYS_CLK_FREQ 33333333 1282ad6b513STimur Tabi #endif 1292ad6b513STimur Tabi #endif 1302ad6b513STimur Tabi 1312ad6b513STimur Tabi #define CFG_IMMRBAR 0xE0000000 /* The IMMR is relocated to here */ 1322ad6b513STimur Tabi 1332ad6b513STimur Tabi #undef CFG_DRAM_TEST /* memory test, takes time */ 1342ad6b513STimur Tabi #define CFG_MEMTEST_START 0x00003000 /* memtest region */ 1352ad6b513STimur Tabi #define CFG_MEMTEST_END 0x07100000 /* only has 128M */ 1362ad6b513STimur Tabi 1372ad6b513STimur Tabi /* 1382ad6b513STimur Tabi * DDR Setup 1392ad6b513STimur Tabi */ 1402ad6b513STimur Tabi #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 1412ad6b513STimur Tabi #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 1422ad6b513STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1432ad6b513STimur Tabi 1442ad6b513STimur Tabi /* 1452ad6b513STimur Tabi * 32-bit data path mode. 1462ad6b513STimur Tabi * 1472ad6b513STimur Tabi * Please note that using this mode for devices with the real density of 64-bit 1482ad6b513STimur Tabi * effectively reduces the amount of available memory due to the effect of 1492ad6b513STimur Tabi * wrapping around while translating address to row/columns, for example in the 1502ad6b513STimur Tabi * 256MB module the upper 128MB get aliased with contents of the lower 1512ad6b513STimur Tabi * 128MB); normally this define should be used for devices with real 32-bit 1522ad6b513STimur Tabi * data path. 1532ad6b513STimur Tabi */ 1542ad6b513STimur Tabi #undef CONFIG_DDR_32BIT 1552ad6b513STimur Tabi 1562ad6b513STimur Tabi #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 1572ad6b513STimur Tabi #define CFG_SDRAM_BASE CFG_DDR_BASE 1582ad6b513STimur Tabi #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 1592ad6b513STimur Tabi #undef CONFIG_DDR_2T_TIMING 1602ad6b513STimur Tabi #define CFG_83XX_DDR_USES_CS0 1612ad6b513STimur Tabi 1622ad6b513STimur Tabi #ifndef CONFIG_SPD_EEPROM 1632ad6b513STimur Tabi /* 1642ad6b513STimur Tabi * Manually set up DDR parameters 1652ad6b513STimur Tabi */ 1662ad6b513STimur Tabi #define CFG_DDR_SIZE 256 /* Mb */ 1672ad6b513STimur Tabi #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 1682ad6b513STimur Tabi 1692ad6b513STimur Tabi #define CFG_DDR_TIMING_1 0x26242321 1702ad6b513STimur Tabi #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1712ad6b513STimur Tabi #endif 1722ad6b513STimur Tabi 1732ad6b513STimur Tabi /* FLASH on the Local Bus */ 1742ad6b513STimur Tabi #define CFG_FLASH_CFI /* use the Common Flash Interface */ 1752ad6b513STimur Tabi #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 1762ad6b513STimur Tabi #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 1772ad6b513STimur Tabi #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ 1782ad6b513STimur Tabi 1792ad6b513STimur Tabi #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) 1802ad6b513STimur Tabi #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 1812ad6b513STimur Tabi OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 1822ad6b513STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 1832ad6b513STimur Tabi #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 1842ad6b513STimur Tabi #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ 1852ad6b513STimur Tabi 1862ad6b513STimur Tabi /* VSC7385 on the Local Bus */ 1872ad6b513STimur Tabi #define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ 1882ad6b513STimur Tabi 1892ad6b513STimur Tabi #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) 1902ad6b513STimur Tabi #define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ 1912ad6b513STimur Tabi OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 1922ad6b513STimur Tabi OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 1932ad6b513STimur Tabi 1942ad6b513STimur Tabi #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ 1952ad6b513STimur Tabi #define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ 1962ad6b513STimur Tabi 1972ad6b513STimur Tabi #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 1982ad6b513STimur Tabi #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 1992ad6b513STimur Tabi 2002ad6b513STimur Tabi #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} 2012ad6b513STimur Tabi 2022ad6b513STimur Tabi #undef CFG_FLASH_CHECKSUM 2032ad6b513STimur Tabi #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2042ad6b513STimur Tabi #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2052ad6b513STimur Tabi 2062ad6b513STimur Tabi #define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ 2072ad6b513STimur Tabi #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) 2082ad6b513STimur Tabi #define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ 2092ad6b513STimur Tabi OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ 2102ad6b513STimur Tabi OR_GPCM_SCY_9 | \ 2112ad6b513STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 2122ad6b513STimur Tabi 2132ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2142ad6b513STimur Tabi 2152ad6b513STimur Tabi #define CFG_CF_BASE 0xF0000000 2162ad6b513STimur Tabi 2172ad6b513STimur Tabi #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 2182ad6b513STimur Tabi #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2192ad6b513STimur Tabi 2202ad6b513STimur Tabi #define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ 2212ad6b513STimur Tabi #define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ 2222ad6b513STimur Tabi 2232ad6b513STimur Tabi #undef CONFIG_IDE_RESET 2242ad6b513STimur Tabi #undef CONFIG_IDE_PREINIT 2252ad6b513STimur Tabi 2262ad6b513STimur Tabi #define CFG_IDE_MAXBUS 1 2272ad6b513STimur Tabi #define CFG_IDE_MAXDEVICE 1 2282ad6b513STimur Tabi 2292ad6b513STimur Tabi #define CFG_ATA_IDE0_OFFSET 0x0000 2302ad6b513STimur Tabi #define CFG_ATA_BASE_ADDR CFG_CF_BASE 2312ad6b513STimur Tabi #define CFG_ATA_DATA_OFFSET 0x0000 2322ad6b513STimur Tabi #define CFG_ATA_REG_OFFSET 0 2332ad6b513STimur Tabi #define CFG_ATA_ALT_OFFSET 0x0200 2342ad6b513STimur Tabi #define CFG_ATA_STRIDE 2 2352ad6b513STimur Tabi 2362ad6b513STimur Tabi #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 2372ad6b513STimur Tabi 2382ad6b513STimur Tabi #endif 2392ad6b513STimur Tabi 2402ad6b513STimur Tabi #define CONFIG_DOS_PARTITION 2412ad6b513STimur Tabi 2422ad6b513STimur Tabi #define CFG_MID_FLASH_JUMP 0x7F000000 2432ad6b513STimur Tabi #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 2442ad6b513STimur Tabi 2452ad6b513STimur Tabi 2462ad6b513STimur Tabi #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 2472ad6b513STimur Tabi #define CFG_RAMBOOT 2482ad6b513STimur Tabi #else 2492ad6b513STimur Tabi #undef CFG_RAMBOOT 2502ad6b513STimur Tabi #endif 2512ad6b513STimur Tabi 2522ad6b513STimur Tabi #define CONFIG_L1_INIT_RAM 2532ad6b513STimur Tabi #define CFG_INIT_RAM_LOCK 2542ad6b513STimur Tabi #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 2552ad6b513STimur Tabi #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 2562ad6b513STimur Tabi 2572ad6b513STimur Tabi #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 2582ad6b513STimur Tabi #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 2592ad6b513STimur Tabi #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 2602ad6b513STimur Tabi 2612ad6b513STimur Tabi #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2622ad6b513STimur Tabi #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 2632ad6b513STimur Tabi 2642ad6b513STimur Tabi /* 2652ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 2662ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 2672ad6b513STimur Tabi * External Local Bus rate is 2682ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 2692ad6b513STimur Tabi */ 2702ad6b513STimur Tabi #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 2712ad6b513STimur Tabi #define CFG_LBC_LBCR 0x00000000 2722ad6b513STimur Tabi 2732ad6b513STimur Tabi #undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ 2742ad6b513STimur Tabi 2752ad6b513STimur Tabi #ifdef CFG_LB_SDRAM 2762ad6b513STimur Tabi /*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ 2772ad6b513STimur Tabi /* 2782ad6b513STimur Tabi * Base Register 2 and Option Register 2 configure SDRAM. 2792ad6b513STimur Tabi * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 2802ad6b513STimur Tabi * 2812ad6b513STimur Tabi * For BR2, need: 2822ad6b513STimur Tabi * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 2832ad6b513STimur Tabi * port-size = 32-bits = BR2[19:20] = 11 2842ad6b513STimur Tabi * no parity checking = BR2[21:22] = 00 2852ad6b513STimur Tabi * SDRAM for MSEL = BR2[24:26] = 011 2862ad6b513STimur Tabi * Valid = BR[31] = 1 2872ad6b513STimur Tabi * 2882ad6b513STimur Tabi * 0 4 8 12 16 20 24 28 2892ad6b513STimur Tabi * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 2902ad6b513STimur Tabi */ 2912ad6b513STimur Tabi 2922ad6b513STimur Tabi #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 2932ad6b513STimur Tabi #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 2942ad6b513STimur Tabi 2952ad6b513STimur Tabi #define CFG_LBLAWBAR2_PRELIM 0xF0000000 2962ad6b513STimur Tabi #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 2972ad6b513STimur Tabi 2982ad6b513STimur Tabi #define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) 2992ad6b513STimur Tabi #define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ 3002ad6b513STimur Tabi OR_SDRAM_XAM | \ 3012ad6b513STimur Tabi ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ 3022ad6b513STimur Tabi ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ 3032ad6b513STimur Tabi OR_SDRAM_EAD) 3042ad6b513STimur Tabi 3052ad6b513STimur Tabi #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 3062ad6b513STimur Tabi #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 3072ad6b513STimur Tabi 3082ad6b513STimur Tabi /* 3092ad6b513STimur Tabi * LSDMR masks 3102ad6b513STimur Tabi */ 3112ad6b513STimur Tabi #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 3122ad6b513STimur Tabi #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 3132ad6b513STimur Tabi #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 3142ad6b513STimur Tabi #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 3152ad6b513STimur Tabi #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 3162ad6b513STimur Tabi #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 3172ad6b513STimur Tabi #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 3182ad6b513STimur Tabi #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 3192ad6b513STimur Tabi #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 3202ad6b513STimur Tabi #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 3212ad6b513STimur Tabi #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 3222ad6b513STimur Tabi #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 3232ad6b513STimur Tabi #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 3242ad6b513STimur Tabi #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 3252ad6b513STimur Tabi #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 3262ad6b513STimur Tabi #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 3272ad6b513STimur Tabi #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 3282ad6b513STimur Tabi #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 3292ad6b513STimur Tabi 3302ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 3312ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 3322ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 3332ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 3342ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 3352ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 3362ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 3372ad6b513STimur Tabi #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 3382ad6b513STimur Tabi 3392ad6b513STimur Tabi #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 3402ad6b513STimur Tabi | CFG_LBC_LSDMR_BSMA1516 \ 3412ad6b513STimur Tabi | CFG_LBC_LSDMR_RFCR8 \ 3422ad6b513STimur Tabi | CFG_LBC_LSDMR_PRETOACT6 \ 3432ad6b513STimur Tabi | CFG_LBC_LSDMR_ACTTORW3 \ 3442ad6b513STimur Tabi | CFG_LBC_LSDMR_BL8 \ 3452ad6b513STimur Tabi | CFG_LBC_LSDMR_WRC3 \ 3462ad6b513STimur Tabi | CFG_LBC_LSDMR_CL3 \ 3472ad6b513STimur Tabi ) 3482ad6b513STimur Tabi 3492ad6b513STimur Tabi /* 3502ad6b513STimur Tabi * SDRAM Controller configuration sequence. 3512ad6b513STimur Tabi */ 3522ad6b513STimur Tabi #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 3532ad6b513STimur Tabi | CFG_LBC_LSDMR_OP_PCHALL) 3542ad6b513STimur Tabi #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 3552ad6b513STimur Tabi | CFG_LBC_LSDMR_OP_ARFRSH) 3562ad6b513STimur Tabi #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 3572ad6b513STimur Tabi | CFG_LBC_LSDMR_OP_ARFRSH) 3582ad6b513STimur Tabi #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 3592ad6b513STimur Tabi | CFG_LBC_LSDMR_OP_MRW) 3602ad6b513STimur Tabi #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 3612ad6b513STimur Tabi | CFG_LBC_LSDMR_OP_NORMAL) 3622ad6b513STimur Tabi #endif 3632ad6b513STimur Tabi 3642ad6b513STimur Tabi /* 3652ad6b513STimur Tabi * Serial Port 3662ad6b513STimur Tabi */ 3672ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3682ad6b513STimur Tabi #undef CONFIG_SERIAL_SOFTWARE_FIFO 3692ad6b513STimur Tabi #define CFG_NS16550 3702ad6b513STimur Tabi #define CFG_NS16550_SERIAL 3712ad6b513STimur Tabi #define CFG_NS16550_REG_SIZE 1 3722ad6b513STimur Tabi #define CFG_NS16550_CLK get_bus_freq(0) 3732ad6b513STimur Tabi 3742ad6b513STimur Tabi #define CFG_BAUDRATE_TABLE \ 3752ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 3762ad6b513STimur Tabi 3772ad6b513STimur Tabi #define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) 3782ad6b513STimur Tabi #define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) 3792ad6b513STimur Tabi 3802ad6b513STimur Tabi /* Use the HUSH parser */ 3812ad6b513STimur Tabi #define CFG_HUSH_PARSER 3822ad6b513STimur Tabi #ifdef CFG_HUSH_PARSER 3832ad6b513STimur Tabi #define CFG_PROMPT_HUSH_PS2 "> " 3842ad6b513STimur Tabi #endif 3852ad6b513STimur Tabi 3862ad6b513STimur Tabi 3872ad6b513STimur Tabi #ifdef CONFIG_PCI 3882ad6b513STimur Tabi 3892ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3902ad6b513STimur Tabi 3912ad6b513STimur Tabi /* 3922ad6b513STimur Tabi * General PCI 3932ad6b513STimur Tabi * Addresses are mapped 1-1. 3942ad6b513STimur Tabi */ 3952ad6b513STimur Tabi #define CFG_PCI1_MEM_BASE 0x80000000 3962ad6b513STimur Tabi #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 3972ad6b513STimur Tabi #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3982ad6b513STimur Tabi #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) 3992ad6b513STimur Tabi #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 4002ad6b513STimur Tabi #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4012ad6b513STimur Tabi #define CFG_PCI1_IO_BASE 0x00000000 4022ad6b513STimur Tabi #define CFG_PCI1_IO_PHYS 0xE2000000 4032ad6b513STimur Tabi #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 4042ad6b513STimur Tabi 4052ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 4062ad6b513STimur Tabi #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) 4072ad6b513STimur Tabi #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 4082ad6b513STimur Tabi #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 4092ad6b513STimur Tabi #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) 4102ad6b513STimur Tabi #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 4112ad6b513STimur Tabi #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 4122ad6b513STimur Tabi #define CFG_PCI2_IO_BASE 0x00000000 4132ad6b513STimur Tabi #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) 4142ad6b513STimur Tabi #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ 4152ad6b513STimur Tabi #endif 4162ad6b513STimur Tabi 4172ad6b513STimur Tabi #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 4182ad6b513STimur Tabi 4192ad6b513STimur Tabi #define CONFIG_NET_MULTI 4202ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4212ad6b513STimur Tabi 4222ad6b513STimur Tabi #ifdef CONFIG_RTL8139 4232ad6b513STimur Tabi /* This macro is used by RTL8139 but not defined in PPC architecture */ 4242ad6b513STimur Tabi #define KSEG1ADDR(x) (x) 4252ad6b513STimur Tabi #endif 4262ad6b513STimur Tabi 4272ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 4282ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 4292ad6b513STimur Tabi #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE 4302ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 4312ad6b513STimur Tabi #endif 4322ad6b513STimur Tabi 4332ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 4342ad6b513STimur Tabi 4352ad6b513STimur Tabi #endif 4362ad6b513STimur Tabi 4372ad6b513STimur Tabi /* TSEC */ 4382ad6b513STimur Tabi 4392ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4402ad6b513STimur Tabi 4412ad6b513STimur Tabi #ifndef CONFIG_NET_MULTI 4422ad6b513STimur Tabi #define CONFIG_NET_MULTI 4432ad6b513STimur Tabi #endif 4442ad6b513STimur Tabi 4452ad6b513STimur Tabi #define CONFIG_MII 4462ad6b513STimur Tabi #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ 4472ad6b513STimur Tabi 4482ad6b513STimur Tabi #define CONFIG_MPC83XX_TSEC1 4492ad6b513STimur Tabi 4502ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC1 4512ad6b513STimur Tabi #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 4522ad6b513STimur Tabi #define CFG_TSEC1_OFFSET 0x24000 4532ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4542ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4552ad6b513STimur Tabi #endif 4562ad6b513STimur Tabi 4572ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC2 4582ad6b513STimur Tabi #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 4592ad6b513STimur Tabi #define CFG_TSEC2_OFFSET 0x25000 4602ad6b513STimur Tabi #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ 4612ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4622ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4632ad6b513STimur Tabi #endif 4642ad6b513STimur Tabi 4652ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4662ad6b513STimur Tabi 4672ad6b513STimur Tabi #endif 4682ad6b513STimur Tabi 4692ad6b513STimur Tabi 4702ad6b513STimur Tabi /* 4712ad6b513STimur Tabi * Environment 4722ad6b513STimur Tabi */ 4732ad6b513STimur Tabi #ifndef CFG_RAMBOOT 4742ad6b513STimur Tabi #define CFG_ENV_IS_IN_FLASH 4752ad6b513STimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 4762ad6b513STimur Tabi #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 4772ad6b513STimur Tabi #define CFG_ENV_SIZE 0x2000 4782ad6b513STimur Tabi #else 4792ad6b513STimur Tabi #define CFG_NO_FLASH /* Flash is not usable now */ 4802ad6b513STimur Tabi #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4812ad6b513STimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 4822ad6b513STimur Tabi #define CFG_ENV_SIZE 0x2000 4832ad6b513STimur Tabi #endif 4842ad6b513STimur Tabi 4852ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4862ad6b513STimur Tabi #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ 4872ad6b513STimur Tabi 4882ad6b513STimur Tabi /* CONFIG_COMMANDS */ 4892ad6b513STimur Tabi 4902ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 4912ad6b513STimur Tabi #define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) 4922ad6b513STimur Tabi #else 4932ad6b513STimur Tabi #define CONFIG_COMMANDS_CF 0 4942ad6b513STimur Tabi #endif 4952ad6b513STimur Tabi 4962ad6b513STimur Tabi #ifdef CONFIG_PCI 4972ad6b513STimur Tabi #define CONFIG_COMMANDS_PCI CFG_CMD_PCI 4982ad6b513STimur Tabi #else 4992ad6b513STimur Tabi #define CONFIG_COMMANDS_PCI 0 5002ad6b513STimur Tabi #endif 5012ad6b513STimur Tabi 5022ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 5032ad6b513STimur Tabi #define CONFIG_COMMANDS_I2C CFG_CMD_I2C 5042ad6b513STimur Tabi #else 5052ad6b513STimur Tabi #define CONFIG_COMMANDS_I2C 0 5062ad6b513STimur Tabi #endif 5072ad6b513STimur Tabi 5082ad6b513STimur Tabi #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ 5092ad6b513STimur Tabi CONFIG_COMMANDS_CF | \ 5102ad6b513STimur Tabi CFG_CMD_NET | \ 5112ad6b513STimur Tabi CFG_CMD_PING | \ 5122ad6b513STimur Tabi CONFIG_COMMANDS_I2C | \ 5132ad6b513STimur Tabi CONFIG_COMMANDS_PCI | \ 5142ad6b513STimur Tabi CFG_CMD_SDRAM | \ 5152ad6b513STimur Tabi CFG_CMD_DATE | \ 5162ad6b513STimur Tabi CFG_CMD_CACHE | \ 5172ad6b513STimur Tabi CFG_CMD_IRQ) 5182ad6b513STimur Tabi #include <cmd_confdefs.h> 5192ad6b513STimur Tabi 5202ad6b513STimur Tabi /* Watchdog */ 5212ad6b513STimur Tabi 5222ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5232ad6b513STimur Tabi #ifdef CONFIG_WATCHDOG 5242ad6b513STimur Tabi #define CFG_WATCHDOG_VALUE 0xFFFFFFC3 5252ad6b513STimur Tabi #endif 5262ad6b513STimur Tabi 5272ad6b513STimur Tabi /* 5282ad6b513STimur Tabi * Miscellaneous configurable options 5292ad6b513STimur Tabi */ 5302ad6b513STimur Tabi #define CFG_LONGHELP /* undef to save memory */ 5312ad6b513STimur Tabi #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 5322ad6b513STimur Tabi #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5332ad6b513STimur Tabi 5342ad6b513STimur Tabi #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 5352ad6b513STimur Tabi #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 5362ad6b513STimur Tabi #else 5372ad6b513STimur Tabi #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 5382ad6b513STimur Tabi #endif 5392ad6b513STimur Tabi 5402ad6b513STimur Tabi #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ 5412ad6b513STimur Tabi #define CFG_MAXARGS 16 /* max number of command args */ 5422ad6b513STimur Tabi #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 5432ad6b513STimur Tabi #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 5442ad6b513STimur Tabi 5452ad6b513STimur Tabi /* 5462ad6b513STimur Tabi * For booting Linux, the board info and command line data 5472ad6b513STimur Tabi * have to be in the first 8 MB of memory, since this is 5482ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5492ad6b513STimur Tabi */ 5502ad6b513STimur Tabi #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 5512ad6b513STimur Tabi 5522ad6b513STimur Tabi /* Cache Configuration */ 5532ad6b513STimur Tabi #define CFG_DCACHE_SIZE 32768 5542ad6b513STimur Tabi #define CFG_CACHELINE_SIZE 32 5552ad6b513STimur Tabi #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 5562ad6b513STimur Tabi #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ 5572ad6b513STimur Tabi #endif 5582ad6b513STimur Tabi 5592ad6b513STimur Tabi #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 5602ad6b513STimur Tabi 5612ad6b513STimur Tabi #define CFG_HRCW_LOW (\ 5622ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5632ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5642ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5652ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5662ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5672ad6b513STimur Tabi 5682ad6b513STimur Tabi #ifdef PCI_64BIT 5692ad6b513STimur Tabi #define CFG_HRCW_HIGH (\ 5702ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5712ad6b513STimur Tabi HRCWH_64_BIT_PCI |\ 5722ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5732ad6b513STimur Tabi HRCWH_PCI2_ARBITER_DISABLE |\ 5742ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5752ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5762ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5772ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5782ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5792ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5802ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5812ad6b513STimur Tabi #else 5822ad6b513STimur Tabi #define CFG_HRCW_HIGH (\ 5832ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5842ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5852ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5862ad6b513STimur Tabi HRCWH_PCI2_ARBITER_DISABLE |\ 5872ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5882ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5892ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5902ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5912ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5922ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5932ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5942ad6b513STimur Tabi #endif 5952ad6b513STimur Tabi 5962ad6b513STimur Tabi /* System performance */ 5972ad6b513STimur Tabi #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5982ad6b513STimur Tabi #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5992ad6b513STimur Tabi #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 6002ad6b513STimur Tabi #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 6012ad6b513STimur Tabi #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 6022ad6b513STimur Tabi #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */ 6032ad6b513STimur Tabi #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ 6042ad6b513STimur Tabi 6052ad6b513STimur Tabi /* System IO Config */ 6062ad6b513STimur Tabi #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 60798883332STimur Tabi #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) 6082ad6b513STimur Tabi 6092ad6b513STimur Tabi #define CFG_HID0_INIT 0x000000000 6102ad6b513STimur Tabi 6112ad6b513STimur Tabi #define CFG_HID0_FINAL CFG_HID0_INIT 6122ad6b513STimur Tabi 6132ad6b513STimur Tabi #define CFG_HID2 HID2_HBE 6142ad6b513STimur Tabi 6152ad6b513STimur Tabi /* DDR @ 0x00000000 */ 6162ad6b513STimur Tabi #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6172ad6b513STimur Tabi #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6182ad6b513STimur Tabi 6192ad6b513STimur Tabi /* PCI @ 0x80000000 */ 6202ad6b513STimur Tabi #ifdef CONFIG_PCI 6212ad6b513STimur Tabi #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6222ad6b513STimur Tabi #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6232ad6b513STimur Tabi #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6242ad6b513STimur Tabi #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6252ad6b513STimur Tabi #else 6262ad6b513STimur Tabi #define CFG_IBAT1L 0 6272ad6b513STimur Tabi #define CFG_IBAT1U 0 6282ad6b513STimur Tabi #define CFG_IBAT2L 0 6292ad6b513STimur Tabi #define CFG_IBAT2U 0 6302ad6b513STimur Tabi #endif 6312ad6b513STimur Tabi 6322ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 6332ad6b513STimur Tabi #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6342ad6b513STimur Tabi #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6352ad6b513STimur Tabi #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6362ad6b513STimur Tabi #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6372ad6b513STimur Tabi #else 6382ad6b513STimur Tabi #define CFG_IBAT3L 0 6392ad6b513STimur Tabi #define CFG_IBAT3U 0 6402ad6b513STimur Tabi #define CFG_IBAT4L 0 6412ad6b513STimur Tabi #define CFG_IBAT4U 0 6422ad6b513STimur Tabi #endif 6432ad6b513STimur Tabi 6442ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 6452ad6b513STimur Tabi #define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6462ad6b513STimur Tabi #define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) 6472ad6b513STimur Tabi 6482ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 6492ad6b513STimur Tabi #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 6502ad6b513STimur Tabi #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 6512ad6b513STimur Tabi 6522ad6b513STimur Tabi #define CFG_IBAT7L 0 6532ad6b513STimur Tabi #define CFG_IBAT7U 0 6542ad6b513STimur Tabi 6552ad6b513STimur Tabi #define CFG_DBAT0L CFG_IBAT0L 6562ad6b513STimur Tabi #define CFG_DBAT0U CFG_IBAT0U 6572ad6b513STimur Tabi #define CFG_DBAT1L CFG_IBAT1L 6582ad6b513STimur Tabi #define CFG_DBAT1U CFG_IBAT1U 6592ad6b513STimur Tabi #define CFG_DBAT2L CFG_IBAT2L 6602ad6b513STimur Tabi #define CFG_DBAT2U CFG_IBAT2U 6612ad6b513STimur Tabi #define CFG_DBAT3L CFG_IBAT3L 6622ad6b513STimur Tabi #define CFG_DBAT3U CFG_IBAT3U 6632ad6b513STimur Tabi #define CFG_DBAT4L CFG_IBAT4L 6642ad6b513STimur Tabi #define CFG_DBAT4U CFG_IBAT4U 6652ad6b513STimur Tabi #define CFG_DBAT5L CFG_IBAT5L 6662ad6b513STimur Tabi #define CFG_DBAT5U CFG_IBAT5U 6672ad6b513STimur Tabi #define CFG_DBAT6L CFG_IBAT6L 6682ad6b513STimur Tabi #define CFG_DBAT6U CFG_IBAT6U 6692ad6b513STimur Tabi #define CFG_DBAT7L CFG_IBAT7L 6702ad6b513STimur Tabi #define CFG_DBAT7U CFG_IBAT7U 6712ad6b513STimur Tabi 6722ad6b513STimur Tabi /* 6732ad6b513STimur Tabi * Internal Definitions 6742ad6b513STimur Tabi * 6752ad6b513STimur Tabi * Boot Flags 6762ad6b513STimur Tabi */ 6772ad6b513STimur Tabi #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 6782ad6b513STimur Tabi #define BOOTFLAG_WARM 0x02 /* Software reboot */ 6792ad6b513STimur Tabi 6802ad6b513STimur Tabi #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 6812ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6822ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 6832ad6b513STimur Tabi #endif 6842ad6b513STimur Tabi 6852ad6b513STimur Tabi 6862ad6b513STimur Tabi /* 6872ad6b513STimur Tabi * Environment Configuration 6882ad6b513STimur Tabi */ 6892ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6902ad6b513STimur Tabi 6912ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC1 6922ad6b513STimur Tabi #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 6932ad6b513STimur Tabi #endif 6942ad6b513STimur Tabi 6952ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC2 6962ad6b513STimur Tabi #define CONFIG_HAS_ETH1 6972ad6b513STimur Tabi #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 6982ad6b513STimur Tabi #endif 6992ad6b513STimur Tabi 7002ad6b513STimur Tabi #define CONFIG_IPADDR 10.82.19.159 7012ad6b513STimur Tabi #define CONFIG_SERVERIP 10.82.48.106 7022ad6b513STimur Tabi #define CONFIG_GATEWAYIP 10.82.19.254 7032ad6b513STimur Tabi #define CONFIG_NETMASK 255.255.252.0 70498883332STimur Tabi #define CONFIG_NETDEV eth0 7052ad6b513STimur Tabi 7062ad6b513STimur Tabi #define CONFIG_HOSTNAME mpc8349emitx 7072ad6b513STimur Tabi #define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs 7082ad6b513STimur Tabi #define CONFIG_BOOTFILE timur/uImage 7092ad6b513STimur Tabi 7102ad6b513STimur Tabi #define CONFIG_UBOOTPATH timur/u-boot.bin 7112ad6b513STimur Tabi #define CONFIG_UBOOTSTART fe700000 7122ad6b513STimur Tabi #define CONFIG_UBOOTEND fe77ffff 7132ad6b513STimur Tabi 7142ad6b513STimur Tabi #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 7152ad6b513STimur Tabi 7162ad6b513STimur Tabi #define CONFIG_BAUDRATE 115200 7172ad6b513STimur Tabi 7182ad6b513STimur Tabi #undef CONFIG_BOOTCOMMAND 7192ad6b513STimur Tabi #ifdef CONFIG_BOOTCOMMAND 7202ad6b513STimur Tabi #define CONFIG_BOOTDELAY 6 7212ad6b513STimur Tabi #else 7222ad6b513STimur Tabi #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 7232ad6b513STimur Tabi #endif 7242ad6b513STimur Tabi 7252ad6b513STimur Tabi #define XMK_STR(x) #x 7262ad6b513STimur Tabi #define MK_STR(x) XMK_STR(x) 7272ad6b513STimur Tabi 72898883332STimur Tabi #define CONFIG_BOOTARGS \ 72998883332STimur Tabi "root=/dev/nfs rw" \ 73098883332STimur Tabi " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 73198883332STimur Tabi " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 73298883332STimur Tabi MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 73398883332STimur Tabi MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 73498883332STimur Tabi " console=ttyS0," MK_STR(CONFIG_BAUDRATE) 73598883332STimur Tabi 7362ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 73798883332STimur Tabi "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 7382ad6b513STimur Tabi "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ 7392ad6b513STimur Tabi "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ 7402ad6b513STimur Tabi "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ 7412ad6b513STimur Tabi "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ 7422ad6b513STimur Tabi "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ 7432ad6b513STimur Tabi "protect off FEF00000 FEF7FFFF; " \ 7442ad6b513STimur Tabi "erase FEF00000 FEF7FFFF; " \ 7452ad6b513STimur Tabi "cp.b $loadaddr FEF00000 $filesize; " \ 7462ad6b513STimur Tabi "protect on FEF00000 FEF7FFFF; " \ 7472ad6b513STimur Tabi "cmp.b $loadaddr FEF00000 $filesize\0" \ 7482ad6b513STimur Tabi "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ 7492ad6b513STimur Tabi "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ 7502ad6b513STimur Tabi "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" 7512ad6b513STimur Tabi 7522ad6b513STimur Tabi 7532ad6b513STimur Tabi #undef MK_STR 7542ad6b513STimur Tabi #undef XMK_STR 7552ad6b513STimur Tabi 7562ad6b513STimur Tabi #endif 757