12ad6b513STimur Tabi /* 22ad6b513STimur Tabi * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 247a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 347a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 367a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 377a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 387a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 597a78f148STimur Tabi #if (TEXT_BASE == 0xFE000000) 607a78f148STimur Tabi #define CFG_LOWBOOT 617a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 662ad6b513STimur Tabi #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 672ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 682ad6b513STimur Tabi 697a78f148STimur Tabi #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ 702ad6b513STimur Tabi 717a78f148STimur Tabi 727a78f148STimur Tabi /* On-board devices */ 737a78f148STimur Tabi 747a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 752ad6b513STimur Tabi #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 767a78f148STimur Tabi #define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ 777a78f148STimur Tabi #endif 787a78f148STimur Tabi 797a78f148STimur Tabi #define CONFIG_PCI 802ad6b513STimur Tabi #define CONFIG_RTC_DS1337 817a78f148STimur Tabi #define CONFIG_HARD_I2C 827a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 837a78f148STimur Tabi 847a78f148STimur Tabi /* 857a78f148STimur Tabi * Device configurations 867a78f148STimur Tabi */ 872ad6b513STimur Tabi 882ad6b513STimur Tabi /* I2C */ 892ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 902ad6b513STimur Tabi 912ad6b513STimur Tabi #define CONFIG_MISC_INIT_F 922ad6b513STimur Tabi #define CONFIG_MISC_INIT_R 932ad6b513STimur Tabi 94be5e6181STimur Tabi #define CONFIG_FSL_I2C 952ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 962ad6b513STimur Tabi #define CONFIG_I2C_CMD_TREE 972ad6b513STimur Tabi #define CFG_I2C_OFFSET 0x3000 982ad6b513STimur Tabi #define CFG_I2C2_OFFSET 0x3100 99be5e6181STimur Tabi #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 1002ad6b513STimur Tabi 101be5e6181STimur Tabi #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 102be5e6181STimur Tabi #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 103be5e6181STimur Tabi #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 104be5e6181STimur Tabi #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 105be5e6181STimur Tabi #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 106be5e6181STimur Tabi #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 107be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1082ad6b513STimur Tabi 1092ad6b513STimur Tabi #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 1102ad6b513STimur Tabi #define CFG_I2C_SLAVE 0x7F 1112ad6b513STimur Tabi 1122ad6b513STimur Tabi /* Don't probe these addresses: */ 1132ad6b513STimur Tabi #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ 1142ad6b513STimur Tabi {1, CFG_I2C_8574_ADDR2}, \ 1152ad6b513STimur Tabi {1, CFG_I2C_8574A_ADDR1}, \ 1162ad6b513STimur Tabi {1, CFG_I2C_8574A_ADDR2}} 1172ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 1182ad6b513STimur Tabi #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 1192ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1202ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1212ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1222ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1232ad6b513STimur Tabi 1242ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1252ad6b513STimur Tabi 1262ad6b513STimur Tabi #endif 1272ad6b513STimur Tabi 1287a78f148STimur Tabi /* Compact Flash */ 1292ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1302ad6b513STimur Tabi 1312ad6b513STimur Tabi #define CFG_IDE_MAXBUS 1 1322ad6b513STimur Tabi #define CFG_IDE_MAXDEVICE 1 1332ad6b513STimur Tabi 1342ad6b513STimur Tabi #define CFG_ATA_IDE0_OFFSET 0x0000 1352ad6b513STimur Tabi #define CFG_ATA_BASE_ADDR CFG_CF_BASE 1362ad6b513STimur Tabi #define CFG_ATA_DATA_OFFSET 0x0000 1372ad6b513STimur Tabi #define CFG_ATA_REG_OFFSET 0 1382ad6b513STimur Tabi #define CFG_ATA_ALT_OFFSET 0x0200 1392ad6b513STimur Tabi #define CFG_ATA_STRIDE 2 1402ad6b513STimur Tabi 1412ad6b513STimur Tabi #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 1422ad6b513STimur Tabi 1432ad6b513STimur Tabi #define CONFIG_DOS_PARTITION 1442ad6b513STimur Tabi 1457a78f148STimur Tabi #endif 1462ad6b513STimur Tabi 1477a78f148STimur Tabi /* 1487a78f148STimur Tabi * DDR Setup 1497a78f148STimur Tabi */ 1507a78f148STimur Tabi #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 1517a78f148STimur Tabi #define CFG_SDRAM_BASE CFG_DDR_BASE 1527a78f148STimur Tabi #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 1537a78f148STimur Tabi #define CFG_83XX_DDR_USES_CS0 1547a78f148STimur Tabi #define CFG_MEMTEST_START 0x1000 /* memtest region */ 1557a78f148STimur Tabi #define CFG_MEMTEST_END 0x2000 1567a78f148STimur Tabi 157f64702b7STimur Tabi #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 158f64702b7STimur Tabi DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 159f64702b7STimur Tabi 1607a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 1617a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1627a78f148STimur Tabi #endif 1637a78f148STimur Tabi 1647a78f148STimur Tabi #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 1657a78f148STimur Tabi #define CFG_DDR_SIZE 256 /* Mb */ 1667a78f148STimur Tabi #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 1677a78f148STimur Tabi 1687a78f148STimur Tabi #define CFG_DDR_TIMING_1 0x26242321 1697a78f148STimur Tabi #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1707a78f148STimur Tabi #endif 1717a78f148STimur Tabi 1727a78f148STimur Tabi /* 1737a78f148STimur Tabi *Flash on the Local Bus 1747a78f148STimur Tabi */ 1757a78f148STimur Tabi 1767a78f148STimur Tabi #define CFG_FLASH_CFI /* use the Common Flash Interface */ 1777a78f148STimur Tabi #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 1787a78f148STimur Tabi #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 1797a78f148STimur Tabi #define CFG_FLASH_EMPTY_INFO 1807a78f148STimur Tabi #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 1817a78f148STimur Tabi #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1827a78f148STimur Tabi #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 1837a78f148STimur Tabi #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 1847a78f148STimur Tabi 1857a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 1867a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 1877a78f148STimur Tabi #define CFG_FLASH_QUIET_TEST 1887a78f148STimur Tabi #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 1897a78f148STimur Tabi #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} 1907a78f148STimur Tabi #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ 1917a78f148STimur Tabi #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 1927a78f148STimur Tabi 1937a78f148STimur Tabi /* 1947a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 1957a78f148STimur Tabi */ 1967a78f148STimur Tabi 1977a78f148STimur Tabi /* Flash */ 1987a78f148STimur Tabi 1997a78f148STimur Tabi #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) 2007a78f148STimur Tabi #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 2017a78f148STimur Tabi OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 2027a78f148STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 2037a78f148STimur Tabi #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE 2047a78f148STimur Tabi #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) 2057a78f148STimur Tabi 2067a78f148STimur Tabi /* Vitesse 7385 */ 2077a78f148STimur Tabi 2087a78f148STimur Tabi #ifdef CONFIG_VSC7385 2097a78f148STimur Tabi 2107a78f148STimur Tabi #define CFG_VSC7385_BASE 0xF8000000 2117a78f148STimur Tabi 2127a78f148STimur Tabi #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) 2137a78f148STimur Tabi #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 2147a78f148STimur Tabi OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 2157a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2167a78f148STimur Tabi 2177a78f148STimur Tabi #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE 2187a78f148STimur Tabi #define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2197a78f148STimur Tabi 2207a78f148STimur Tabi #endif 2217a78f148STimur Tabi 2227a78f148STimur Tabi /* LED */ 2237a78f148STimur Tabi 2247a78f148STimur Tabi #define CFG_LED_BASE 0xF9000000 2257a78f148STimur Tabi #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) 2267a78f148STimur Tabi #define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ 2277a78f148STimur Tabi OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 2287a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2297a78f148STimur Tabi 2307a78f148STimur Tabi /* Compact Flash */ 2317a78f148STimur Tabi 2327a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2337a78f148STimur Tabi 2347a78f148STimur Tabi #define CFG_CF_BASE 0xF0000000 2357a78f148STimur Tabi 2367a78f148STimur Tabi #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 2377a78f148STimur Tabi #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2387a78f148STimur Tabi 2397a78f148STimur Tabi #define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE 2407a78f148STimur Tabi #define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 2417a78f148STimur Tabi 2427a78f148STimur Tabi #endif 2437a78f148STimur Tabi 2447a78f148STimur Tabi /* 2457a78f148STimur Tabi * U-Boot memory configuration 2467a78f148STimur Tabi */ 2477a78f148STimur Tabi #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 2482ad6b513STimur Tabi 2492ad6b513STimur Tabi #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 2502ad6b513STimur Tabi #define CFG_RAMBOOT 2512ad6b513STimur Tabi #else 2522ad6b513STimur Tabi #undef CFG_RAMBOOT 2532ad6b513STimur Tabi #endif 2542ad6b513STimur Tabi 2552ad6b513STimur Tabi #define CONFIG_L1_INIT_RAM 2562ad6b513STimur Tabi #define CFG_INIT_RAM_LOCK 2572ad6b513STimur Tabi #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 2582ad6b513STimur Tabi #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 2592ad6b513STimur Tabi 2602ad6b513STimur Tabi #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 2612ad6b513STimur Tabi #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 2622ad6b513STimur Tabi #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 2632ad6b513STimur Tabi 2642ad6b513STimur Tabi #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2652ad6b513STimur Tabi #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 2662ad6b513STimur Tabi 2672ad6b513STimur Tabi /* 2682ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 2692ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 2702ad6b513STimur Tabi * External Local Bus rate is 2712ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 2722ad6b513STimur Tabi */ 2732ad6b513STimur Tabi #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 2742ad6b513STimur Tabi #define CFG_LBC_LBCR 0x00000000 2752ad6b513STimur Tabi 2762ad6b513STimur Tabi #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 2772ad6b513STimur Tabi #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 2782ad6b513STimur Tabi 2792ad6b513STimur Tabi /* 2802ad6b513STimur Tabi * Serial Port 2812ad6b513STimur Tabi */ 2822ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 2832ad6b513STimur Tabi #undef CONFIG_SERIAL_SOFTWARE_FIFO 2842ad6b513STimur Tabi #define CFG_NS16550 2852ad6b513STimur Tabi #define CFG_NS16550_SERIAL 2862ad6b513STimur Tabi #define CFG_NS16550_REG_SIZE 1 2872ad6b513STimur Tabi #define CFG_NS16550_CLK get_bus_freq(0) 2882ad6b513STimur Tabi 2892ad6b513STimur Tabi #define CFG_BAUDRATE_TABLE \ 2902ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 2912ad6b513STimur Tabi 2927a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 2937a78f148STimur Tabi 294d239d74bSTimur Tabi #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) 295d239d74bSTimur Tabi #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) 2962ad6b513STimur Tabi 297bf0b542dSKim Phillips /* pass open firmware flat tree */ 2987a78f148STimur Tabi #define CONFIG_OF_FLAT_TREE 2997a78f148STimur Tabi #define CONFIG_OF_BOARD_SETUP 300bf0b542dSKim Phillips 301bf0b542dSKim Phillips /* maximum size of the flat tree (8K) */ 302bf0b542dSKim Phillips #define OF_FLAT_TREE_MAX_SIZE 8192 303bf0b542dSKim Phillips 304bf0b542dSKim Phillips #define OF_CPU "PowerPC,8349@0" 305bf0b542dSKim Phillips #define OF_SOC "soc8349@e0000000" 306bf0b542dSKim Phillips #define OF_TBCLK (bd->bi_busfreq / 4) 307bf0b542dSKim Phillips #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" 3082ad6b513STimur Tabi 3097a78f148STimur Tabi /* 3107a78f148STimur Tabi * PCI 3117a78f148STimur Tabi */ 3122ad6b513STimur Tabi #ifdef CONFIG_PCI 3132ad6b513STimur Tabi 3142ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3152ad6b513STimur Tabi 3162ad6b513STimur Tabi /* 3172ad6b513STimur Tabi * General PCI 3182ad6b513STimur Tabi * Addresses are mapped 1-1. 3192ad6b513STimur Tabi */ 3202ad6b513STimur Tabi #define CFG_PCI1_MEM_BASE 0x80000000 3212ad6b513STimur Tabi #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 3222ad6b513STimur Tabi #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3232ad6b513STimur Tabi #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) 3242ad6b513STimur Tabi #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 3252ad6b513STimur Tabi #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3262ad6b513STimur Tabi #define CFG_PCI1_IO_BASE 0x00000000 3272ad6b513STimur Tabi #define CFG_PCI1_IO_PHYS 0xE2000000 3282ad6b513STimur Tabi #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 3292ad6b513STimur Tabi 3302ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 3312ad6b513STimur Tabi #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) 3322ad6b513STimur Tabi #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 3332ad6b513STimur Tabi #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 3342ad6b513STimur Tabi #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) 3352ad6b513STimur Tabi #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 3362ad6b513STimur Tabi #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3372ad6b513STimur Tabi #define CFG_PCI2_IO_BASE 0x00000000 3382ad6b513STimur Tabi #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) 3392ad6b513STimur Tabi #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ 3402ad6b513STimur Tabi #endif 3412ad6b513STimur Tabi 3422ad6b513STimur Tabi #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 3432ad6b513STimur Tabi 3442ad6b513STimur Tabi #define CONFIG_NET_MULTI 3452ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3462ad6b513STimur Tabi 3472ad6b513STimur Tabi #ifdef CONFIG_RTL8139 3482ad6b513STimur Tabi /* This macro is used by RTL8139 but not defined in PPC architecture */ 3492ad6b513STimur Tabi #define KSEG1ADDR(x) (x) 3502ad6b513STimur Tabi #endif 3512ad6b513STimur Tabi 3522ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3532ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3542ad6b513STimur Tabi #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE 3552ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3562ad6b513STimur Tabi #endif 3572ad6b513STimur Tabi 3582ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3592ad6b513STimur Tabi 3602ad6b513STimur Tabi #endif 3612ad6b513STimur Tabi 3627a78f148STimur Tabi #define PCI_66M 3637a78f148STimur Tabi #ifdef PCI_66M 3647a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 3657a78f148STimur Tabi #else 3667a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 3677a78f148STimur Tabi #endif 3687a78f148STimur Tabi 3692ad6b513STimur Tabi /* TSEC */ 3702ad6b513STimur Tabi 3712ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 3722ad6b513STimur Tabi 3732ad6b513STimur Tabi #define CONFIG_NET_MULTI 3742ad6b513STimur Tabi #define CONFIG_MII 3752ad6b513STimur Tabi #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ 3762ad6b513STimur Tabi 377255a3577SKim Phillips #define CONFIG_TSEC1 3782ad6b513STimur Tabi 379255a3577SKim Phillips #ifdef CONFIG_TSEC1 380255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 3812ad6b513STimur Tabi #define CFG_TSEC1_OFFSET 0x24000 3822ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 3832ad6b513STimur Tabi #define TSEC1_PHYIDX 0 3842ad6b513STimur Tabi #endif 3852ad6b513STimur Tabi 386255a3577SKim Phillips #ifdef CONFIG_TSEC2 3877a78f148STimur Tabi #define CONFIG_HAS_ETH1 388255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3892ad6b513STimur Tabi #define CFG_TSEC2_OFFSET 0x25000 3902ad6b513STimur Tabi #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ 3912ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 3922ad6b513STimur Tabi #define TSEC2_PHYIDX 0 3932ad6b513STimur Tabi #endif 3942ad6b513STimur Tabi 3952ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 3962ad6b513STimur Tabi 3972ad6b513STimur Tabi #endif 3982ad6b513STimur Tabi 3992ad6b513STimur Tabi /* 4002ad6b513STimur Tabi * Environment 4012ad6b513STimur Tabi */ 4027a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4037a78f148STimur Tabi 4042ad6b513STimur Tabi #ifndef CFG_RAMBOOT 4052ad6b513STimur Tabi #define CFG_ENV_IS_IN_FLASH 4067a78f148STimur Tabi #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4077a78f148STimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) 4082ad6b513STimur Tabi #define CFG_ENV_SIZE 0x2000 4092ad6b513STimur Tabi #else 4102ad6b513STimur Tabi #define CFG_NO_FLASH /* Flash is not usable now */ 4112ad6b513STimur Tabi #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4122ad6b513STimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 4132ad6b513STimur Tabi #define CFG_ENV_SIZE 0x2000 4142ad6b513STimur Tabi #endif 4152ad6b513STimur Tabi 4162ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4172ad6b513STimur Tabi #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ 4182ad6b513STimur Tabi 419*8ea5499aSJon Loeliger /* 420*8ea5499aSJon Loeliger * Command line configuration. 421*8ea5499aSJon Loeliger */ 422*8ea5499aSJon Loeliger #include <config_cmd_default.h> 423*8ea5499aSJon Loeliger 424*8ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 425*8ea5499aSJon Loeliger #define CONFIG_CMD_DATE 426*8ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 427*8ea5499aSJon Loeliger #define CONFIG_CMD_NET 428*8ea5499aSJon Loeliger #define CONFIG_CMD_PING 429*8ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 4302ad6b513STimur Tabi 4312ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 432*8ea5499aSJon Loeliger #define CONFIG_CMD_IDE 433*8ea5499aSJon Loeliger #define CONFIG_CMD_FAT 4342ad6b513STimur Tabi #endif 4352ad6b513STimur Tabi 4362ad6b513STimur Tabi #ifdef CONFIG_PCI 437*8ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4382ad6b513STimur Tabi #endif 4392ad6b513STimur Tabi 4402ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 441*8ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4422ad6b513STimur Tabi #endif 4432ad6b513STimur Tabi 4442ad6b513STimur Tabi 4452ad6b513STimur Tabi /* Watchdog */ 4462ad6b513STimur Tabi 4472ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 4482ad6b513STimur Tabi 4492ad6b513STimur Tabi /* 4502ad6b513STimur Tabi * Miscellaneous configurable options 4512ad6b513STimur Tabi */ 4522ad6b513STimur Tabi #define CFG_LONGHELP /* undef to save memory */ 4537a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 4547a78f148STimur Tabi #define CFG_HUSH_PARSER /* Use the HUSH parser */ 4557a78f148STimur Tabi #define CFG_PROMPT_HUSH_PS2 "> " 4567a78f148STimur Tabi 4572ad6b513STimur Tabi #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 4587a78f148STimur Tabi #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 4597a78f148STimur Tabi 4607a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 4612ad6b513STimur Tabi #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 4627a78f148STimur Tabi #else 4637a78f148STimur Tabi #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 4647a78f148STimur Tabi #endif 4652ad6b513STimur Tabi 466*8ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 4672ad6b513STimur Tabi #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 4682ad6b513STimur Tabi #else 4692ad6b513STimur Tabi #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 4702ad6b513STimur Tabi #endif 4712ad6b513STimur Tabi 4722ad6b513STimur Tabi #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ 4732ad6b513STimur Tabi #define CFG_MAXARGS 16 /* max number of command args */ 4742ad6b513STimur Tabi #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 4752ad6b513STimur Tabi #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 4762ad6b513STimur Tabi 4772ad6b513STimur Tabi /* 4782ad6b513STimur Tabi * For booting Linux, the board info and command line data 4792ad6b513STimur Tabi * have to be in the first 8 MB of memory, since this is 4802ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 4812ad6b513STimur Tabi */ 4822ad6b513STimur Tabi #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 4832ad6b513STimur Tabi 4847a78f148STimur Tabi /* 4857a78f148STimur Tabi * Cache Configuration 4867a78f148STimur Tabi */ 4872ad6b513STimur Tabi #define CFG_DCACHE_SIZE 32768 4882ad6b513STimur Tabi #define CFG_CACHELINE_SIZE 32 489*8ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 4902ad6b513STimur Tabi #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ 4912ad6b513STimur Tabi #endif 4922ad6b513STimur Tabi 4932ad6b513STimur Tabi #define CFG_HRCW_LOW (\ 4942ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 4952ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 4962ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 4972ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 4982ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 4992ad6b513STimur Tabi 5007a78f148STimur Tabi #ifdef CFG_LOWBOOT 5012ad6b513STimur Tabi #define CFG_HRCW_HIGH (\ 5022ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5037a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5042ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5057a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5062ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5072ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5082ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5092ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5102ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5112ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5122ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5132ad6b513STimur Tabi #else 5142ad6b513STimur Tabi #define CFG_HRCW_HIGH (\ 5152ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5162ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5172ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5187a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5192ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5202ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5212ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5222ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5232ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5242ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5252ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5262ad6b513STimur Tabi #endif 5272ad6b513STimur Tabi 5287a78f148STimur Tabi /* 5297a78f148STimur Tabi * System performance 5307a78f148STimur Tabi */ 5312ad6b513STimur Tabi #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5322ad6b513STimur Tabi #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5332ad6b513STimur Tabi #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5342ad6b513STimur Tabi #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5352ad6b513STimur Tabi #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 536be5e6181STimur Tabi #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 5372ad6b513STimur Tabi 5387a78f148STimur Tabi /* 5397a78f148STimur Tabi * System IO Config 5407a78f148STimur Tabi */ 5412ad6b513STimur Tabi #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 54298883332STimur Tabi #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) 5432ad6b513STimur Tabi 5442ad6b513STimur Tabi #define CFG_HID0_INIT 0x000000000 5452ad6b513STimur Tabi #define CFG_HID0_FINAL CFG_HID0_INIT 5462ad6b513STimur Tabi 5472ad6b513STimur Tabi #define CFG_HID2 HID2_HBE 5482ad6b513STimur Tabi 5497a78f148STimur Tabi /* DDR */ 5502ad6b513STimur Tabi #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5512ad6b513STimur Tabi #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5522ad6b513STimur Tabi 5537a78f148STimur Tabi /* PCI */ 5542ad6b513STimur Tabi #ifdef CONFIG_PCI 5552ad6b513STimur Tabi #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5562ad6b513STimur Tabi #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5572ad6b513STimur Tabi #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5582ad6b513STimur Tabi #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5592ad6b513STimur Tabi #else 5602ad6b513STimur Tabi #define CFG_IBAT1L 0 5612ad6b513STimur Tabi #define CFG_IBAT1U 0 5622ad6b513STimur Tabi #define CFG_IBAT2L 0 5632ad6b513STimur Tabi #define CFG_IBAT2U 0 5642ad6b513STimur Tabi #endif 5652ad6b513STimur Tabi 5662ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 5672ad6b513STimur Tabi #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5682ad6b513STimur Tabi #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5692ad6b513STimur Tabi #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5702ad6b513STimur Tabi #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5712ad6b513STimur Tabi #else 5722ad6b513STimur Tabi #define CFG_IBAT3L 0 5732ad6b513STimur Tabi #define CFG_IBAT3U 0 5742ad6b513STimur Tabi #define CFG_IBAT4L 0 5752ad6b513STimur Tabi #define CFG_IBAT4U 0 5762ad6b513STimur Tabi #endif 5772ad6b513STimur Tabi 5782ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 579d239d74bSTimur Tabi #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 580d239d74bSTimur Tabi #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 5812ad6b513STimur Tabi 5822ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 5832ad6b513STimur Tabi #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 5842ad6b513STimur Tabi #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 5852ad6b513STimur Tabi 5862ad6b513STimur Tabi #define CFG_IBAT7L 0 5872ad6b513STimur Tabi #define CFG_IBAT7U 0 5882ad6b513STimur Tabi 5892ad6b513STimur Tabi #define CFG_DBAT0L CFG_IBAT0L 5902ad6b513STimur Tabi #define CFG_DBAT0U CFG_IBAT0U 5912ad6b513STimur Tabi #define CFG_DBAT1L CFG_IBAT1L 5922ad6b513STimur Tabi #define CFG_DBAT1U CFG_IBAT1U 5932ad6b513STimur Tabi #define CFG_DBAT2L CFG_IBAT2L 5942ad6b513STimur Tabi #define CFG_DBAT2U CFG_IBAT2U 5952ad6b513STimur Tabi #define CFG_DBAT3L CFG_IBAT3L 5962ad6b513STimur Tabi #define CFG_DBAT3U CFG_IBAT3U 5972ad6b513STimur Tabi #define CFG_DBAT4L CFG_IBAT4L 5982ad6b513STimur Tabi #define CFG_DBAT4U CFG_IBAT4U 5992ad6b513STimur Tabi #define CFG_DBAT5L CFG_IBAT5L 6002ad6b513STimur Tabi #define CFG_DBAT5U CFG_IBAT5U 6012ad6b513STimur Tabi #define CFG_DBAT6L CFG_IBAT6L 6022ad6b513STimur Tabi #define CFG_DBAT6U CFG_IBAT6U 6032ad6b513STimur Tabi #define CFG_DBAT7L CFG_IBAT7L 6042ad6b513STimur Tabi #define CFG_DBAT7U CFG_IBAT7U 6052ad6b513STimur Tabi 6062ad6b513STimur Tabi /* 6072ad6b513STimur Tabi * Internal Definitions 6082ad6b513STimur Tabi * 6092ad6b513STimur Tabi * Boot Flags 6102ad6b513STimur Tabi */ 6112ad6b513STimur Tabi #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 6122ad6b513STimur Tabi #define BOOTFLAG_WARM 0x02 /* Software reboot */ 6132ad6b513STimur Tabi 614*8ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 6152ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6162ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 6172ad6b513STimur Tabi #endif 6182ad6b513STimur Tabi 6192ad6b513STimur Tabi 6202ad6b513STimur Tabi /* 6212ad6b513STimur Tabi * Environment Configuration 6222ad6b513STimur Tabi */ 6232ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6242ad6b513STimur Tabi 625255a3577SKim Phillips #ifdef CONFIG_TSEC1 6262ad6b513STimur Tabi #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 6272ad6b513STimur Tabi #endif 6282ad6b513STimur Tabi 629255a3577SKim Phillips #ifdef CONFIG_TSEC2 6302ad6b513STimur Tabi #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 6312ad6b513STimur Tabi #endif 6322ad6b513STimur Tabi 633bf0b542dSKim Phillips #define CONFIG_IPADDR 192.168.1.253 634bf0b542dSKim Phillips #define CONFIG_SERVERIP 192.168.1.1 635bf0b542dSKim Phillips #define CONFIG_GATEWAYIP 192.168.1.1 6362ad6b513STimur Tabi #define CONFIG_NETMASK 255.255.252.0 63798883332STimur Tabi #define CONFIG_NETDEV eth0 6382ad6b513STimur Tabi 6397a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6402ad6b513STimur Tabi #define CONFIG_HOSTNAME mpc8349emitx 6417a78f148STimur Tabi #else 6427a78f148STimur Tabi #define CONFIG_HOSTNAME mpc8349emitxgp 6437a78f148STimur Tabi #endif 6447a78f148STimur Tabi 6457a78f148STimur Tabi /* Default path and filenames */ 646bf0b542dSKim Phillips #define CONFIG_ROOTPATH /nfsroot/rootfs 647bf0b542dSKim Phillips #define CONFIG_BOOTFILE uImage 6487a78f148STimur Tabi #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 6492ad6b513STimur Tabi 6507a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6517a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitx.dtb 6522ad6b513STimur Tabi #else 6537a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitxgp.dtb 6542ad6b513STimur Tabi #endif 6552ad6b513STimur Tabi 6567a78f148STimur Tabi #define CONFIG_BOOTDELAY 0 6577a78f148STimur Tabi 6582ad6b513STimur Tabi #define XMK_STR(x) #x 6592ad6b513STimur Tabi #define MK_STR(x) XMK_STR(x) 6602ad6b513STimur Tabi 66198883332STimur Tabi #define CONFIG_BOOTARGS \ 66298883332STimur Tabi "root=/dev/nfs rw" \ 66398883332STimur Tabi " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 66498883332STimur Tabi " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 66598883332STimur Tabi MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 66698883332STimur Tabi MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 66798883332STimur Tabi " console=ttyS0," MK_STR(CONFIG_BAUDRATE) 66898883332STimur Tabi 6692ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 67098883332STimur Tabi "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 6717a78f148STimur Tabi "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 6727a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 6737a78f148STimur Tabi "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 6747a78f148STimur Tabi "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 6757a78f148STimur Tabi "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 6767a78f148STimur Tabi "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 6777a78f148STimur Tabi "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 678bf0b542dSKim Phillips "fdtaddr=400000\0" \ 6797a78f148STimur Tabi "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 680bf0b542dSKim Phillips 681bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 6827a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 683bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 6847a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 685bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 686bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 687bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 688bf0b542dSKim Phillips 689bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 690bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 6917a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 692bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 693bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 694bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 695bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 6962ad6b513STimur Tabi 6972ad6b513STimur Tabi #undef MK_STR 6982ad6b513STimur Tabi #undef XMK_STR 6992ad6b513STimur Tabi 7002ad6b513STimur Tabi #endif 701