1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22ad6b513STimur Tabi /* 34c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 42ad6b513STimur Tabi */ 52ad6b513STimur Tabi 62ad6b513STimur Tabi /* 77a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 82ad6b513STimur Tabi 92ad6b513STimur Tabi Memory map: 102ad6b513STimur Tabi 112ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 122ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 132ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 142ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 152ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 162ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 177a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 182ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 197a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 207a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 217a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 222ad6b513STimur Tabi 232ad6b513STimur Tabi I2C address list: 242ad6b513STimur Tabi Align. Board 252ad6b513STimur Tabi Bus Addr Part No. Description Length Location 262ad6b513STimur Tabi ---------------------------------------------------------------- 27be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 282ad6b513STimur Tabi 29be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 30be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 31be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 32be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 33be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 34be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 352ad6b513STimur Tabi 362ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 372ad6b513STimur Tabi */ 382ad6b513STimur Tabi 392ad6b513STimur Tabi #ifndef __CONFIG_H 402ad6b513STimur Tabi #define __CONFIG_H 412ad6b513STimur Tabi 4214d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 447a78f148STimur Tabi #endif 452ad6b513STimur Tabi 462ad6b513STimur Tabi /* 472ad6b513STimur Tabi * High Level Configuration Options 482ad6b513STimur Tabi */ 492c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 502ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 512ad6b513STimur Tabi 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 532ad6b513STimur Tabi 5489c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 5589c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 567a78f148STimur Tabi 5789c7784eSTimur Tabi /* 5889c7784eSTimur Tabi * On-board devices 5989c7784eSTimur Tabi */ 607a78f148STimur Tabi 617a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 62396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 63396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 6489c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 65c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 667a78f148STimur Tabi #endif 677a78f148STimur Tabi 682ad6b513STimur Tabi #define CONFIG_RTC_DS1337 6900f792e0SHeiko Schocher #define CONFIG_SYS_I2C 707a78f148STimur Tabi 717a78f148STimur Tabi /* 727a78f148STimur Tabi * Device configurations 737a78f148STimur Tabi */ 742ad6b513STimur Tabi 752ad6b513STimur Tabi /* I2C */ 7600f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 7700f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 7800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 7900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 8000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 8100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 8200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 8300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 842ad6b513STimur Tabi 856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 86b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 872ad6b513STimur Tabi 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 94be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 952ad6b513STimur Tabi 962ad6b513STimur Tabi /* Don't probe these addresses: */ 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1012ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 102396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 103396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1042ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1052ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1062ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1072ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1082ad6b513STimur Tabi 1092ad6b513STimur Tabi #endif 1102ad6b513STimur Tabi 1117a78f148STimur Tabi /* Compact Flash */ 1122ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1132ad6b513STimur Tabi 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1162ad6b513STimur Tabi 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1232ad6b513STimur Tabi 124396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 125396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1262ad6b513STimur Tabi 127c9e34fe2SValeriy Glushkov #endif 128c9e34fe2SValeriy Glushkov 129c9e34fe2SValeriy Glushkov /* 130c9e34fe2SValeriy Glushkov * SATA 131c9e34fe2SValeriy Glushkov */ 132c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 133c9e34fe2SValeriy Glushkov 134c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 135c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1362ad6b513STimur Tabi 1377a78f148STimur Tabi #endif 1382ad6b513STimur Tabi 139c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 140c31e1326SValeriy Glushkov /* 141c31e1326SValeriy Glushkov * Support USB 142c31e1326SValeriy Glushkov */ 143c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 144c31e1326SValeriy Glushkov 145c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 146c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 147c31e1326SValeriy Glushkov #if 1 148c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 149c31e1326SValeriy Glushkov #else 150c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 151c31e1326SValeriy Glushkov #endif 152c31e1326SValeriy Glushkov 153c31e1326SValeriy Glushkov #endif 154c31e1326SValeriy Glushkov 1557a78f148STimur Tabi /* 1567a78f148STimur Tabi * DDR Setup 1577a78f148STimur Tabi */ 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1647a78f148STimur Tabi 165396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 166396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 167f64702b7STimur Tabi 168b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 169b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 170b7be63abSValeriy Glushkov 17100f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 1727a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1737a78f148STimur Tabi #endif 1747a78f148STimur Tabi 175396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 176396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 1782e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 179396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 180396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 1817a78f148STimur Tabi 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1847a78f148STimur Tabi #endif 1857a78f148STimur Tabi 1867a78f148STimur Tabi /* 1877a78f148STimur Tabi *Flash on the Local Bus 1887a78f148STimur Tabi */ 1897a78f148STimur Tabi 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 19100b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 194396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 195396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 1997a78f148STimur Tabi 2007a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2017a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 204396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 205396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2087a78f148STimur Tabi 20989c7784eSTimur Tabi /* Vitesse 7385 */ 21089c7784eSTimur Tabi 21189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 21289c7784eSTimur Tabi 21389c7784eSTimur Tabi #define CONFIG_TSEC2 21489c7784eSTimur Tabi 21589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 21689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 21789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 21889c7784eSTimur Tabi 21989c7784eSTimur Tabi #endif 22089c7784eSTimur Tabi 2217a78f148STimur Tabi /* 2227a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2237a78f148STimur Tabi */ 2247a78f148STimur Tabi 2257a78f148STimur Tabi /* Flash */ 2267a78f148STimur Tabi 2277d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2287d6a0982SJoe Hershberger | BR_PS_16 \ 2297d6a0982SJoe Hershberger | BR_MS_GPCM \ 2307d6a0982SJoe Hershberger | BR_V) 2317d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 232396abba2SJoe Hershberger | OR_UPM_XAM \ 233396abba2SJoe Hershberger | OR_GPCM_CSNT \ 234396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 235396abba2SJoe Hershberger | OR_GPCM_XACS \ 236396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2377d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2387d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 239396abba2SJoe Hershberger | OR_GPCM_EAD) 2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2417d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2427a78f148STimur Tabi 2437a78f148STimur Tabi /* Vitesse 7385 */ 2447a78f148STimur Tabi 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2467a78f148STimur Tabi 24789c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 24889c7784eSTimur Tabi 2497d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2507d6a0982SJoe Hershberger | BR_PS_8 \ 2517d6a0982SJoe Hershberger | BR_MS_GPCM \ 2527d6a0982SJoe Hershberger | BR_V) 253396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 254396abba2SJoe Hershberger | OR_GPCM_CSNT \ 255396abba2SJoe Hershberger | OR_GPCM_XACS \ 256396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 257396abba2SJoe Hershberger | OR_GPCM_SETA \ 2587d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2597d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 260396abba2SJoe Hershberger | OR_GPCM_EAD) 2617a78f148STimur Tabi 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2647a78f148STimur Tabi 2657a78f148STimur Tabi #endif 2667a78f148STimur Tabi 2677a78f148STimur Tabi /* LED */ 2687a78f148STimur Tabi 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2707d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 2717d6a0982SJoe Hershberger | BR_PS_8 \ 2727d6a0982SJoe Hershberger | BR_MS_GPCM \ 2737d6a0982SJoe Hershberger | BR_V) 274396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 275396abba2SJoe Hershberger | OR_GPCM_CSNT \ 276396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 277396abba2SJoe Hershberger | OR_GPCM_XACS \ 278396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 2797d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2807d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 281396abba2SJoe Hershberger | OR_GPCM_EAD) 2827a78f148STimur Tabi 2837a78f148STimur Tabi /* Compact Flash */ 2847a78f148STimur Tabi 2857a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2867a78f148STimur Tabi 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 2887a78f148STimur Tabi 289396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 290396abba2SJoe Hershberger | BR_PS_16 \ 291396abba2SJoe Hershberger | BR_MS_UPMA \ 292396abba2SJoe Hershberger | BR_V) 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2947a78f148STimur Tabi 2956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 2977a78f148STimur Tabi 2987a78f148STimur Tabi #endif 2997a78f148STimur Tabi 3007a78f148STimur Tabi /* 3017a78f148STimur Tabi * U-Boot memory configuration 3027a78f148STimur Tabi */ 30314d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3042ad6b513STimur Tabi 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3072ad6b513STimur Tabi #else 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3092ad6b513STimur Tabi #endif 3102ad6b513STimur Tabi 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 312396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 313553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3142ad6b513STimur Tabi 315396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 316396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3182ad6b513STimur Tabi 3196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 32016c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 321c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3222ad6b513STimur Tabi 3232ad6b513STimur Tabi /* 3242ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3252ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3262ad6b513STimur Tabi * External Local Bus rate is 3272ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3282ad6b513STimur Tabi */ 329c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 330c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3322ad6b513STimur Tabi 333396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 334396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 335396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 336396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3372ad6b513STimur Tabi 3382ad6b513STimur Tabi /* 3392ad6b513STimur Tabi * Serial Port 3402ad6b513STimur Tabi */ 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3442ad6b513STimur Tabi 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3462ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3472ad6b513STimur Tabi 34883302fb8SSimon Glass #define CONSOLE ttyS0 3497a78f148STimur Tabi 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3522ad6b513STimur Tabi 3537a78f148STimur Tabi /* 3547a78f148STimur Tabi * PCI 3557a78f148STimur Tabi */ 3562ad6b513STimur Tabi #ifdef CONFIG_PCI 357842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3582ad6b513STimur Tabi 3592ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3602ad6b513STimur Tabi 3612ad6b513STimur Tabi /* 3622ad6b513STimur Tabi * General PCI 3632ad6b513STimur Tabi * Addresses are mapped 1-1. 3642ad6b513STimur Tabi */ 3656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 368396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 369396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3752ad6b513STimur Tabi 3762ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 377396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 378396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 381396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 382396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 386396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 387396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 3886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 3892ad6b513STimur Tabi #endif 3902ad6b513STimur Tabi 3912ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3922ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 3942ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3952ad6b513STimur Tabi #endif 3962ad6b513STimur Tabi 3972ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3982ad6b513STimur Tabi 3992ad6b513STimur Tabi #endif 4002ad6b513STimur Tabi 4012ae18241SWolfgang Denk #define CONFIG_PCI_66M 4022ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4037a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4047a78f148STimur Tabi #else 4057a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4067a78f148STimur Tabi #endif 4077a78f148STimur Tabi 4082ad6b513STimur Tabi /* TSEC */ 4092ad6b513STimur Tabi 4102ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4112ad6b513STimur Tabi 4122ad6b513STimur Tabi #define CONFIG_MII 4132ad6b513STimur Tabi 414255a3577SKim Phillips #define CONFIG_TSEC1 4152ad6b513STimur Tabi 416255a3577SKim Phillips #ifdef CONFIG_TSEC1 41710327dc5SAndy Fleming #define CONFIG_HAS_ETH0 418255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4202ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4212ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4223a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4232ad6b513STimur Tabi #endif 4242ad6b513STimur Tabi 425255a3577SKim Phillips #ifdef CONFIG_TSEC2 4267a78f148STimur Tabi #define CONFIG_HAS_ETH1 427255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 42989c7784eSTimur Tabi 4302ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4312ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4323a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4332ad6b513STimur Tabi #endif 4342ad6b513STimur Tabi 4352ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4362ad6b513STimur Tabi 4372ad6b513STimur Tabi #endif 4382ad6b513STimur Tabi 4392ad6b513STimur Tabi /* 4402ad6b513STimur Tabi * Environment 4412ad6b513STimur Tabi */ 4427a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4437a78f148STimur Tabi 4446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 445396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 446396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4470e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4480e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4492ad6b513STimur Tabi #else 45000b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 4516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4520e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4532ad6b513STimur Tabi #endif 4542ad6b513STimur Tabi 4552ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4572ad6b513STimur Tabi 4588ea5499aSJon Loeliger /* 459659e2f67SJon Loeliger * BOOTP options 460659e2f67SJon Loeliger */ 461659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 462659e2f67SJon Loeliger 4632ad6b513STimur Tabi /* Watchdog */ 4642ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 4652ad6b513STimur Tabi 4662ad6b513STimur Tabi /* 4672ad6b513STimur Tabi * Miscellaneous configurable options 4682ad6b513STimur Tabi */ 4697a78f148STimur Tabi 4706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 47105f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 4727a78f148STimur Tabi 4732ad6b513STimur Tabi /* 4742ad6b513STimur Tabi * For booting Linux, the board info and command line data 4759f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 4762ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 4772ad6b513STimur Tabi */ 478396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 479396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 48063865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 4812ad6b513STimur Tabi 4826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 4832ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 4842ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 4852ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 4862ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 4872ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 4882ad6b513STimur Tabi 4896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 4906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 4912ad6b513STimur Tabi HRCWH_PCI_HOST |\ 4927a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 4932ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 4947a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 4952ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 4962ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 4972ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 4982ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 4992ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5002ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5012ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5022ad6b513STimur Tabi #else 5036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5042ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5052ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5062ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5077a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5082ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5092ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5102ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5112ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5122ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5132ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5142ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5152ad6b513STimur Tabi #endif 5162ad6b513STimur Tabi 5177a78f148STimur Tabi /* 5187a78f148STimur Tabi * System performance 5197a78f148STimur Tabi */ 5206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 526c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 527c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 5282ad6b513STimur Tabi 5297a78f148STimur Tabi /* 5307a78f148STimur Tabi * System IO Config 5317a78f148STimur Tabi */ 532396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 533396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 534396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 535396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 5362ad6b513STimur Tabi 5371a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 5381a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 5392ad6b513STimur Tabi 5406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 54131d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 5422ad6b513STimur Tabi 5437a78f148STimur Tabi /* DDR */ 544396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 54572cd4087SJoe Hershberger | BATL_PP_RW \ 546396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 547396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 548396abba2SJoe Hershberger | BATU_BL_256M \ 549396abba2SJoe Hershberger | BATU_VS \ 550396abba2SJoe Hershberger | BATU_VP) 5512ad6b513STimur Tabi 5527a78f148STimur Tabi /* PCI */ 5532ad6b513STimur Tabi #ifdef CONFIG_PCI 554396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 55572cd4087SJoe Hershberger | BATL_PP_RW \ 556396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 557396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 558396abba2SJoe Hershberger | BATU_BL_256M \ 559396abba2SJoe Hershberger | BATU_VS \ 560396abba2SJoe Hershberger | BATU_VP) 561396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 56272cd4087SJoe Hershberger | BATL_PP_RW \ 563396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 564396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 565396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 566396abba2SJoe Hershberger | BATU_BL_256M \ 567396abba2SJoe Hershberger | BATU_VS \ 568396abba2SJoe Hershberger | BATU_VP) 5692ad6b513STimur Tabi #else 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 5726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 5736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 5742ad6b513STimur Tabi #endif 5752ad6b513STimur Tabi 5762ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 577396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 57872cd4087SJoe Hershberger | BATL_PP_RW \ 579396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 580396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 581396abba2SJoe Hershberger | BATU_BL_256M \ 582396abba2SJoe Hershberger | BATU_VS \ 583396abba2SJoe Hershberger | BATU_VP) 584396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 58572cd4087SJoe Hershberger | BATL_PP_RW \ 586396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 587396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 588396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 589396abba2SJoe Hershberger | BATU_BL_256M \ 590396abba2SJoe Hershberger | BATU_VS \ 591396abba2SJoe Hershberger | BATU_VP) 5922ad6b513STimur Tabi #else 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 5946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 5956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 5966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 5972ad6b513STimur Tabi #endif 5982ad6b513STimur Tabi 5992ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 600396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 60172cd4087SJoe Hershberger | BATL_PP_RW \ 602396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 603396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 604396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 605396abba2SJoe Hershberger | BATU_BL_256M \ 606396abba2SJoe Hershberger | BATU_VS \ 607396abba2SJoe Hershberger | BATU_VP) 6082ad6b513STimur Tabi 6092ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 610396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 61172cd4087SJoe Hershberger | BATL_PP_RW \ 612396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 613396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 614396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 615396abba2SJoe Hershberger | BATU_BL_256M \ 616396abba2SJoe Hershberger | BATU_VS \ 617396abba2SJoe Hershberger | BATU_VP) 6182ad6b513STimur Tabi 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6212ad6b513STimur Tabi 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 6382ad6b513STimur Tabi 6398ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 6402ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6412ad6b513STimur Tabi #endif 6422ad6b513STimur Tabi 6432ad6b513STimur Tabi /* 6442ad6b513STimur Tabi * Environment Configuration 6452ad6b513STimur Tabi */ 6462ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6472ad6b513STimur Tabi 648396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 6492ad6b513STimur Tabi 6507a78f148STimur Tabi /* Default path and filenames */ 6518b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 652b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 653396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 654396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 6552ad6b513STimur Tabi 6567a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 657396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 6582ad6b513STimur Tabi #else 659396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 6602ad6b513STimur Tabi #endif 6612ad6b513STimur Tabi 6627a78f148STimur Tabi 6632ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 66483302fb8SSimon Glass "console=" __stringify(CONSOLE) "\0" \ 665396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 666396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 6677a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 6685368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6695368c55dSMarek Vasut " +$filesize; " \ 6705368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6715368c55dSMarek Vasut " +$filesize; " \ 6725368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6735368c55dSMarek Vasut " $filesize; " \ 6745368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6755368c55dSMarek Vasut " +$filesize; " \ 6765368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6775368c55dSMarek Vasut " $filesize\0" \ 67805f91a65SKim Phillips "fdtaddr=780000\0" \ 679396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 680bf0b542dSKim Phillips 681bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 6827a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 683bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 6847a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 685bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 686bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 687bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 688bf0b542dSKim Phillips 689bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 690bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 6917a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 692bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 693bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 694bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 695bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 6962ad6b513STimur Tabi 6972ad6b513STimur Tabi #endif 698