12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 52ad6b513STimur Tabi */ 62ad6b513STimur Tabi 72ad6b513STimur Tabi /* 87a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 92ad6b513STimur Tabi 102ad6b513STimur Tabi Memory map: 112ad6b513STimur Tabi 122ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 132ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 142ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 152ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 162ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 172ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 187a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 192ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 207a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 217a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 227a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 232ad6b513STimur Tabi 242ad6b513STimur Tabi I2C address list: 252ad6b513STimur Tabi Align. Board 262ad6b513STimur Tabi Bus Addr Part No. Description Length Location 272ad6b513STimur Tabi ---------------------------------------------------------------- 28be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 292ad6b513STimur Tabi 30be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 31be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 32be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 33be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 34be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 35be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 362ad6b513STimur Tabi 372ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 382ad6b513STimur Tabi */ 392ad6b513STimur Tabi 402ad6b513STimur Tabi #ifndef __CONFIG_H 412ad6b513STimur Tabi #define __CONFIG_H 422ad6b513STimur Tabi 4314d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 457a78f148STimur Tabi #endif 462ad6b513STimur Tabi 472ad6b513STimur Tabi /* 482ad6b513STimur Tabi * High Level Configuration Options 492ad6b513STimur Tabi */ 502c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 512ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 522ad6b513STimur Tabi 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFEF00000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 582ad6b513STimur Tabi 5989c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 6089c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 617a78f148STimur Tabi 6289c7784eSTimur Tabi /* 6389c7784eSTimur Tabi * On-board devices 6489c7784eSTimur Tabi */ 657a78f148STimur Tabi 667a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 67396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 68396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 6989c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 70c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 71c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 727a78f148STimur Tabi #endif 737a78f148STimur Tabi 747a78f148STimur Tabi #define CONFIG_PCI 752ad6b513STimur Tabi #define CONFIG_RTC_DS1337 7600f792e0SHeiko Schocher #define CONFIG_SYS_I2C 777a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 787a78f148STimur Tabi 797a78f148STimur Tabi /* 807a78f148STimur Tabi * Device configurations 817a78f148STimur Tabi */ 822ad6b513STimur Tabi 832ad6b513STimur Tabi /* I2C */ 8400f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 8500f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 8600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 8700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 8800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 8900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 9000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 9100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 922ad6b513STimur Tabi 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 94b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 952ad6b513STimur Tabi 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 102be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1032ad6b513STimur Tabi 1042ad6b513STimur Tabi /* Don't probe these addresses: */ 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1092ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 110396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 111396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1122ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1132ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1142ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1152ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1162ad6b513STimur Tabi 1172ad6b513STimur Tabi #endif 1182ad6b513STimur Tabi 1197a78f148STimur Tabi /* Compact Flash */ 1202ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1212ad6b513STimur Tabi 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1242ad6b513STimur Tabi 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1312ad6b513STimur Tabi 132396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 133396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1342ad6b513STimur Tabi 135c9e34fe2SValeriy Glushkov #endif 136c9e34fe2SValeriy Glushkov 137c9e34fe2SValeriy Glushkov /* 138c9e34fe2SValeriy Glushkov * SATA 139c9e34fe2SValeriy Glushkov */ 140c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 141c9e34fe2SValeriy Glushkov 142c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 143c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 144c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1452ad6b513STimur Tabi 1467a78f148STimur Tabi #endif 1472ad6b513STimur Tabi 148c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 149c31e1326SValeriy Glushkov /* 150c31e1326SValeriy Glushkov * Support USB 151c31e1326SValeriy Glushkov */ 152c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 153c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 154c31e1326SValeriy Glushkov 155c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 156c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 157c31e1326SValeriy Glushkov #if 1 158c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 159c31e1326SValeriy Glushkov #else 160c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 161c31e1326SValeriy Glushkov #endif 162c31e1326SValeriy Glushkov 163c31e1326SValeriy Glushkov #endif 164c31e1326SValeriy Glushkov 1657a78f148STimur Tabi /* 1667a78f148STimur Tabi * DDR Setup 1677a78f148STimur Tabi */ 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1747a78f148STimur Tabi 175396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 176396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 177f64702b7STimur Tabi 178b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 179b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 180b7be63abSValeriy Glushkov 18100f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 1827a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1837a78f148STimur Tabi #endif 1847a78f148STimur Tabi 185396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 186396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 1882e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 189396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 190396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 1917a78f148STimur Tabi 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1947a78f148STimur Tabi #endif 1957a78f148STimur Tabi 1967a78f148STimur Tabi /* 1977a78f148STimur Tabi *Flash on the Local Bus 1987a78f148STimur Tabi */ 1997a78f148STimur Tabi 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20100b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 204396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 205396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2097a78f148STimur Tabi 2107a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2117a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 214396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 215396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2187a78f148STimur Tabi 21989c7784eSTimur Tabi /* Vitesse 7385 */ 22089c7784eSTimur Tabi 22189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 22289c7784eSTimur Tabi 22389c7784eSTimur Tabi #define CONFIG_TSEC2 22489c7784eSTimur Tabi 22589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 22689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 22789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 22889c7784eSTimur Tabi 22989c7784eSTimur Tabi #endif 23089c7784eSTimur Tabi 2317a78f148STimur Tabi /* 2327a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2337a78f148STimur Tabi */ 2347a78f148STimur Tabi 2357a78f148STimur Tabi /* Flash */ 2367a78f148STimur Tabi 2377d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2387d6a0982SJoe Hershberger | BR_PS_16 \ 2397d6a0982SJoe Hershberger | BR_MS_GPCM \ 2407d6a0982SJoe Hershberger | BR_V) 2417d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 242396abba2SJoe Hershberger | OR_UPM_XAM \ 243396abba2SJoe Hershberger | OR_GPCM_CSNT \ 244396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 245396abba2SJoe Hershberger | OR_GPCM_XACS \ 246396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2477d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2487d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 249396abba2SJoe Hershberger | OR_GPCM_EAD) 2506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2517d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2527a78f148STimur Tabi 2537a78f148STimur Tabi /* Vitesse 7385 */ 2547a78f148STimur Tabi 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2567a78f148STimur Tabi 25789c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 25889c7784eSTimur Tabi 2597d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2607d6a0982SJoe Hershberger | BR_PS_8 \ 2617d6a0982SJoe Hershberger | BR_MS_GPCM \ 2627d6a0982SJoe Hershberger | BR_V) 263396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 264396abba2SJoe Hershberger | OR_GPCM_CSNT \ 265396abba2SJoe Hershberger | OR_GPCM_XACS \ 266396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 267396abba2SJoe Hershberger | OR_GPCM_SETA \ 2687d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2697d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 270396abba2SJoe Hershberger | OR_GPCM_EAD) 2717a78f148STimur Tabi 2726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2747a78f148STimur Tabi 2757a78f148STimur Tabi #endif 2767a78f148STimur Tabi 2777a78f148STimur Tabi /* LED */ 2787a78f148STimur Tabi 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2807d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 2817d6a0982SJoe Hershberger | BR_PS_8 \ 2827d6a0982SJoe Hershberger | BR_MS_GPCM \ 2837d6a0982SJoe Hershberger | BR_V) 284396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 285396abba2SJoe Hershberger | OR_GPCM_CSNT \ 286396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 287396abba2SJoe Hershberger | OR_GPCM_XACS \ 288396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 2897d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2907d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 291396abba2SJoe Hershberger | OR_GPCM_EAD) 2927a78f148STimur Tabi 2937a78f148STimur Tabi /* Compact Flash */ 2947a78f148STimur Tabi 2957a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2967a78f148STimur Tabi 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 2987a78f148STimur Tabi 299396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 300396abba2SJoe Hershberger | BR_PS_16 \ 301396abba2SJoe Hershberger | BR_MS_UPMA \ 302396abba2SJoe Hershberger | BR_V) 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 3047a78f148STimur Tabi 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 3077a78f148STimur Tabi 3087a78f148STimur Tabi #endif 3097a78f148STimur Tabi 3107a78f148STimur Tabi /* 3117a78f148STimur Tabi * U-Boot memory configuration 3127a78f148STimur Tabi */ 31314d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3142ad6b513STimur Tabi 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3172ad6b513STimur Tabi #else 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3192ad6b513STimur Tabi #endif 3202ad6b513STimur Tabi 3216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 322396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 323553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3242ad6b513STimur Tabi 325396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 326396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3282ad6b513STimur Tabi 3296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 33016c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 331c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3322ad6b513STimur Tabi 3332ad6b513STimur Tabi /* 3342ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3352ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3362ad6b513STimur Tabi * External Local Bus rate is 3372ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3382ad6b513STimur Tabi */ 339c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 340c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3422ad6b513STimur Tabi 343396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 344396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 345396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 346396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3472ad6b513STimur Tabi 3482ad6b513STimur Tabi /* 3492ad6b513STimur Tabi * Serial Port 3502ad6b513STimur Tabi */ 3512ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3552ad6b513STimur Tabi 3566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3572ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3582ad6b513STimur Tabi 359*83302fb8SSimon Glass #define CONSOLE ttyS0 3607a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3617a78f148STimur Tabi 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3642ad6b513STimur Tabi 3657a78f148STimur Tabi /* 3667a78f148STimur Tabi * PCI 3677a78f148STimur Tabi */ 3682ad6b513STimur Tabi #ifdef CONFIG_PCI 369842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3702ad6b513STimur Tabi 3712ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3722ad6b513STimur Tabi 3732ad6b513STimur Tabi /* 3742ad6b513STimur Tabi * General PCI 3752ad6b513STimur Tabi * Addresses are mapped 1-1. 3762ad6b513STimur Tabi */ 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 380396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 381396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3872ad6b513STimur Tabi 3882ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 389396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 390396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 393396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 394396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 398396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 399396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 4006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 4012ad6b513STimur Tabi #endif 4022ad6b513STimur Tabi 4032ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4042ad6b513STimur Tabi 4052ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 4062ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 4082ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 4092ad6b513STimur Tabi #endif 4102ad6b513STimur Tabi 4112ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 4122ad6b513STimur Tabi 4132ad6b513STimur Tabi #endif 4142ad6b513STimur Tabi 4152ae18241SWolfgang Denk #define CONFIG_PCI_66M 4162ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4177a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4187a78f148STimur Tabi #else 4197a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4207a78f148STimur Tabi #endif 4217a78f148STimur Tabi 4222ad6b513STimur Tabi /* TSEC */ 4232ad6b513STimur Tabi 4242ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4252ad6b513STimur Tabi 4262ad6b513STimur Tabi #define CONFIG_MII 427659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4282ad6b513STimur Tabi 429255a3577SKim Phillips #define CONFIG_TSEC1 4302ad6b513STimur Tabi 431255a3577SKim Phillips #ifdef CONFIG_TSEC1 43210327dc5SAndy Fleming #define CONFIG_HAS_ETH0 433255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4352ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4362ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4373a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4382ad6b513STimur Tabi #endif 4392ad6b513STimur Tabi 440255a3577SKim Phillips #ifdef CONFIG_TSEC2 4417a78f148STimur Tabi #define CONFIG_HAS_ETH1 442255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 44489c7784eSTimur Tabi 4452ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4462ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4473a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4482ad6b513STimur Tabi #endif 4492ad6b513STimur Tabi 4502ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4512ad6b513STimur Tabi 4522ad6b513STimur Tabi #endif 4532ad6b513STimur Tabi 4542ad6b513STimur Tabi /* 4552ad6b513STimur Tabi * Environment 4562ad6b513STimur Tabi */ 4577a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4587a78f148STimur Tabi 4596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4605a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 461396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 462396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4630e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4640e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4652ad6b513STimur Tabi #else 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 46700b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 46893f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4700e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4712ad6b513STimur Tabi #endif 4722ad6b513STimur Tabi 4732ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4752ad6b513STimur Tabi 4768ea5499aSJon Loeliger /* 477659e2f67SJon Loeliger * BOOTP options 478659e2f67SJon Loeliger */ 479659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 480659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 481659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 482659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 483659e2f67SJon Loeliger 484659e2f67SJon Loeliger /* 4858ea5499aSJon Loeliger * Command line configuration. 4868ea5499aSJon Loeliger */ 4878ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4888ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 4898ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 4902ad6b513STimur Tabi 491c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 492c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 493c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 494c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 495c9e34fe2SValeriy Glushkov #endif 496c9e34fe2SValeriy Glushkov 4972ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 4988ea5499aSJon Loeliger #define CONFIG_CMD_IDE 499c9e34fe2SValeriy Glushkov #endif 500c9e34fe2SValeriy Glushkov 501c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 502c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 503c31e1326SValeriy Glushkov #endif 504c31e1326SValeriy Glushkov 505c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 5062ad6b513STimur Tabi #endif 5072ad6b513STimur Tabi 5082ad6b513STimur Tabi #ifdef CONFIG_PCI 5098ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5102ad6b513STimur Tabi #endif 5112ad6b513STimur Tabi 5122ad6b513STimur Tabi /* Watchdog */ 5132ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5142ad6b513STimur Tabi 5152ad6b513STimur Tabi /* 5162ad6b513STimur Tabi * Miscellaneous configurable options 5172ad6b513STimur Tabi */ 5186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5197a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 520a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5217a78f148STimur Tabi 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 52305f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5247a78f148STimur Tabi 5258ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5272ad6b513STimur Tabi #else 5286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5292ad6b513STimur Tabi #endif 5302ad6b513STimur Tabi 531396abba2SJoe Hershberger /* Print Buffer Size */ 532396abba2SJoe Hershberger #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 5336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 534396abba2SJoe Hershberger /* Boot Argument Buffer Size */ 535396abba2SJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5362ad6b513STimur Tabi 5372ad6b513STimur Tabi /* 5382ad6b513STimur Tabi * For booting Linux, the board info and command line data 5399f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 5402ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5412ad6b513STimur Tabi */ 542396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 543396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 54463865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 5452ad6b513STimur Tabi 5466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5472ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5482ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5492ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5502ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5512ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5522ad6b513STimur Tabi 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5552ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5567a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5572ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5587a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5592ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5602ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5612ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5622ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5632ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5642ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5652ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5662ad6b513STimur Tabi #else 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5682ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5692ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5702ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5717a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5722ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5732ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5742ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5752ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5762ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5772ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5782ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5792ad6b513STimur Tabi #endif 5802ad6b513STimur Tabi 5817a78f148STimur Tabi /* 5827a78f148STimur Tabi * System performance 5837a78f148STimur Tabi */ 5846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 590c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 591c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 5922ad6b513STimur Tabi 5937a78f148STimur Tabi /* 5947a78f148STimur Tabi * System IO Config 5957a78f148STimur Tabi */ 596396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 597396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 598396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 599396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 6002ad6b513STimur Tabi 6011a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 6021a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 6032ad6b513STimur Tabi 6046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 60531d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6062ad6b513STimur Tabi 6077a78f148STimur Tabi /* DDR */ 608396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 60972cd4087SJoe Hershberger | BATL_PP_RW \ 610396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 611396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 612396abba2SJoe Hershberger | BATU_BL_256M \ 613396abba2SJoe Hershberger | BATU_VS \ 614396abba2SJoe Hershberger | BATU_VP) 6152ad6b513STimur Tabi 6167a78f148STimur Tabi /* PCI */ 6172ad6b513STimur Tabi #ifdef CONFIG_PCI 618396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 61972cd4087SJoe Hershberger | BATL_PP_RW \ 620396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 621396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 622396abba2SJoe Hershberger | BATU_BL_256M \ 623396abba2SJoe Hershberger | BATU_VS \ 624396abba2SJoe Hershberger | BATU_VP) 625396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 62672cd4087SJoe Hershberger | BATL_PP_RW \ 627396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 628396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 629396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 630396abba2SJoe Hershberger | BATU_BL_256M \ 631396abba2SJoe Hershberger | BATU_VS \ 632396abba2SJoe Hershberger | BATU_VP) 6332ad6b513STimur Tabi #else 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6382ad6b513STimur Tabi #endif 6392ad6b513STimur Tabi 6402ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 641396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 64272cd4087SJoe Hershberger | BATL_PP_RW \ 643396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 644396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 645396abba2SJoe Hershberger | BATU_BL_256M \ 646396abba2SJoe Hershberger | BATU_VS \ 647396abba2SJoe Hershberger | BATU_VP) 648396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 64972cd4087SJoe Hershberger | BATL_PP_RW \ 650396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 651396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 652396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 653396abba2SJoe Hershberger | BATU_BL_256M \ 654396abba2SJoe Hershberger | BATU_VS \ 655396abba2SJoe Hershberger | BATU_VP) 6562ad6b513STimur Tabi #else 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 6586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 6596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 6606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 6612ad6b513STimur Tabi #endif 6622ad6b513STimur Tabi 6632ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 664396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 66572cd4087SJoe Hershberger | BATL_PP_RW \ 666396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 667396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 668396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 669396abba2SJoe Hershberger | BATU_BL_256M \ 670396abba2SJoe Hershberger | BATU_VS \ 671396abba2SJoe Hershberger | BATU_VP) 6722ad6b513STimur Tabi 6732ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 674396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 67572cd4087SJoe Hershberger | BATL_PP_RW \ 676396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 677396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 678396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 679396abba2SJoe Hershberger | BATU_BL_256M \ 680396abba2SJoe Hershberger | BATU_VS \ 681396abba2SJoe Hershberger | BATU_VP) 6822ad6b513STimur Tabi 6836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6852ad6b513STimur Tabi 6866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 7006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 7016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 7022ad6b513STimur Tabi 7038ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 7042ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 7052ad6b513STimur Tabi #endif 7062ad6b513STimur Tabi 7072ad6b513STimur Tabi /* 7082ad6b513STimur Tabi * Environment Configuration 7092ad6b513STimur Tabi */ 7102ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 7112ad6b513STimur Tabi 712396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 7132ad6b513STimur Tabi 7147a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 715396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitx" 7167a78f148STimur Tabi #else 717396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitxgp" 7187a78f148STimur Tabi #endif 7197a78f148STimur Tabi 7207a78f148STimur Tabi /* Default path and filenames */ 7218b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 722b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 723396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 724396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 7252ad6b513STimur Tabi 7267a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 727396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 7282ad6b513STimur Tabi #else 729396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 7302ad6b513STimur Tabi #endif 7312ad6b513STimur Tabi 7327a78f148STimur Tabi 73398883332STimur Tabi #define CONFIG_BOOTARGS \ 73498883332STimur Tabi "root=/dev/nfs rw" \ 7355368c55dSMarek Vasut " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 7365368c55dSMarek Vasut " ip=" __stringify(CONFIG_IPADDR) ":" \ 7375368c55dSMarek Vasut __stringify(CONFIG_SERVERIP) ":" \ 7385368c55dSMarek Vasut __stringify(CONFIG_GATEWAYIP) ":" \ 7395368c55dSMarek Vasut __stringify(CONFIG_NETMASK) ":" \ 740396abba2SJoe Hershberger CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 741*83302fb8SSimon Glass " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE) 74298883332STimur Tabi 7432ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 744*83302fb8SSimon Glass "console=" __stringify(CONSOLE) "\0" \ 745396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 746396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 7477a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 7485368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7495368c55dSMarek Vasut " +$filesize; " \ 7505368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7515368c55dSMarek Vasut " +$filesize; " \ 7525368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7535368c55dSMarek Vasut " $filesize; " \ 7545368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7555368c55dSMarek Vasut " +$filesize; " \ 7565368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7575368c55dSMarek Vasut " $filesize\0" \ 75805f91a65SKim Phillips "fdtaddr=780000\0" \ 759396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 760bf0b542dSKim Phillips 761bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 7627a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 763bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 7647a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 765bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 766bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 767bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 768bf0b542dSKim Phillips 769bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 770bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 7717a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 772bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 773bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 774bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 775bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 7762ad6b513STimur Tabi 7772ad6b513STimur Tabi #endif 778