12ad6b513STimur Tabi /* 22ad6b513STimur Tabi * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 24*7a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34*7a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 36*7a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37*7a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38*7a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 59*7a78f148STimur Tabi #if (TEXT_BASE == 0xFE000000) 60*7a78f148STimur Tabi #define CFG_LOWBOOT 61*7a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 662ad6b513STimur Tabi #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 672ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 682ad6b513STimur Tabi 69*7a78f148STimur Tabi #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ 702ad6b513STimur Tabi 71*7a78f148STimur Tabi 72*7a78f148STimur Tabi /* On-board devices */ 73*7a78f148STimur Tabi 74*7a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 752ad6b513STimur Tabi #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 76*7a78f148STimur Tabi #define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ 77*7a78f148STimur Tabi #endif 78*7a78f148STimur Tabi 79*7a78f148STimur Tabi #define CONFIG_PCI 802ad6b513STimur Tabi #define CONFIG_RTC_DS1337 81*7a78f148STimur Tabi #define CONFIG_HARD_I2C 82*7a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 83*7a78f148STimur Tabi 84*7a78f148STimur Tabi /* 85*7a78f148STimur Tabi * Device configurations 86*7a78f148STimur Tabi */ 872ad6b513STimur Tabi 882ad6b513STimur Tabi /* I2C */ 892ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 902ad6b513STimur Tabi 912ad6b513STimur Tabi #define CONFIG_MISC_INIT_F 922ad6b513STimur Tabi #define CONFIG_MISC_INIT_R 932ad6b513STimur Tabi 94be5e6181STimur Tabi #define CONFIG_FSL_I2C 952ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 962ad6b513STimur Tabi #define CONFIG_I2C_CMD_TREE 972ad6b513STimur Tabi #define CFG_I2C_OFFSET 0x3000 982ad6b513STimur Tabi #define CFG_I2C2_OFFSET 0x3100 99be5e6181STimur Tabi #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 1002ad6b513STimur Tabi 101be5e6181STimur Tabi #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 102be5e6181STimur Tabi #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 103be5e6181STimur Tabi #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 104be5e6181STimur Tabi #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 105be5e6181STimur Tabi #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 106be5e6181STimur Tabi #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 107be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1082ad6b513STimur Tabi 1092ad6b513STimur Tabi #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 1102ad6b513STimur Tabi #define CFG_I2C_SLAVE 0x7F 1112ad6b513STimur Tabi 1122ad6b513STimur Tabi /* Don't probe these addresses: */ 1132ad6b513STimur Tabi #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ 1142ad6b513STimur Tabi {1, CFG_I2C_8574_ADDR2}, \ 1152ad6b513STimur Tabi {1, CFG_I2C_8574A_ADDR1}, \ 1162ad6b513STimur Tabi {1, CFG_I2C_8574A_ADDR2}} 1172ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 1182ad6b513STimur Tabi #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 1192ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1202ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1212ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1222ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1232ad6b513STimur Tabi 1242ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1252ad6b513STimur Tabi 1262ad6b513STimur Tabi #endif 1272ad6b513STimur Tabi 128*7a78f148STimur Tabi /* Compact Flash */ 1292ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1302ad6b513STimur Tabi 1312ad6b513STimur Tabi #define CFG_IDE_MAXBUS 1 1322ad6b513STimur Tabi #define CFG_IDE_MAXDEVICE 1 1332ad6b513STimur Tabi 1342ad6b513STimur Tabi #define CFG_ATA_IDE0_OFFSET 0x0000 1352ad6b513STimur Tabi #define CFG_ATA_BASE_ADDR CFG_CF_BASE 1362ad6b513STimur Tabi #define CFG_ATA_DATA_OFFSET 0x0000 1372ad6b513STimur Tabi #define CFG_ATA_REG_OFFSET 0 1382ad6b513STimur Tabi #define CFG_ATA_ALT_OFFSET 0x0200 1392ad6b513STimur Tabi #define CFG_ATA_STRIDE 2 1402ad6b513STimur Tabi 1412ad6b513STimur Tabi #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 1422ad6b513STimur Tabi 1432ad6b513STimur Tabi #define CONFIG_DOS_PARTITION 1442ad6b513STimur Tabi 145*7a78f148STimur Tabi #endif 1462ad6b513STimur Tabi 147*7a78f148STimur Tabi /* 148*7a78f148STimur Tabi * DDR Setup 149*7a78f148STimur Tabi */ 150*7a78f148STimur Tabi #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 151*7a78f148STimur Tabi #define CFG_SDRAM_BASE CFG_DDR_BASE 152*7a78f148STimur Tabi #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 153*7a78f148STimur Tabi #define CFG_83XX_DDR_USES_CS0 154*7a78f148STimur Tabi #define CFG_MEMTEST_START 0x1000 /* memtest region */ 155*7a78f148STimur Tabi #define CFG_MEMTEST_END 0x2000 156*7a78f148STimur Tabi 157*7a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 158*7a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 159*7a78f148STimur Tabi #endif 160*7a78f148STimur Tabi 161*7a78f148STimur Tabi #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 162*7a78f148STimur Tabi #define CFG_DDR_SIZE 256 /* Mb */ 163*7a78f148STimur Tabi #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 164*7a78f148STimur Tabi 165*7a78f148STimur Tabi #define CFG_DDR_TIMING_1 0x26242321 166*7a78f148STimur Tabi #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 167*7a78f148STimur Tabi #endif 168*7a78f148STimur Tabi 169*7a78f148STimur Tabi /* 170*7a78f148STimur Tabi *Flash on the Local Bus 171*7a78f148STimur Tabi */ 172*7a78f148STimur Tabi 173*7a78f148STimur Tabi #define CFG_FLASH_CFI /* use the Common Flash Interface */ 174*7a78f148STimur Tabi #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 175*7a78f148STimur Tabi #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 176*7a78f148STimur Tabi #define CFG_FLASH_EMPTY_INFO 177*7a78f148STimur Tabi #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 178*7a78f148STimur Tabi #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 179*7a78f148STimur Tabi #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 180*7a78f148STimur Tabi #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 181*7a78f148STimur Tabi 182*7a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 183*7a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 184*7a78f148STimur Tabi #define CFG_FLASH_QUIET_TEST 185*7a78f148STimur Tabi #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 186*7a78f148STimur Tabi #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} 187*7a78f148STimur Tabi #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ 188*7a78f148STimur Tabi #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 189*7a78f148STimur Tabi 190*7a78f148STimur Tabi /* 191*7a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 192*7a78f148STimur Tabi */ 193*7a78f148STimur Tabi 194*7a78f148STimur Tabi /* Flash */ 195*7a78f148STimur Tabi 196*7a78f148STimur Tabi #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) 197*7a78f148STimur Tabi #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 198*7a78f148STimur Tabi OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 199*7a78f148STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 200*7a78f148STimur Tabi #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE 201*7a78f148STimur Tabi #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) 202*7a78f148STimur Tabi 203*7a78f148STimur Tabi /* Vitesse 7385 */ 204*7a78f148STimur Tabi 205*7a78f148STimur Tabi #ifdef CONFIG_VSC7385 206*7a78f148STimur Tabi 207*7a78f148STimur Tabi #define CFG_VSC7385_BASE 0xF8000000 208*7a78f148STimur Tabi 209*7a78f148STimur Tabi #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) 210*7a78f148STimur Tabi #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 211*7a78f148STimur Tabi OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 212*7a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 213*7a78f148STimur Tabi 214*7a78f148STimur Tabi #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE 215*7a78f148STimur Tabi #define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 216*7a78f148STimur Tabi 217*7a78f148STimur Tabi #endif 218*7a78f148STimur Tabi 219*7a78f148STimur Tabi /* LED */ 220*7a78f148STimur Tabi 221*7a78f148STimur Tabi #define CFG_LED_BASE 0xF9000000 222*7a78f148STimur Tabi #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) 223*7a78f148STimur Tabi #define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ 224*7a78f148STimur Tabi OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 225*7a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 226*7a78f148STimur Tabi 227*7a78f148STimur Tabi /* Compact Flash */ 228*7a78f148STimur Tabi 229*7a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 230*7a78f148STimur Tabi 231*7a78f148STimur Tabi #define CFG_CF_BASE 0xF0000000 232*7a78f148STimur Tabi 233*7a78f148STimur Tabi #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 234*7a78f148STimur Tabi #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 235*7a78f148STimur Tabi 236*7a78f148STimur Tabi #define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE 237*7a78f148STimur Tabi #define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 238*7a78f148STimur Tabi 239*7a78f148STimur Tabi #endif 240*7a78f148STimur Tabi 241*7a78f148STimur Tabi /* 242*7a78f148STimur Tabi * U-Boot memory configuration 243*7a78f148STimur Tabi */ 244*7a78f148STimur Tabi #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 2452ad6b513STimur Tabi 2462ad6b513STimur Tabi #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 2472ad6b513STimur Tabi #define CFG_RAMBOOT 2482ad6b513STimur Tabi #else 2492ad6b513STimur Tabi #undef CFG_RAMBOOT 2502ad6b513STimur Tabi #endif 2512ad6b513STimur Tabi 2522ad6b513STimur Tabi #define CONFIG_L1_INIT_RAM 2532ad6b513STimur Tabi #define CFG_INIT_RAM_LOCK 2542ad6b513STimur Tabi #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 2552ad6b513STimur Tabi #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 2562ad6b513STimur Tabi 2572ad6b513STimur Tabi #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 2582ad6b513STimur Tabi #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 2592ad6b513STimur Tabi #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 2602ad6b513STimur Tabi 2612ad6b513STimur Tabi #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2622ad6b513STimur Tabi #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 2632ad6b513STimur Tabi 2642ad6b513STimur Tabi /* 2652ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 2662ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 2672ad6b513STimur Tabi * External Local Bus rate is 2682ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 2692ad6b513STimur Tabi */ 2702ad6b513STimur Tabi #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 2712ad6b513STimur Tabi #define CFG_LBC_LBCR 0x00000000 2722ad6b513STimur Tabi 2732ad6b513STimur Tabi #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 2742ad6b513STimur Tabi #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 2752ad6b513STimur Tabi 2762ad6b513STimur Tabi /* 2772ad6b513STimur Tabi * Serial Port 2782ad6b513STimur Tabi */ 2792ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 2802ad6b513STimur Tabi #undef CONFIG_SERIAL_SOFTWARE_FIFO 2812ad6b513STimur Tabi #define CFG_NS16550 2822ad6b513STimur Tabi #define CFG_NS16550_SERIAL 2832ad6b513STimur Tabi #define CFG_NS16550_REG_SIZE 1 2842ad6b513STimur Tabi #define CFG_NS16550_CLK get_bus_freq(0) 2852ad6b513STimur Tabi 2862ad6b513STimur Tabi #define CFG_BAUDRATE_TABLE \ 2872ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 2882ad6b513STimur Tabi 289*7a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 290*7a78f148STimur Tabi 291d239d74bSTimur Tabi #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) 292d239d74bSTimur Tabi #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) 2932ad6b513STimur Tabi 294bf0b542dSKim Phillips /* pass open firmware flat tree */ 295*7a78f148STimur Tabi #define CONFIG_OF_FLAT_TREE 296*7a78f148STimur Tabi #define CONFIG_OF_BOARD_SETUP 297bf0b542dSKim Phillips 298bf0b542dSKim Phillips /* maximum size of the flat tree (8K) */ 299bf0b542dSKim Phillips #define OF_FLAT_TREE_MAX_SIZE 8192 300bf0b542dSKim Phillips 301bf0b542dSKim Phillips #define OF_CPU "PowerPC,8349@0" 302bf0b542dSKim Phillips #define OF_SOC "soc8349@e0000000" 303bf0b542dSKim Phillips #define OF_TBCLK (bd->bi_busfreq / 4) 304bf0b542dSKim Phillips #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" 3052ad6b513STimur Tabi 306*7a78f148STimur Tabi /* 307*7a78f148STimur Tabi * PCI 308*7a78f148STimur Tabi */ 3092ad6b513STimur Tabi #ifdef CONFIG_PCI 3102ad6b513STimur Tabi 3112ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3122ad6b513STimur Tabi 3132ad6b513STimur Tabi /* 3142ad6b513STimur Tabi * General PCI 3152ad6b513STimur Tabi * Addresses are mapped 1-1. 3162ad6b513STimur Tabi */ 3172ad6b513STimur Tabi #define CFG_PCI1_MEM_BASE 0x80000000 3182ad6b513STimur Tabi #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 3192ad6b513STimur Tabi #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3202ad6b513STimur Tabi #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) 3212ad6b513STimur Tabi #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 3222ad6b513STimur Tabi #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3232ad6b513STimur Tabi #define CFG_PCI1_IO_BASE 0x00000000 3242ad6b513STimur Tabi #define CFG_PCI1_IO_PHYS 0xE2000000 3252ad6b513STimur Tabi #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 3262ad6b513STimur Tabi 3272ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 3282ad6b513STimur Tabi #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) 3292ad6b513STimur Tabi #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 3302ad6b513STimur Tabi #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 3312ad6b513STimur Tabi #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) 3322ad6b513STimur Tabi #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 3332ad6b513STimur Tabi #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3342ad6b513STimur Tabi #define CFG_PCI2_IO_BASE 0x00000000 3352ad6b513STimur Tabi #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) 3362ad6b513STimur Tabi #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ 3372ad6b513STimur Tabi #endif 3382ad6b513STimur Tabi 3392ad6b513STimur Tabi #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 3402ad6b513STimur Tabi 3412ad6b513STimur Tabi #define CONFIG_NET_MULTI 3422ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3432ad6b513STimur Tabi 3442ad6b513STimur Tabi #ifdef CONFIG_RTL8139 3452ad6b513STimur Tabi /* This macro is used by RTL8139 but not defined in PPC architecture */ 3462ad6b513STimur Tabi #define KSEG1ADDR(x) (x) 3472ad6b513STimur Tabi #endif 3482ad6b513STimur Tabi 3492ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3502ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3512ad6b513STimur Tabi #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE 3522ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3532ad6b513STimur Tabi #endif 3542ad6b513STimur Tabi 3552ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3562ad6b513STimur Tabi 3572ad6b513STimur Tabi #endif 3582ad6b513STimur Tabi 359*7a78f148STimur Tabi #define PCI_66M 360*7a78f148STimur Tabi #ifdef PCI_66M 361*7a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 362*7a78f148STimur Tabi #else 363*7a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 364*7a78f148STimur Tabi #endif 365*7a78f148STimur Tabi 3662ad6b513STimur Tabi /* TSEC */ 3672ad6b513STimur Tabi 3682ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 3692ad6b513STimur Tabi 3702ad6b513STimur Tabi #define CONFIG_NET_MULTI 3712ad6b513STimur Tabi #define CONFIG_MII 3722ad6b513STimur Tabi #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ 3732ad6b513STimur Tabi 3742ad6b513STimur Tabi #define CONFIG_MPC83XX_TSEC1 3752ad6b513STimur Tabi 3762ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC1 3772ad6b513STimur Tabi #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 3782ad6b513STimur Tabi #define CFG_TSEC1_OFFSET 0x24000 3792ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 3802ad6b513STimur Tabi #define TSEC1_PHYIDX 0 3812ad6b513STimur Tabi #endif 3822ad6b513STimur Tabi 3832ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC2 384*7a78f148STimur Tabi #define CONFIG_HAS_ETH1 3852ad6b513STimur Tabi #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 3862ad6b513STimur Tabi #define CFG_TSEC2_OFFSET 0x25000 3872ad6b513STimur Tabi #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ 3882ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 3892ad6b513STimur Tabi #define TSEC2_PHYIDX 0 3902ad6b513STimur Tabi #endif 3912ad6b513STimur Tabi 3922ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 3932ad6b513STimur Tabi 3942ad6b513STimur Tabi #endif 3952ad6b513STimur Tabi 3962ad6b513STimur Tabi /* 3972ad6b513STimur Tabi * Environment 3982ad6b513STimur Tabi */ 399*7a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 400*7a78f148STimur Tabi 4012ad6b513STimur Tabi #ifndef CFG_RAMBOOT 4022ad6b513STimur Tabi #define CFG_ENV_IS_IN_FLASH 403*7a78f148STimur Tabi #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 404*7a78f148STimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) 4052ad6b513STimur Tabi #define CFG_ENV_SIZE 0x2000 4062ad6b513STimur Tabi #else 4072ad6b513STimur Tabi #define CFG_NO_FLASH /* Flash is not usable now */ 4082ad6b513STimur Tabi #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4092ad6b513STimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 4102ad6b513STimur Tabi #define CFG_ENV_SIZE 0x2000 4112ad6b513STimur Tabi #endif 4122ad6b513STimur Tabi 4132ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4142ad6b513STimur Tabi #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ 4152ad6b513STimur Tabi 4162ad6b513STimur Tabi /* CONFIG_COMMANDS */ 4172ad6b513STimur Tabi 4182ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 4192ad6b513STimur Tabi #define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) 4202ad6b513STimur Tabi #else 4212ad6b513STimur Tabi #define CONFIG_COMMANDS_CF 0 4222ad6b513STimur Tabi #endif 4232ad6b513STimur Tabi 4242ad6b513STimur Tabi #ifdef CONFIG_PCI 4252ad6b513STimur Tabi #define CONFIG_COMMANDS_PCI CFG_CMD_PCI 4262ad6b513STimur Tabi #else 4272ad6b513STimur Tabi #define CONFIG_COMMANDS_PCI 0 4282ad6b513STimur Tabi #endif 4292ad6b513STimur Tabi 4302ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 4312ad6b513STimur Tabi #define CONFIG_COMMANDS_I2C CFG_CMD_I2C 4322ad6b513STimur Tabi #else 4332ad6b513STimur Tabi #define CONFIG_COMMANDS_I2C 0 4342ad6b513STimur Tabi #endif 4352ad6b513STimur Tabi 4362ad6b513STimur Tabi #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ 4372ad6b513STimur Tabi CONFIG_COMMANDS_CF | \ 4382ad6b513STimur Tabi CFG_CMD_NET | \ 4392ad6b513STimur Tabi CFG_CMD_PING | \ 4402ad6b513STimur Tabi CONFIG_COMMANDS_I2C | \ 4412ad6b513STimur Tabi CONFIG_COMMANDS_PCI | \ 4422ad6b513STimur Tabi CFG_CMD_SDRAM | \ 4432ad6b513STimur Tabi CFG_CMD_DATE | \ 4442ad6b513STimur Tabi CFG_CMD_CACHE | \ 4452ad6b513STimur Tabi CFG_CMD_IRQ) 4462ad6b513STimur Tabi #include <cmd_confdefs.h> 4472ad6b513STimur Tabi 4482ad6b513STimur Tabi /* Watchdog */ 4492ad6b513STimur Tabi 4502ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 4512ad6b513STimur Tabi 4522ad6b513STimur Tabi /* 4532ad6b513STimur Tabi * Miscellaneous configurable options 4542ad6b513STimur Tabi */ 4552ad6b513STimur Tabi #define CFG_LONGHELP /* undef to save memory */ 456*7a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 457*7a78f148STimur Tabi #define CFG_HUSH_PARSER /* Use the HUSH parser */ 458*7a78f148STimur Tabi #define CFG_PROMPT_HUSH_PS2 "> " 459*7a78f148STimur Tabi 4602ad6b513STimur Tabi #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 461*7a78f148STimur Tabi #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 462*7a78f148STimur Tabi 463*7a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 4642ad6b513STimur Tabi #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 465*7a78f148STimur Tabi #else 466*7a78f148STimur Tabi #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 467*7a78f148STimur Tabi #endif 4682ad6b513STimur Tabi 4692ad6b513STimur Tabi #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 4702ad6b513STimur Tabi #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 4712ad6b513STimur Tabi #else 4722ad6b513STimur Tabi #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 4732ad6b513STimur Tabi #endif 4742ad6b513STimur Tabi 4752ad6b513STimur Tabi #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ 4762ad6b513STimur Tabi #define CFG_MAXARGS 16 /* max number of command args */ 4772ad6b513STimur Tabi #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 4782ad6b513STimur Tabi #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 4792ad6b513STimur Tabi 4802ad6b513STimur Tabi /* 4812ad6b513STimur Tabi * For booting Linux, the board info and command line data 4822ad6b513STimur Tabi * have to be in the first 8 MB of memory, since this is 4832ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 4842ad6b513STimur Tabi */ 4852ad6b513STimur Tabi #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 4862ad6b513STimur Tabi 487*7a78f148STimur Tabi /* 488*7a78f148STimur Tabi * Cache Configuration 489*7a78f148STimur Tabi */ 4902ad6b513STimur Tabi #define CFG_DCACHE_SIZE 32768 4912ad6b513STimur Tabi #define CFG_CACHELINE_SIZE 32 4922ad6b513STimur Tabi #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 4932ad6b513STimur Tabi #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ 4942ad6b513STimur Tabi #endif 4952ad6b513STimur Tabi 4962ad6b513STimur Tabi #define CFG_HRCW_LOW (\ 4972ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 4982ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 4992ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5002ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5012ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5022ad6b513STimur Tabi 503*7a78f148STimur Tabi #ifdef CFG_LOWBOOT 5042ad6b513STimur Tabi #define CFG_HRCW_HIGH (\ 5052ad6b513STimur Tabi HRCWH_PCI_HOST |\ 506*7a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5072ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 508*7a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5092ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5102ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5112ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5122ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5132ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5142ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5152ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5162ad6b513STimur Tabi #else 5172ad6b513STimur Tabi #define CFG_HRCW_HIGH (\ 5182ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5192ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5202ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 521*7a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5222ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5232ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5242ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5252ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5262ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5272ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5282ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5292ad6b513STimur Tabi #endif 5302ad6b513STimur Tabi 531*7a78f148STimur Tabi /* 532*7a78f148STimur Tabi * System performance 533*7a78f148STimur Tabi */ 5342ad6b513STimur Tabi #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5352ad6b513STimur Tabi #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5362ad6b513STimur Tabi #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5372ad6b513STimur Tabi #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5382ad6b513STimur Tabi #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 539be5e6181STimur Tabi #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 5402ad6b513STimur Tabi 541*7a78f148STimur Tabi /* 542*7a78f148STimur Tabi * System IO Config 543*7a78f148STimur Tabi */ 5442ad6b513STimur Tabi #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 54598883332STimur Tabi #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) 5462ad6b513STimur Tabi 5472ad6b513STimur Tabi #define CFG_HID0_INIT 0x000000000 5482ad6b513STimur Tabi #define CFG_HID0_FINAL CFG_HID0_INIT 5492ad6b513STimur Tabi 5502ad6b513STimur Tabi #define CFG_HID2 HID2_HBE 5512ad6b513STimur Tabi 552*7a78f148STimur Tabi /* DDR */ 5532ad6b513STimur Tabi #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5542ad6b513STimur Tabi #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5552ad6b513STimur Tabi 556*7a78f148STimur Tabi /* PCI */ 5572ad6b513STimur Tabi #ifdef CONFIG_PCI 5582ad6b513STimur Tabi #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5592ad6b513STimur Tabi #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5602ad6b513STimur Tabi #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5612ad6b513STimur Tabi #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5622ad6b513STimur Tabi #else 5632ad6b513STimur Tabi #define CFG_IBAT1L 0 5642ad6b513STimur Tabi #define CFG_IBAT1U 0 5652ad6b513STimur Tabi #define CFG_IBAT2L 0 5662ad6b513STimur Tabi #define CFG_IBAT2U 0 5672ad6b513STimur Tabi #endif 5682ad6b513STimur Tabi 5692ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 5702ad6b513STimur Tabi #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 5712ad6b513STimur Tabi #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5722ad6b513STimur Tabi #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5732ad6b513STimur Tabi #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5742ad6b513STimur Tabi #else 5752ad6b513STimur Tabi #define CFG_IBAT3L 0 5762ad6b513STimur Tabi #define CFG_IBAT3U 0 5772ad6b513STimur Tabi #define CFG_IBAT4L 0 5782ad6b513STimur Tabi #define CFG_IBAT4U 0 5792ad6b513STimur Tabi #endif 5802ad6b513STimur Tabi 5812ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 582d239d74bSTimur Tabi #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 583d239d74bSTimur Tabi #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 5842ad6b513STimur Tabi 5852ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 5862ad6b513STimur Tabi #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 5872ad6b513STimur Tabi #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 5882ad6b513STimur Tabi 5892ad6b513STimur Tabi #define CFG_IBAT7L 0 5902ad6b513STimur Tabi #define CFG_IBAT7U 0 5912ad6b513STimur Tabi 5922ad6b513STimur Tabi #define CFG_DBAT0L CFG_IBAT0L 5932ad6b513STimur Tabi #define CFG_DBAT0U CFG_IBAT0U 5942ad6b513STimur Tabi #define CFG_DBAT1L CFG_IBAT1L 5952ad6b513STimur Tabi #define CFG_DBAT1U CFG_IBAT1U 5962ad6b513STimur Tabi #define CFG_DBAT2L CFG_IBAT2L 5972ad6b513STimur Tabi #define CFG_DBAT2U CFG_IBAT2U 5982ad6b513STimur Tabi #define CFG_DBAT3L CFG_IBAT3L 5992ad6b513STimur Tabi #define CFG_DBAT3U CFG_IBAT3U 6002ad6b513STimur Tabi #define CFG_DBAT4L CFG_IBAT4L 6012ad6b513STimur Tabi #define CFG_DBAT4U CFG_IBAT4U 6022ad6b513STimur Tabi #define CFG_DBAT5L CFG_IBAT5L 6032ad6b513STimur Tabi #define CFG_DBAT5U CFG_IBAT5U 6042ad6b513STimur Tabi #define CFG_DBAT6L CFG_IBAT6L 6052ad6b513STimur Tabi #define CFG_DBAT6U CFG_IBAT6U 6062ad6b513STimur Tabi #define CFG_DBAT7L CFG_IBAT7L 6072ad6b513STimur Tabi #define CFG_DBAT7U CFG_IBAT7U 6082ad6b513STimur Tabi 6092ad6b513STimur Tabi /* 6102ad6b513STimur Tabi * Internal Definitions 6112ad6b513STimur Tabi * 6122ad6b513STimur Tabi * Boot Flags 6132ad6b513STimur Tabi */ 6142ad6b513STimur Tabi #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 6152ad6b513STimur Tabi #define BOOTFLAG_WARM 0x02 /* Software reboot */ 6162ad6b513STimur Tabi 6172ad6b513STimur Tabi #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 6182ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6192ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 6202ad6b513STimur Tabi #endif 6212ad6b513STimur Tabi 6222ad6b513STimur Tabi 6232ad6b513STimur Tabi /* 6242ad6b513STimur Tabi * Environment Configuration 6252ad6b513STimur Tabi */ 6262ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6272ad6b513STimur Tabi 6282ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC1 6292ad6b513STimur Tabi #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 6302ad6b513STimur Tabi #endif 6312ad6b513STimur Tabi 6322ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_TSEC2 6332ad6b513STimur Tabi #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 6342ad6b513STimur Tabi #endif 6352ad6b513STimur Tabi 636bf0b542dSKim Phillips #define CONFIG_IPADDR 192.168.1.253 637bf0b542dSKim Phillips #define CONFIG_SERVERIP 192.168.1.1 638bf0b542dSKim Phillips #define CONFIG_GATEWAYIP 192.168.1.1 6392ad6b513STimur Tabi #define CONFIG_NETMASK 255.255.252.0 64098883332STimur Tabi #define CONFIG_NETDEV eth0 6412ad6b513STimur Tabi 642*7a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6432ad6b513STimur Tabi #define CONFIG_HOSTNAME mpc8349emitx 644*7a78f148STimur Tabi #else 645*7a78f148STimur Tabi #define CONFIG_HOSTNAME mpc8349emitxgp 646*7a78f148STimur Tabi #endif 647*7a78f148STimur Tabi 648*7a78f148STimur Tabi /* Default path and filenames */ 649bf0b542dSKim Phillips #define CONFIG_ROOTPATH /nfsroot/rootfs 650bf0b542dSKim Phillips #define CONFIG_BOOTFILE uImage 651*7a78f148STimur Tabi #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 6522ad6b513STimur Tabi 653*7a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 654*7a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitx.dtb 6552ad6b513STimur Tabi #else 656*7a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitxgp.dtb 6572ad6b513STimur Tabi #endif 6582ad6b513STimur Tabi 659*7a78f148STimur Tabi #define CONFIG_BOOTDELAY 0 660*7a78f148STimur Tabi 6612ad6b513STimur Tabi #define XMK_STR(x) #x 6622ad6b513STimur Tabi #define MK_STR(x) XMK_STR(x) 6632ad6b513STimur Tabi 66498883332STimur Tabi #define CONFIG_BOOTARGS \ 66598883332STimur Tabi "root=/dev/nfs rw" \ 66698883332STimur Tabi " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 66798883332STimur Tabi " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 66898883332STimur Tabi MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 66998883332STimur Tabi MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 67098883332STimur Tabi " console=ttyS0," MK_STR(CONFIG_BAUDRATE) 67198883332STimur Tabi 6722ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 67398883332STimur Tabi "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 674*7a78f148STimur Tabi "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 675*7a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 676*7a78f148STimur Tabi "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 677*7a78f148STimur Tabi "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 678*7a78f148STimur Tabi "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 679*7a78f148STimur Tabi "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 680*7a78f148STimur Tabi "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 681bf0b542dSKim Phillips "fdtaddr=400000\0" \ 682*7a78f148STimur Tabi "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 683bf0b542dSKim Phillips 684bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 685*7a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 686bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 687*7a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 688bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 689bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 690bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 691bf0b542dSKim Phillips 692bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 693bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 694*7a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 695bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 696bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 697bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 698bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 6992ad6b513STimur Tabi 7002ad6b513STimur Tabi #undef MK_STR 7012ad6b513STimur Tabi #undef XMK_STR 7022ad6b513STimur Tabi 7032ad6b513STimur Tabi #endif 704