12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 52ad6b513STimur Tabi */ 62ad6b513STimur Tabi 72ad6b513STimur Tabi /* 87a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 92ad6b513STimur Tabi 102ad6b513STimur Tabi Memory map: 112ad6b513STimur Tabi 122ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 132ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 142ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 152ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 162ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 172ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 187a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 192ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 207a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 217a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 227a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 232ad6b513STimur Tabi 242ad6b513STimur Tabi I2C address list: 252ad6b513STimur Tabi Align. Board 262ad6b513STimur Tabi Bus Addr Part No. Description Length Location 272ad6b513STimur Tabi ---------------------------------------------------------------- 28be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 292ad6b513STimur Tabi 30be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 31be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 32be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 33be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 34be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 35be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 362ad6b513STimur Tabi 372ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 382ad6b513STimur Tabi */ 392ad6b513STimur Tabi 402ad6b513STimur Tabi #ifndef __CONFIG_H 412ad6b513STimur Tabi #define __CONFIG_H 422ad6b513STimur Tabi 43fdfaa29eSKim Phillips #define CONFIG_DISPLAY_BOARDINFO 44fdfaa29eSKim Phillips 4514d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 477a78f148STimur Tabi #endif 482ad6b513STimur Tabi 492ad6b513STimur Tabi /* 502ad6b513STimur Tabi * High Level Configuration Options 512ad6b513STimur Tabi */ 522c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 532ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 542ad6b513STimur Tabi 552ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 562ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFEF00000 572ae18241SWolfgang Denk #endif 582ae18241SWolfgang Denk 596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 602ad6b513STimur Tabi 6189c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 6289c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 637a78f148STimur Tabi 6489c7784eSTimur Tabi /* 6589c7784eSTimur Tabi * On-board devices 6689c7784eSTimur Tabi */ 677a78f148STimur Tabi 687a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 69396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 70396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 7189c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 72c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 73c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 747a78f148STimur Tabi #endif 757a78f148STimur Tabi 767a78f148STimur Tabi #define CONFIG_PCI 772ad6b513STimur Tabi #define CONFIG_RTC_DS1337 7800f792e0SHeiko Schocher #define CONFIG_SYS_I2C 797a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 807a78f148STimur Tabi 817a78f148STimur Tabi /* 827a78f148STimur Tabi * Device configurations 837a78f148STimur Tabi */ 842ad6b513STimur Tabi 852ad6b513STimur Tabi /* I2C */ 8600f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 8700f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 8800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 8900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 9000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 9100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 9200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 9300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 942ad6b513STimur Tabi 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 96b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 972ad6b513STimur Tabi 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 104be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1052ad6b513STimur Tabi 1062ad6b513STimur Tabi /* Don't probe these addresses: */ 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1112ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 112396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 113396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1142ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1152ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1162ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1172ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1182ad6b513STimur Tabi 1192ad6b513STimur Tabi #endif 1202ad6b513STimur Tabi 1217a78f148STimur Tabi /* Compact Flash */ 1222ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1232ad6b513STimur Tabi 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1262ad6b513STimur Tabi 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1332ad6b513STimur Tabi 134396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 135396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1362ad6b513STimur Tabi 137c9e34fe2SValeriy Glushkov #endif 138c9e34fe2SValeriy Glushkov 139c9e34fe2SValeriy Glushkov /* 140c9e34fe2SValeriy Glushkov * SATA 141c9e34fe2SValeriy Glushkov */ 142c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 143c9e34fe2SValeriy Glushkov 144c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 145c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 146c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1472ad6b513STimur Tabi 1487a78f148STimur Tabi #endif 1492ad6b513STimur Tabi 150c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 151c31e1326SValeriy Glushkov /* 152c31e1326SValeriy Glushkov * Support USB 153c31e1326SValeriy Glushkov */ 154c31e1326SValeriy Glushkov #define CONFIG_USB_STORAGE 155c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 156c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 157c31e1326SValeriy Glushkov 158c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 159c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 160c31e1326SValeriy Glushkov #if 1 161c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 162c31e1326SValeriy Glushkov #else 163c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 164c31e1326SValeriy Glushkov #endif 165c31e1326SValeriy Glushkov 166c31e1326SValeriy Glushkov #endif 167c31e1326SValeriy Glushkov 1687a78f148STimur Tabi /* 1697a78f148STimur Tabi * DDR Setup 1707a78f148STimur Tabi */ 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1777a78f148STimur Tabi 178396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 179396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 180f64702b7STimur Tabi 181b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 182b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 183b7be63abSValeriy Glushkov 18400f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 1857a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1867a78f148STimur Tabi #endif 1877a78f148STimur Tabi 188396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 189396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 1912e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 192396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 193396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 1947a78f148STimur Tabi 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1977a78f148STimur Tabi #endif 1987a78f148STimur Tabi 1997a78f148STimur Tabi /* 2007a78f148STimur Tabi *Flash on the Local Bus 2017a78f148STimur Tabi */ 2027a78f148STimur Tabi 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20400b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 207396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 208396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2127a78f148STimur Tabi 2137a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2147a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 217396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 218396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2217a78f148STimur Tabi 22289c7784eSTimur Tabi /* Vitesse 7385 */ 22389c7784eSTimur Tabi 22489c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 22589c7784eSTimur Tabi 22689c7784eSTimur Tabi #define CONFIG_TSEC2 22789c7784eSTimur Tabi 22889c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 22989c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 23089c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 23189c7784eSTimur Tabi 23289c7784eSTimur Tabi #endif 23389c7784eSTimur Tabi 2347a78f148STimur Tabi /* 2357a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2367a78f148STimur Tabi */ 2377a78f148STimur Tabi 2387a78f148STimur Tabi /* Flash */ 2397a78f148STimur Tabi 2407d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2417d6a0982SJoe Hershberger | BR_PS_16 \ 2427d6a0982SJoe Hershberger | BR_MS_GPCM \ 2437d6a0982SJoe Hershberger | BR_V) 2447d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 245396abba2SJoe Hershberger | OR_UPM_XAM \ 246396abba2SJoe Hershberger | OR_GPCM_CSNT \ 247396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 248396abba2SJoe Hershberger | OR_GPCM_XACS \ 249396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2507d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2517d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 252396abba2SJoe Hershberger | OR_GPCM_EAD) 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2547d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2557a78f148STimur Tabi 2567a78f148STimur Tabi /* Vitesse 7385 */ 2577a78f148STimur Tabi 2586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2597a78f148STimur Tabi 26089c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 26189c7784eSTimur Tabi 2627d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2637d6a0982SJoe Hershberger | BR_PS_8 \ 2647d6a0982SJoe Hershberger | BR_MS_GPCM \ 2657d6a0982SJoe Hershberger | BR_V) 266396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 267396abba2SJoe Hershberger | OR_GPCM_CSNT \ 268396abba2SJoe Hershberger | OR_GPCM_XACS \ 269396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 270396abba2SJoe Hershberger | OR_GPCM_SETA \ 2717d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2727d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 273396abba2SJoe Hershberger | OR_GPCM_EAD) 2747a78f148STimur Tabi 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2777a78f148STimur Tabi 2787a78f148STimur Tabi #endif 2797a78f148STimur Tabi 2807a78f148STimur Tabi /* LED */ 2817a78f148STimur Tabi 2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2837d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 2847d6a0982SJoe Hershberger | BR_PS_8 \ 2857d6a0982SJoe Hershberger | BR_MS_GPCM \ 2867d6a0982SJoe Hershberger | BR_V) 287396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 288396abba2SJoe Hershberger | OR_GPCM_CSNT \ 289396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 290396abba2SJoe Hershberger | OR_GPCM_XACS \ 291396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 2927d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2937d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 294396abba2SJoe Hershberger | OR_GPCM_EAD) 2957a78f148STimur Tabi 2967a78f148STimur Tabi /* Compact Flash */ 2977a78f148STimur Tabi 2987a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2997a78f148STimur Tabi 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 3017a78f148STimur Tabi 302396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 303396abba2SJoe Hershberger | BR_PS_16 \ 304396abba2SJoe Hershberger | BR_MS_UPMA \ 305396abba2SJoe Hershberger | BR_V) 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 3077a78f148STimur Tabi 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 3107a78f148STimur Tabi 3117a78f148STimur Tabi #endif 3127a78f148STimur Tabi 3137a78f148STimur Tabi /* 3147a78f148STimur Tabi * U-Boot memory configuration 3157a78f148STimur Tabi */ 31614d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3172ad6b513STimur Tabi 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3202ad6b513STimur Tabi #else 3216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3222ad6b513STimur Tabi #endif 3232ad6b513STimur Tabi 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 325396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 326553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3272ad6b513STimur Tabi 328396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 329396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3312ad6b513STimur Tabi 3326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 33316c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 334c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3352ad6b513STimur Tabi 3362ad6b513STimur Tabi /* 3372ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3382ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3392ad6b513STimur Tabi * External Local Bus rate is 3402ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3412ad6b513STimur Tabi */ 342c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 343c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3452ad6b513STimur Tabi 346396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 347396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 348396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 349396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3502ad6b513STimur Tabi 3512ad6b513STimur Tabi /* 3522ad6b513STimur Tabi * Serial Port 3532ad6b513STimur Tabi */ 3542ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3582ad6b513STimur Tabi 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3602ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3612ad6b513STimur Tabi 3628a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3637a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3647a78f148STimur Tabi 3656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3672ad6b513STimur Tabi 3687a78f148STimur Tabi /* 3697a78f148STimur Tabi * PCI 3707a78f148STimur Tabi */ 3712ad6b513STimur Tabi #ifdef CONFIG_PCI 372842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3732ad6b513STimur Tabi 3742ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3752ad6b513STimur Tabi 3762ad6b513STimur Tabi /* 3772ad6b513STimur Tabi * General PCI 3782ad6b513STimur Tabi * Addresses are mapped 1-1. 3792ad6b513STimur Tabi */ 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 383396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 384396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3902ad6b513STimur Tabi 3912ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 392396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 393396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 396396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 397396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 4006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 401396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 402396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 4042ad6b513STimur Tabi #endif 4052ad6b513STimur Tabi 4062ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4072ad6b513STimur Tabi 4082ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 4092ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 4112ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 4122ad6b513STimur Tabi #endif 4132ad6b513STimur Tabi 4142ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 4152ad6b513STimur Tabi 4162ad6b513STimur Tabi #endif 4172ad6b513STimur Tabi 4182ae18241SWolfgang Denk #define CONFIG_PCI_66M 4192ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4207a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4217a78f148STimur Tabi #else 4227a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4237a78f148STimur Tabi #endif 4247a78f148STimur Tabi 4252ad6b513STimur Tabi /* TSEC */ 4262ad6b513STimur Tabi 4272ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4282ad6b513STimur Tabi 4292ad6b513STimur Tabi #define CONFIG_MII 430659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4312ad6b513STimur Tabi 432255a3577SKim Phillips #define CONFIG_TSEC1 4332ad6b513STimur Tabi 434255a3577SKim Phillips #ifdef CONFIG_TSEC1 43510327dc5SAndy Fleming #define CONFIG_HAS_ETH0 436255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4382ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4392ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4403a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4412ad6b513STimur Tabi #endif 4422ad6b513STimur Tabi 443255a3577SKim Phillips #ifdef CONFIG_TSEC2 4447a78f148STimur Tabi #define CONFIG_HAS_ETH1 445255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 44789c7784eSTimur Tabi 4482ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4492ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4503a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4512ad6b513STimur Tabi #endif 4522ad6b513STimur Tabi 4532ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4542ad6b513STimur Tabi 4552ad6b513STimur Tabi #endif 4562ad6b513STimur Tabi 4572ad6b513STimur Tabi /* 4582ad6b513STimur Tabi * Environment 4592ad6b513STimur Tabi */ 4607a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4617a78f148STimur Tabi 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4635a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 464396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 465396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4660e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4670e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4682ad6b513STimur Tabi #else 4696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 47000b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 47193f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4730e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4742ad6b513STimur Tabi #endif 4752ad6b513STimur Tabi 4762ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4782ad6b513STimur Tabi 4798ea5499aSJon Loeliger /* 480659e2f67SJon Loeliger * BOOTP options 481659e2f67SJon Loeliger */ 482659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 483659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 484659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 485659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 486659e2f67SJon Loeliger 487659e2f67SJon Loeliger /* 4888ea5499aSJon Loeliger * Command line configuration. 4898ea5499aSJon Loeliger */ 4908ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4918ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 4928ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 4932ad6b513STimur Tabi 494c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 495c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 496c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 497c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 498c9e34fe2SValeriy Glushkov #endif 499c9e34fe2SValeriy Glushkov 5002ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 5018ea5499aSJon Loeliger #define CONFIG_CMD_IDE 502c9e34fe2SValeriy Glushkov #endif 503c9e34fe2SValeriy Glushkov 504c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 505c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 506c31e1326SValeriy Glushkov #endif 507c31e1326SValeriy Glushkov 508c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 5092ad6b513STimur Tabi #endif 5102ad6b513STimur Tabi 5112ad6b513STimur Tabi #ifdef CONFIG_PCI 5128ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5132ad6b513STimur Tabi #endif 5142ad6b513STimur Tabi 5152ad6b513STimur Tabi /* Watchdog */ 5162ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5172ad6b513STimur Tabi 5182ad6b513STimur Tabi /* 5192ad6b513STimur Tabi * Miscellaneous configurable options 5202ad6b513STimur Tabi */ 5216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5227a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 523a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5247a78f148STimur Tabi 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 52605f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5277a78f148STimur Tabi 5288ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5302ad6b513STimur Tabi #else 5316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5322ad6b513STimur Tabi #endif 5332ad6b513STimur Tabi 534396abba2SJoe Hershberger /* Print Buffer Size */ 535396abba2SJoe Hershberger #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 5366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 537396abba2SJoe Hershberger /* Boot Argument Buffer Size */ 538396abba2SJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5392ad6b513STimur Tabi 5402ad6b513STimur Tabi /* 5412ad6b513STimur Tabi * For booting Linux, the board info and command line data 5429f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 5432ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5442ad6b513STimur Tabi */ 545396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 546396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 547*63865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 5482ad6b513STimur Tabi 5496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5502ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5512ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5522ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5532ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5542ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5552ad6b513STimur Tabi 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5582ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5597a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5602ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5617a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5622ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5632ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5642ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5652ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5662ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5672ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5682ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5692ad6b513STimur Tabi #else 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5712ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5722ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5732ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5747a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5752ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5762ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5772ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5782ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5792ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5802ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5812ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5822ad6b513STimur Tabi #endif 5832ad6b513STimur Tabi 5847a78f148STimur Tabi /* 5857a78f148STimur Tabi * System performance 5867a78f148STimur Tabi */ 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 593c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 594c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 5952ad6b513STimur Tabi 5967a78f148STimur Tabi /* 5977a78f148STimur Tabi * System IO Config 5987a78f148STimur Tabi */ 599396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 600396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 601396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 602396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 6032ad6b513STimur Tabi 6041a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 6051a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 6062ad6b513STimur Tabi 6076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 60831d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6092ad6b513STimur Tabi 6107a78f148STimur Tabi /* DDR */ 611396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 61272cd4087SJoe Hershberger | BATL_PP_RW \ 613396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 614396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 615396abba2SJoe Hershberger | BATU_BL_256M \ 616396abba2SJoe Hershberger | BATU_VS \ 617396abba2SJoe Hershberger | BATU_VP) 6182ad6b513STimur Tabi 6197a78f148STimur Tabi /* PCI */ 6202ad6b513STimur Tabi #ifdef CONFIG_PCI 621396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 62272cd4087SJoe Hershberger | BATL_PP_RW \ 623396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 624396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 625396abba2SJoe Hershberger | BATU_BL_256M \ 626396abba2SJoe Hershberger | BATU_VS \ 627396abba2SJoe Hershberger | BATU_VP) 628396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 62972cd4087SJoe Hershberger | BATL_PP_RW \ 630396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 631396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 632396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 633396abba2SJoe Hershberger | BATU_BL_256M \ 634396abba2SJoe Hershberger | BATU_VS \ 635396abba2SJoe Hershberger | BATU_VP) 6362ad6b513STimur Tabi #else 6376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6412ad6b513STimur Tabi #endif 6422ad6b513STimur Tabi 6432ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 644396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 64572cd4087SJoe Hershberger | BATL_PP_RW \ 646396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 647396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 648396abba2SJoe Hershberger | BATU_BL_256M \ 649396abba2SJoe Hershberger | BATU_VS \ 650396abba2SJoe Hershberger | BATU_VP) 651396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 65272cd4087SJoe Hershberger | BATL_PP_RW \ 653396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 654396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 655396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 656396abba2SJoe Hershberger | BATU_BL_256M \ 657396abba2SJoe Hershberger | BATU_VS \ 658396abba2SJoe Hershberger | BATU_VP) 6592ad6b513STimur Tabi #else 6606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 6616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 6626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 6636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 6642ad6b513STimur Tabi #endif 6652ad6b513STimur Tabi 6662ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 667396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 66872cd4087SJoe Hershberger | BATL_PP_RW \ 669396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 670396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 671396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 672396abba2SJoe Hershberger | BATU_BL_256M \ 673396abba2SJoe Hershberger | BATU_VS \ 674396abba2SJoe Hershberger | BATU_VP) 6752ad6b513STimur Tabi 6762ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 677396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 67872cd4087SJoe Hershberger | BATL_PP_RW \ 679396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 680396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 681396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 682396abba2SJoe Hershberger | BATU_BL_256M \ 683396abba2SJoe Hershberger | BATU_VS \ 684396abba2SJoe Hershberger | BATU_VP) 6852ad6b513STimur Tabi 6866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6882ad6b513STimur Tabi 6896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 7006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 7016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 7026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 7036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 7046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 7052ad6b513STimur Tabi 7068ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 7072ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 7082ad6b513STimur Tabi #endif 7092ad6b513STimur Tabi 7102ad6b513STimur Tabi /* 7112ad6b513STimur Tabi * Environment Configuration 7122ad6b513STimur Tabi */ 7132ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 7142ad6b513STimur Tabi 715396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 7162ad6b513STimur Tabi 7177a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 718396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitx" 7197a78f148STimur Tabi #else 720396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitxgp" 7217a78f148STimur Tabi #endif 7227a78f148STimur Tabi 7237a78f148STimur Tabi /* Default path and filenames */ 7248b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 725b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 726396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 727396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 7282ad6b513STimur Tabi 7297a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 730396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 7312ad6b513STimur Tabi #else 732396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 7332ad6b513STimur Tabi #endif 7342ad6b513STimur Tabi 7357a78f148STimur Tabi 73698883332STimur Tabi #define CONFIG_BOOTARGS \ 73798883332STimur Tabi "root=/dev/nfs rw" \ 7385368c55dSMarek Vasut " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 7395368c55dSMarek Vasut " ip=" __stringify(CONFIG_IPADDR) ":" \ 7405368c55dSMarek Vasut __stringify(CONFIG_SERVERIP) ":" \ 7415368c55dSMarek Vasut __stringify(CONFIG_GATEWAYIP) ":" \ 7425368c55dSMarek Vasut __stringify(CONFIG_NETMASK) ":" \ 743396abba2SJoe Hershberger CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 7445368c55dSMarek Vasut " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 74598883332STimur Tabi 7462ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 7475368c55dSMarek Vasut "console=" __stringify(CONFIG_CONSOLE) "\0" \ 748396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 749396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 7507a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 7515368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7525368c55dSMarek Vasut " +$filesize; " \ 7535368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7545368c55dSMarek Vasut " +$filesize; " \ 7555368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7565368c55dSMarek Vasut " $filesize; " \ 7575368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7585368c55dSMarek Vasut " +$filesize; " \ 7595368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7605368c55dSMarek Vasut " $filesize\0" \ 76105f91a65SKim Phillips "fdtaddr=780000\0" \ 762396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 763bf0b542dSKim Phillips 764bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 7657a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 766bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 7677a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 768bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 769bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 770bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 771bf0b542dSKim Phillips 772bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 773bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 7747a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 775bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 776bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 777bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 778bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 7792ad6b513STimur Tabi 7802ad6b513STimur Tabi #endif 781