12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 247a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 347a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 367a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 377a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 387a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 5914d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 617a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 661a2e203bSKim Phillips #define CONFIG_MPC83xx 1 672c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 682ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 692ad6b513STimur Tabi 702ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 712ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFEF00000 722ae18241SWolfgang Denk #endif 732ae18241SWolfgang Denk 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 752ad6b513STimur Tabi 7689c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 7789c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 787a78f148STimur Tabi 7989c7784eSTimur Tabi /* 8089c7784eSTimur Tabi * On-board devices 8189c7784eSTimur Tabi */ 827a78f148STimur Tabi 837a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 84396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 85396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 8689c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 87c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 88c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 897a78f148STimur Tabi #endif 907a78f148STimur Tabi 917a78f148STimur Tabi #define CONFIG_PCI 922ad6b513STimur Tabi #define CONFIG_RTC_DS1337 937a78f148STimur Tabi #define CONFIG_HARD_I2C 947a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 957a78f148STimur Tabi 967a78f148STimur Tabi /* 977a78f148STimur Tabi * Device configurations 987a78f148STimur Tabi */ 992ad6b513STimur Tabi 1002ad6b513STimur Tabi /* I2C */ 1012ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 1022ad6b513STimur Tabi 103be5e6181STimur Tabi #define CONFIG_FSL_I2C 1042ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 108b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 1092ad6b513STimur Tabi 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 116be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1172ad6b513STimur Tabi 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 1202ad6b513STimur Tabi 1212ad6b513STimur Tabi /* Don't probe these addresses: */ 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1262ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 127396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 128396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1292ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1302ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1312ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1322ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1332ad6b513STimur Tabi 1342ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1352ad6b513STimur Tabi 1362ad6b513STimur Tabi #endif 1372ad6b513STimur Tabi 1387a78f148STimur Tabi /* Compact Flash */ 1392ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1402ad6b513STimur Tabi 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1432ad6b513STimur Tabi 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1502ad6b513STimur Tabi 151396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 152396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1532ad6b513STimur Tabi 154c9e34fe2SValeriy Glushkov #endif 155c9e34fe2SValeriy Glushkov 156c9e34fe2SValeriy Glushkov /* 157c9e34fe2SValeriy Glushkov * SATA 158c9e34fe2SValeriy Glushkov */ 159c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 160c9e34fe2SValeriy Glushkov 161c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 162c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 163c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1642ad6b513STimur Tabi 1657a78f148STimur Tabi #endif 1662ad6b513STimur Tabi 167c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 168c31e1326SValeriy Glushkov /* 169c31e1326SValeriy Glushkov * Support USB 170c31e1326SValeriy Glushkov */ 171c31e1326SValeriy Glushkov #define CONFIG_CMD_USB 172c31e1326SValeriy Glushkov #define CONFIG_USB_STORAGE 173c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 174c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 175c31e1326SValeriy Glushkov 176c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 177c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 178c31e1326SValeriy Glushkov #if 1 179c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 180c31e1326SValeriy Glushkov #else 181c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 182c31e1326SValeriy Glushkov #endif 183c31e1326SValeriy Glushkov 184c31e1326SValeriy Glushkov #endif 185c31e1326SValeriy Glushkov 1867a78f148STimur Tabi /* 1877a78f148STimur Tabi * DDR Setup 1887a78f148STimur Tabi */ 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1957a78f148STimur Tabi 196396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 197396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 198f64702b7STimur Tabi 199b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 200b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 201b7be63abSValeriy Glushkov 2027a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 2037a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 2047a78f148STimur Tabi #endif 2057a78f148STimur Tabi 206396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 207396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 2092e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 210396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 211396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 2127a78f148STimur Tabi 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 2157a78f148STimur Tabi #endif 2167a78f148STimur Tabi 2177a78f148STimur Tabi /* 2187a78f148STimur Tabi *Flash on the Local Bus 2197a78f148STimur Tabi */ 2207a78f148STimur Tabi 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 22200b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 225396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 226396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2307a78f148STimur Tabi 2317a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2327a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 235396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 236396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2397a78f148STimur Tabi 24089c7784eSTimur Tabi /* Vitesse 7385 */ 24189c7784eSTimur Tabi 24289c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 24389c7784eSTimur Tabi 24489c7784eSTimur Tabi #define CONFIG_TSEC2 24589c7784eSTimur Tabi 24689c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 24789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 24889c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 24989c7784eSTimur Tabi 25089c7784eSTimur Tabi #endif 25189c7784eSTimur Tabi 2527a78f148STimur Tabi /* 2537a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2547a78f148STimur Tabi */ 2557a78f148STimur Tabi 2567a78f148STimur Tabi /* Flash */ 2577a78f148STimur Tabi 2587d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2597d6a0982SJoe Hershberger | BR_PS_16 \ 2607d6a0982SJoe Hershberger | BR_MS_GPCM \ 2617d6a0982SJoe Hershberger | BR_V) 2627d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 263396abba2SJoe Hershberger | OR_UPM_XAM \ 264396abba2SJoe Hershberger | OR_GPCM_CSNT \ 265396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 266396abba2SJoe Hershberger | OR_GPCM_XACS \ 267396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2687d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2697d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 270396abba2SJoe Hershberger | OR_GPCM_EAD) 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2727d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2737a78f148STimur Tabi 2747a78f148STimur Tabi /* Vitesse 7385 */ 2757a78f148STimur Tabi 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2777a78f148STimur Tabi 27889c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 27989c7784eSTimur Tabi 2807d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2817d6a0982SJoe Hershberger | BR_PS_8 \ 2827d6a0982SJoe Hershberger | BR_MS_GPCM \ 2837d6a0982SJoe Hershberger | BR_V) 284396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 285396abba2SJoe Hershberger | OR_GPCM_CSNT \ 286396abba2SJoe Hershberger | OR_GPCM_XACS \ 287396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 288396abba2SJoe Hershberger | OR_GPCM_SETA \ 2897d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2907d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 291396abba2SJoe Hershberger | OR_GPCM_EAD) 2927a78f148STimur Tabi 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2957a78f148STimur Tabi 2967a78f148STimur Tabi #endif 2977a78f148STimur Tabi 2987a78f148STimur Tabi /* LED */ 2997a78f148STimur Tabi 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 3017d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 3027d6a0982SJoe Hershberger | BR_PS_8 \ 3037d6a0982SJoe Hershberger | BR_MS_GPCM \ 3047d6a0982SJoe Hershberger | BR_V) 305396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 306396abba2SJoe Hershberger | OR_GPCM_CSNT \ 307396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 308396abba2SJoe Hershberger | OR_GPCM_XACS \ 309396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 3107d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3117d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 312396abba2SJoe Hershberger | OR_GPCM_EAD) 3137a78f148STimur Tabi 3147a78f148STimur Tabi /* Compact Flash */ 3157a78f148STimur Tabi 3167a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 3177a78f148STimur Tabi 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 3197a78f148STimur Tabi 320396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 321396abba2SJoe Hershberger | BR_PS_16 \ 322396abba2SJoe Hershberger | BR_MS_UPMA \ 323396abba2SJoe Hershberger | BR_V) 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 3257a78f148STimur Tabi 3266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 3276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 3287a78f148STimur Tabi 3297a78f148STimur Tabi #endif 3307a78f148STimur Tabi 3317a78f148STimur Tabi /* 3327a78f148STimur Tabi * U-Boot memory configuration 3337a78f148STimur Tabi */ 33414d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3352ad6b513STimur Tabi 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3382ad6b513STimur Tabi #else 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3402ad6b513STimur Tabi #endif 3412ad6b513STimur Tabi 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 343396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 344553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3452ad6b513STimur Tabi 346396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 347396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3492ad6b513STimur Tabi 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 3514a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 352c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3532ad6b513STimur Tabi 3542ad6b513STimur Tabi /* 3552ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3562ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3572ad6b513STimur Tabi * External Local Bus rate is 3582ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3592ad6b513STimur Tabi */ 360c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 361c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3632ad6b513STimur Tabi 364396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 365396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 366396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 367396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3682ad6b513STimur Tabi 3692ad6b513STimur Tabi /* 3702ad6b513STimur Tabi * Serial Port 3712ad6b513STimur Tabi */ 3722ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3772ad6b513STimur Tabi 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3792ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3802ad6b513STimur Tabi 3818a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3827a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3837a78f148STimur Tabi 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3862ad6b513STimur Tabi 387bf0b542dSKim Phillips /* pass open firmware flat tree */ 38835cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 3895b8bc606SKim Phillips #define CONFIG_OF_BOARD_SETUP 1 3905b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3912ad6b513STimur Tabi 3927a78f148STimur Tabi /* 3937a78f148STimur Tabi * PCI 3947a78f148STimur Tabi */ 3952ad6b513STimur Tabi #ifdef CONFIG_PCI 3962ad6b513STimur Tabi 3972ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3982ad6b513STimur Tabi 3992ad6b513STimur Tabi /* 4002ad6b513STimur Tabi * General PCI 4012ad6b513STimur Tabi * Addresses are mapped 1-1. 4022ad6b513STimur Tabi */ 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 406396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 407396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 4126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 4132ad6b513STimur Tabi 4142ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 415396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 416396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 4176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 419396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 420396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 4226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 4236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 424396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 425396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 4272ad6b513STimur Tabi #endif 4282ad6b513STimur Tabi 4292ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4302ad6b513STimur Tabi 4312ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 4322ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 4336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 4342ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 4352ad6b513STimur Tabi #endif 4362ad6b513STimur Tabi 4372ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 4382ad6b513STimur Tabi 4392ad6b513STimur Tabi #endif 4402ad6b513STimur Tabi 4412ae18241SWolfgang Denk #define CONFIG_PCI_66M 4422ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4437a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4447a78f148STimur Tabi #else 4457a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4467a78f148STimur Tabi #endif 4477a78f148STimur Tabi 4482ad6b513STimur Tabi /* TSEC */ 4492ad6b513STimur Tabi 4502ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4512ad6b513STimur Tabi 4522ad6b513STimur Tabi #define CONFIG_MII 453659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4542ad6b513STimur Tabi 455255a3577SKim Phillips #define CONFIG_TSEC1 4562ad6b513STimur Tabi 457255a3577SKim Phillips #ifdef CONFIG_TSEC1 45810327dc5SAndy Fleming #define CONFIG_HAS_ETH0 459255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4612ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4622ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4633a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4642ad6b513STimur Tabi #endif 4652ad6b513STimur Tabi 466255a3577SKim Phillips #ifdef CONFIG_TSEC2 4677a78f148STimur Tabi #define CONFIG_HAS_ETH1 468255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 47089c7784eSTimur Tabi 4712ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4722ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4733a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4742ad6b513STimur Tabi #endif 4752ad6b513STimur Tabi 4762ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4772ad6b513STimur Tabi 4782ad6b513STimur Tabi #endif 4792ad6b513STimur Tabi 4802ad6b513STimur Tabi /* 4812ad6b513STimur Tabi * Environment 4822ad6b513STimur Tabi */ 4837a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4847a78f148STimur Tabi 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4865a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 487396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 488396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4890e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4900e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4912ad6b513STimur Tabi #else 4926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 49300b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 49493f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4960e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4972ad6b513STimur Tabi #endif 4982ad6b513STimur Tabi 4992ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 5006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 5012ad6b513STimur Tabi 5028ea5499aSJon Loeliger /* 503659e2f67SJon Loeliger * BOOTP options 504659e2f67SJon Loeliger */ 505659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 506659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 507659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 508659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 509659e2f67SJon Loeliger 510659e2f67SJon Loeliger 511659e2f67SJon Loeliger /* 5128ea5499aSJon Loeliger * Command line configuration. 5138ea5499aSJon Loeliger */ 5148ea5499aSJon Loeliger #include <config_cmd_default.h> 5158ea5499aSJon Loeliger 5168ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 5178ea5499aSJon Loeliger #define CONFIG_CMD_DATE 5188ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 5198ea5499aSJon Loeliger #define CONFIG_CMD_NET 5208ea5499aSJon Loeliger #define CONFIG_CMD_PING 521b7be63abSValeriy Glushkov #define CONFIG_CMD_DHCP 5228ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 5232ad6b513STimur Tabi 524c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 525c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 526c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 527c9e34fe2SValeriy Glushkov #define CONFIG_CMD_FAT 528c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 529c9e34fe2SValeriy Glushkov #endif 530c9e34fe2SValeriy Glushkov 5312ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 5328ea5499aSJon Loeliger #define CONFIG_CMD_IDE 533c9e34fe2SValeriy Glushkov #endif 534c9e34fe2SValeriy Glushkov 535c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 536c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 537c31e1326SValeriy Glushkov #endif 538c31e1326SValeriy Glushkov 539c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 540c9e34fe2SValeriy Glushkov #define CONFIG_CMD_EXT2 5412ad6b513STimur Tabi #endif 5422ad6b513STimur Tabi 5432ad6b513STimur Tabi #ifdef CONFIG_PCI 5448ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5452ad6b513STimur Tabi #endif 5462ad6b513STimur Tabi 5472ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 5488ea5499aSJon Loeliger #define CONFIG_CMD_I2C 5492ad6b513STimur Tabi #endif 5502ad6b513STimur Tabi 5512ad6b513STimur Tabi /* Watchdog */ 5522ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5532ad6b513STimur Tabi 5542ad6b513STimur Tabi /* 5552ad6b513STimur Tabi * Miscellaneous configurable options 5562ad6b513STimur Tabi */ 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5587a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 559a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 5617a78f148STimur Tabi 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 56305f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5647a78f148STimur Tabi 5657a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5677a78f148STimur Tabi #else 5686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 5697a78f148STimur Tabi #endif 5702ad6b513STimur Tabi 5718ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5732ad6b513STimur Tabi #else 5746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5752ad6b513STimur Tabi #endif 5762ad6b513STimur Tabi 577396abba2SJoe Hershberger /* Print Buffer Size */ 578396abba2SJoe Hershberger #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 580396abba2SJoe Hershberger /* Boot Argument Buffer Size */ 581396abba2SJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 5832ad6b513STimur Tabi 5842ad6b513STimur Tabi /* 5852ad6b513STimur Tabi * For booting Linux, the board info and command line data 5869f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 5872ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5882ad6b513STimur Tabi */ 589396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 590396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 5912ad6b513STimur Tabi 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5932ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5942ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5952ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5962ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5972ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5982ad6b513STimur Tabi 5996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 6006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 6012ad6b513STimur Tabi HRCWH_PCI_HOST |\ 6027a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 6032ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 6047a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 6052ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 6062ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 6072ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 6082ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 6092ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 6102ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 6112ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 6122ad6b513STimur Tabi #else 6136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 6142ad6b513STimur Tabi HRCWH_PCI_HOST |\ 6152ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 6162ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 6177a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 6182ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 6192ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 6202ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 6212ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 6222ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 6232ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 6242ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 6252ad6b513STimur Tabi #endif 6262ad6b513STimur Tabi 6277a78f148STimur Tabi /* 6287a78f148STimur Tabi * System performance 6297a78f148STimur Tabi */ 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 6316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 6326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 636c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 637c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 6382ad6b513STimur Tabi 6397a78f148STimur Tabi /* 6407a78f148STimur Tabi * System IO Config 6417a78f148STimur Tabi */ 642396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 643396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 644396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 645396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 6462ad6b513STimur Tabi 6471a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 6481a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 6492ad6b513STimur Tabi 6506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 65131d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6522ad6b513STimur Tabi 6537a78f148STimur Tabi /* DDR */ 654396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 65572cd4087SJoe Hershberger | BATL_PP_RW \ 656396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 657396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 658396abba2SJoe Hershberger | BATU_BL_256M \ 659396abba2SJoe Hershberger | BATU_VS \ 660396abba2SJoe Hershberger | BATU_VP) 6612ad6b513STimur Tabi 6627a78f148STimur Tabi /* PCI */ 6632ad6b513STimur Tabi #ifdef CONFIG_PCI 664396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 66572cd4087SJoe Hershberger | BATL_PP_RW \ 666396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 667396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 668396abba2SJoe Hershberger | BATU_BL_256M \ 669396abba2SJoe Hershberger | BATU_VS \ 670396abba2SJoe Hershberger | BATU_VP) 671396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 67272cd4087SJoe Hershberger | BATL_PP_RW \ 673396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 674396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 675396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 676396abba2SJoe Hershberger | BATU_BL_256M \ 677396abba2SJoe Hershberger | BATU_VS \ 678396abba2SJoe Hershberger | BATU_VP) 6792ad6b513STimur Tabi #else 6806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6842ad6b513STimur Tabi #endif 6852ad6b513STimur Tabi 6862ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 687396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 68872cd4087SJoe Hershberger | BATL_PP_RW \ 689396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 690396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 691396abba2SJoe Hershberger | BATU_BL_256M \ 692396abba2SJoe Hershberger | BATU_VS \ 693396abba2SJoe Hershberger | BATU_VP) 694396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 69572cd4087SJoe Hershberger | BATL_PP_RW \ 696396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 697396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 698396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 699396abba2SJoe Hershberger | BATU_BL_256M \ 700396abba2SJoe Hershberger | BATU_VS \ 701396abba2SJoe Hershberger | BATU_VP) 7022ad6b513STimur Tabi #else 7036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 7046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 7056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 7066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 7072ad6b513STimur Tabi #endif 7082ad6b513STimur Tabi 7092ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 710396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 71172cd4087SJoe Hershberger | BATL_PP_RW \ 712396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 713396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 714396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 715396abba2SJoe Hershberger | BATU_BL_256M \ 716396abba2SJoe Hershberger | BATU_VS \ 717396abba2SJoe Hershberger | BATU_VP) 7182ad6b513STimur Tabi 7192ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 720396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 72172cd4087SJoe Hershberger | BATL_PP_RW \ 722396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 723396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 724396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 725396abba2SJoe Hershberger | BATU_BL_256M \ 726396abba2SJoe Hershberger | BATU_VS \ 727396abba2SJoe Hershberger | BATU_VP) 7282ad6b513STimur Tabi 7296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 7306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 7312ad6b513STimur Tabi 7326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 7336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 7346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 7356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 7366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 7376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 7386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 7396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 7406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 7416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 7426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 7436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 7446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 7456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 7466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 7476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 7482ad6b513STimur Tabi 7498ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 7502ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 7512ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 7522ad6b513STimur Tabi #endif 7532ad6b513STimur Tabi 7542ad6b513STimur Tabi 7552ad6b513STimur Tabi /* 7562ad6b513STimur Tabi * Environment Configuration 7572ad6b513STimur Tabi */ 7582ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 7592ad6b513STimur Tabi 760396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 7612ad6b513STimur Tabi 7627a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 763396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitx" 7647a78f148STimur Tabi #else 765396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitxgp" 7667a78f148STimur Tabi #endif 7677a78f148STimur Tabi 7687a78f148STimur Tabi /* Default path and filenames */ 7698b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 770b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 771396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 772396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 7732ad6b513STimur Tabi 7747a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 775396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 7762ad6b513STimur Tabi #else 777396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 7782ad6b513STimur Tabi #endif 7792ad6b513STimur Tabi 78005f91a65SKim Phillips #define CONFIG_BOOTDELAY 6 7817a78f148STimur Tabi 78298883332STimur Tabi #define CONFIG_BOOTARGS \ 78398883332STimur Tabi "root=/dev/nfs rw" \ 784*5368c55dSMarek Vasut " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 785*5368c55dSMarek Vasut " ip=" __stringify(CONFIG_IPADDR) ":" \ 786*5368c55dSMarek Vasut __stringify(CONFIG_SERVERIP) ":" \ 787*5368c55dSMarek Vasut __stringify(CONFIG_GATEWAYIP) ":" \ 788*5368c55dSMarek Vasut __stringify(CONFIG_NETMASK) ":" \ 789396abba2SJoe Hershberger CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 790*5368c55dSMarek Vasut " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 79198883332STimur Tabi 7922ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 793*5368c55dSMarek Vasut "console=" __stringify(CONFIG_CONSOLE) "\0" \ 794396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 795396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 7967a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 797*5368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 798*5368c55dSMarek Vasut " +$filesize; " \ 799*5368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 800*5368c55dSMarek Vasut " +$filesize; " \ 801*5368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 802*5368c55dSMarek Vasut " $filesize; " \ 803*5368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 804*5368c55dSMarek Vasut " +$filesize; " \ 805*5368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 806*5368c55dSMarek Vasut " $filesize\0" \ 80705f91a65SKim Phillips "fdtaddr=780000\0" \ 808396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 809bf0b542dSKim Phillips 810bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 8117a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 812bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 8137a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 814bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 815bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 816bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 817bf0b542dSKim Phillips 818bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 819bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 8207a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 821bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 822bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 823bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 824bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 8252ad6b513STimur Tabi 8262ad6b513STimur Tabi #endif 827