12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 247a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 347a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 367a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 377a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 387a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 5914d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 617a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 661a2e203bSKim Phillips #define CONFIG_MPC83xx 1 672c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 682ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 692ad6b513STimur Tabi 70*2ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 71*2ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFEF00000 72*2ae18241SWolfgang Denk #endif 73*2ae18241SWolfgang Denk 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 752ad6b513STimur Tabi 7689c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 7789c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 787a78f148STimur Tabi 7989c7784eSTimur Tabi /* 8089c7784eSTimur Tabi * On-board devices 8189c7784eSTimur Tabi */ 827a78f148STimur Tabi 837a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 842ad6b513STimur Tabi #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 8589c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 86c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 87c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 887a78f148STimur Tabi #endif 897a78f148STimur Tabi 907a78f148STimur Tabi #define CONFIG_PCI 912ad6b513STimur Tabi #define CONFIG_RTC_DS1337 927a78f148STimur Tabi #define CONFIG_HARD_I2C 937a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 947a78f148STimur Tabi 957a78f148STimur Tabi /* 967a78f148STimur Tabi * Device configurations 977a78f148STimur Tabi */ 982ad6b513STimur Tabi 992ad6b513STimur Tabi /* I2C */ 1002ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 1012ad6b513STimur Tabi 102be5e6181STimur Tabi #define CONFIG_FSL_I2C 1032ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 107b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 1082ad6b513STimur Tabi 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 115be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1162ad6b513STimur Tabi 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 1192ad6b513STimur Tabi 1202ad6b513STimur Tabi /* Don't probe these addresses: */ 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2}} 1252ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 1262ad6b513STimur Tabi #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 1272ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1282ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1292ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1302ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1312ad6b513STimur Tabi 1322ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1332ad6b513STimur Tabi 1342ad6b513STimur Tabi #endif 1352ad6b513STimur Tabi 1367a78f148STimur Tabi /* Compact Flash */ 1372ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1382ad6b513STimur Tabi 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1412ad6b513STimur Tabi 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1482ad6b513STimur Tabi 1492ad6b513STimur Tabi #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 1502ad6b513STimur Tabi 151c9e34fe2SValeriy Glushkov #endif 152c9e34fe2SValeriy Glushkov 153c9e34fe2SValeriy Glushkov /* 154c9e34fe2SValeriy Glushkov * SATA 155c9e34fe2SValeriy Glushkov */ 156c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 157c9e34fe2SValeriy Glushkov 158c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 159c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 160c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1612ad6b513STimur Tabi 1627a78f148STimur Tabi #endif 1632ad6b513STimur Tabi 164c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 165c31e1326SValeriy Glushkov /* 166c31e1326SValeriy Glushkov * Support USB 167c31e1326SValeriy Glushkov */ 168c31e1326SValeriy Glushkov #define CONFIG_CMD_USB 169c31e1326SValeriy Glushkov #define CONFIG_USB_STORAGE 170c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 171c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 172c31e1326SValeriy Glushkov 173c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 174c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 175c31e1326SValeriy Glushkov #if 1 176c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 177c31e1326SValeriy Glushkov #else 178c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 179c31e1326SValeriy Glushkov #endif 180c31e1326SValeriy Glushkov 181c31e1326SValeriy Glushkov #endif 182c31e1326SValeriy Glushkov 1837a78f148STimur Tabi /* 1847a78f148STimur Tabi * DDR Setup 1857a78f148STimur Tabi */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1927a78f148STimur Tabi 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 194507e2d79SJoe D'Abbraccio DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 195f64702b7STimur Tabi 196b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 197b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 198b7be63abSValeriy Glushkov 1997a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 2007a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 2017a78f148STimur Tabi #endif 2027a78f148STimur Tabi 2037a78f148STimur Tabi #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 2067a78f148STimur Tabi 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 2097a78f148STimur Tabi #endif 2107a78f148STimur Tabi 2117a78f148STimur Tabi /* 2127a78f148STimur Tabi *Flash on the Local Bus 2137a78f148STimur Tabi */ 2147a78f148STimur Tabi 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 21600b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2237a78f148STimur Tabi 2247a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2257a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2327a78f148STimur Tabi 23389c7784eSTimur Tabi /* Vitesse 7385 */ 23489c7784eSTimur Tabi 23589c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 23689c7784eSTimur Tabi 23789c7784eSTimur Tabi #define CONFIG_TSEC2 23889c7784eSTimur Tabi 23989c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 24089c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 24189c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 24289c7784eSTimur Tabi 24389c7784eSTimur Tabi #endif 24489c7784eSTimur Tabi 2457a78f148STimur Tabi /* 2467a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2477a78f148STimur Tabi */ 2487a78f148STimur Tabi 2497a78f148STimur Tabi /* Flash */ 2507a78f148STimur Tabi 2516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 253f9023afbSAnton Vorontsov OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 2547a78f148STimur Tabi OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 2577a78f148STimur Tabi 2587a78f148STimur Tabi /* Vitesse 7385 */ 2597a78f148STimur Tabi 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2617a78f148STimur Tabi 26289c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 26389c7784eSTimur Tabi 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 2667a78f148STimur Tabi OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 2677a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2687a78f148STimur Tabi 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2717a78f148STimur Tabi 2727a78f148STimur Tabi #endif 2737a78f148STimur Tabi 2747a78f148STimur Tabi /* LED */ 2757a78f148STimur Tabi 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 2797a78f148STimur Tabi OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 2807a78f148STimur Tabi OR_GPCM_EHTR | OR_GPCM_EAD) 2817a78f148STimur Tabi 2827a78f148STimur Tabi /* Compact Flash */ 2837a78f148STimur Tabi 2847a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2857a78f148STimur Tabi 2866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 2877a78f148STimur Tabi 2886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2907a78f148STimur Tabi 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 2937a78f148STimur Tabi 2947a78f148STimur Tabi #endif 2957a78f148STimur Tabi 2967a78f148STimur Tabi /* 2977a78f148STimur Tabi * U-Boot memory configuration 2987a78f148STimur Tabi */ 29914d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3002ad6b513STimur Tabi 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3032ad6b513STimur Tabi #else 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3052ad6b513STimur Tabi #endif 3062ad6b513STimur Tabi 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 3102ad6b513STimur Tabi 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 3126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3142ad6b513STimur Tabi 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 3164a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 3176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 3182ad6b513STimur Tabi 3192ad6b513STimur Tabi /* 3202ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3212ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3222ad6b513STimur Tabi * External Local Bus rate is 3232ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3242ad6b513STimur Tabi */ 325c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 326c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3282ad6b513STimur Tabi 3296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 3306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 3312ad6b513STimur Tabi 3322ad6b513STimur Tabi /* 3332ad6b513STimur Tabi * Serial Port 3342ad6b513STimur Tabi */ 3352ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3402ad6b513STimur Tabi 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3422ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3432ad6b513STimur Tabi 3448a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3457a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3467a78f148STimur Tabi 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3492ad6b513STimur Tabi 350bf0b542dSKim Phillips /* pass open firmware flat tree */ 35135cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 3525b8bc606SKim Phillips #define CONFIG_OF_BOARD_SETUP 1 3535b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3542ad6b513STimur Tabi 3557a78f148STimur Tabi /* 3567a78f148STimur Tabi * PCI 3577a78f148STimur Tabi */ 3582ad6b513STimur Tabi #ifdef CONFIG_PCI 3592ad6b513STimur Tabi 3602ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3612ad6b513STimur Tabi 3622ad6b513STimur Tabi /* 3632ad6b513STimur Tabi * General PCI 3642ad6b513STimur Tabi * Addresses are mapped 1-1. 3652ad6b513STimur Tabi */ 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3752ad6b513STimur Tabi 3762ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 3862ad6b513STimur Tabi #endif 3872ad6b513STimur Tabi 3882ad6b513STimur Tabi #define CONFIG_NET_MULTI 3892ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3902ad6b513STimur Tabi 3912ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3922ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 3942ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3952ad6b513STimur Tabi #endif 3962ad6b513STimur Tabi 3972ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3982ad6b513STimur Tabi 3992ad6b513STimur Tabi #endif 4002ad6b513STimur Tabi 401*2ae18241SWolfgang Denk #define CONFIG_PCI_66M 402*2ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4037a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4047a78f148STimur Tabi #else 4057a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4067a78f148STimur Tabi #endif 4077a78f148STimur Tabi 4082ad6b513STimur Tabi /* TSEC */ 4092ad6b513STimur Tabi 4102ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4112ad6b513STimur Tabi 4122ad6b513STimur Tabi #define CONFIG_NET_MULTI 4132ad6b513STimur Tabi #define CONFIG_MII 414659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4152ad6b513STimur Tabi 416255a3577SKim Phillips #define CONFIG_TSEC1 4172ad6b513STimur Tabi 418255a3577SKim Phillips #ifdef CONFIG_TSEC1 41910327dc5SAndy Fleming #define CONFIG_HAS_ETH0 420255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4222ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4232ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4243a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4252ad6b513STimur Tabi #endif 4262ad6b513STimur Tabi 427255a3577SKim Phillips #ifdef CONFIG_TSEC2 4287a78f148STimur Tabi #define CONFIG_HAS_ETH1 429255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 43189c7784eSTimur Tabi 4322ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4332ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4343a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4352ad6b513STimur Tabi #endif 4362ad6b513STimur Tabi 4372ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4382ad6b513STimur Tabi 4392ad6b513STimur Tabi #endif 4402ad6b513STimur Tabi 4412ad6b513STimur Tabi /* 4422ad6b513STimur Tabi * Environment 4432ad6b513STimur Tabi */ 4447a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4457a78f148STimur Tabi 4466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4475a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4490e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4500e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4512ad6b513STimur Tabi #else 4526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 45300b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 45493f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4560e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4572ad6b513STimur Tabi #endif 4582ad6b513STimur Tabi 4592ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4612ad6b513STimur Tabi 4628ea5499aSJon Loeliger /* 463659e2f67SJon Loeliger * BOOTP options 464659e2f67SJon Loeliger */ 465659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 466659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 467659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 468659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 469659e2f67SJon Loeliger 470659e2f67SJon Loeliger 471659e2f67SJon Loeliger /* 4728ea5499aSJon Loeliger * Command line configuration. 4738ea5499aSJon Loeliger */ 4748ea5499aSJon Loeliger #include <config_cmd_default.h> 4758ea5499aSJon Loeliger 4768ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 4778ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4788ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 4798ea5499aSJon Loeliger #define CONFIG_CMD_NET 4808ea5499aSJon Loeliger #define CONFIG_CMD_PING 481b7be63abSValeriy Glushkov #define CONFIG_CMD_DHCP 4828ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 4832ad6b513STimur Tabi 484c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 485c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 486c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 487c9e34fe2SValeriy Glushkov #define CONFIG_CMD_FAT 488c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 489c9e34fe2SValeriy Glushkov #endif 490c9e34fe2SValeriy Glushkov 4912ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 4928ea5499aSJon Loeliger #define CONFIG_CMD_IDE 493c9e34fe2SValeriy Glushkov #endif 494c9e34fe2SValeriy Glushkov 495c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 496c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 497c31e1326SValeriy Glushkov #endif 498c31e1326SValeriy Glushkov 499c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 500c9e34fe2SValeriy Glushkov #define CONFIG_CMD_EXT2 5012ad6b513STimur Tabi #endif 5022ad6b513STimur Tabi 5032ad6b513STimur Tabi #ifdef CONFIG_PCI 5048ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5052ad6b513STimur Tabi #endif 5062ad6b513STimur Tabi 5072ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 5088ea5499aSJon Loeliger #define CONFIG_CMD_I2C 5092ad6b513STimur Tabi #endif 5102ad6b513STimur Tabi 5112ad6b513STimur Tabi /* Watchdog */ 5122ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5132ad6b513STimur Tabi 5142ad6b513STimur Tabi /* 5152ad6b513STimur Tabi * Miscellaneous configurable options 5162ad6b513STimur Tabi */ 5176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5187a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 519a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 5216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 5227a78f148STimur Tabi 5236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 52405f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5257a78f148STimur Tabi 5267a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 5276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5287a78f148STimur Tabi #else 5296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 5307a78f148STimur Tabi #endif 5312ad6b513STimur Tabi 5328ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5342ad6b513STimur Tabi #else 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5362ad6b513STimur Tabi #endif 5372ad6b513STimur Tabi 5386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 5406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 5416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 5422ad6b513STimur Tabi 5432ad6b513STimur Tabi /* 5442ad6b513STimur Tabi * For booting Linux, the board info and command line data 5459f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 5462ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5472ad6b513STimur Tabi */ 5489f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 5492ad6b513STimur Tabi 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5512ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5522ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5532ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5542ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5552ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5562ad6b513STimur Tabi 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5592ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5607a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5612ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5627a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5632ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5642ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5652ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5662ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5672ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5682ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5692ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5702ad6b513STimur Tabi #else 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5722ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5732ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 5742ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5757a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5762ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5772ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5782ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5792ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5802ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5812ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5822ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII ) 5832ad6b513STimur Tabi #endif 5842ad6b513STimur Tabi 5857a78f148STimur Tabi /* 5867a78f148STimur Tabi * System performance 5877a78f148STimur Tabi */ 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 594c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 595c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 5962ad6b513STimur Tabi 5977a78f148STimur Tabi /* 5987a78f148STimur Tabi * System IO Config 5997a78f148STimur Tabi */ 6006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 601c31e1326SValeriy Glushkov #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */ 6022ad6b513STimur Tabi 6031a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 6041a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 6052ad6b513STimur Tabi 6066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 60731d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6082ad6b513STimur Tabi 6097a78f148STimur Tabi /* DDR */ 6106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6122ad6b513STimur Tabi 6137a78f148STimur Tabi /* PCI */ 6142ad6b513STimur Tabi #ifdef CONFIG_PCI 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6192ad6b513STimur Tabi #else 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6242ad6b513STimur Tabi #endif 6252ad6b513STimur Tabi 6262ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 6286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 6312ad6b513STimur Tabi #else 6326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 6362ad6b513STimur Tabi #endif 6372ad6b513STimur Tabi 6382ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 6396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 6412ad6b513STimur Tabi 6422ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 643c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 644c1230980SScott Wood BATL_GUARDEDSTORAGE) 6456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 6462ad6b513STimur Tabi 6476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6492ad6b513STimur Tabi 6506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 6662ad6b513STimur Tabi 6672ad6b513STimur Tabi /* 6682ad6b513STimur Tabi * Internal Definitions 6692ad6b513STimur Tabi * 6702ad6b513STimur Tabi * Boot Flags 6712ad6b513STimur Tabi */ 6722ad6b513STimur Tabi #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 6732ad6b513STimur Tabi #define BOOTFLAG_WARM 0x02 /* Software reboot */ 6742ad6b513STimur Tabi 6758ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 6762ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6772ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 6782ad6b513STimur Tabi #endif 6792ad6b513STimur Tabi 6802ad6b513STimur Tabi 6812ad6b513STimur Tabi /* 6822ad6b513STimur Tabi * Environment Configuration 6832ad6b513STimur Tabi */ 6842ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6852ad6b513STimur Tabi 68698883332STimur Tabi #define CONFIG_NETDEV eth0 6872ad6b513STimur Tabi 6887a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 6892ad6b513STimur Tabi #define CONFIG_HOSTNAME mpc8349emitx 6907a78f148STimur Tabi #else 6917a78f148STimur Tabi #define CONFIG_HOSTNAME mpc8349emitxgp 6927a78f148STimur Tabi #endif 6937a78f148STimur Tabi 6947a78f148STimur Tabi /* Default path and filenames */ 695bf0b542dSKim Phillips #define CONFIG_ROOTPATH /nfsroot/rootfs 696bf0b542dSKim Phillips #define CONFIG_BOOTFILE uImage 6977a78f148STimur Tabi #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 6982ad6b513STimur Tabi 6997a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 7007a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitx.dtb 7012ad6b513STimur Tabi #else 7027a78f148STimur Tabi #define CONFIG_FDTFILE mpc8349emitxgp.dtb 7032ad6b513STimur Tabi #endif 7042ad6b513STimur Tabi 70505f91a65SKim Phillips #define CONFIG_BOOTDELAY 6 7067a78f148STimur Tabi 7072ad6b513STimur Tabi #define XMK_STR(x) #x 7082ad6b513STimur Tabi #define MK_STR(x) XMK_STR(x) 7092ad6b513STimur Tabi 71098883332STimur Tabi #define CONFIG_BOOTARGS \ 71198883332STimur Tabi "root=/dev/nfs rw" \ 71298883332STimur Tabi " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 71398883332STimur Tabi " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 71498883332STimur Tabi MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 71598883332STimur Tabi MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 7168a364f09SNikita V. Youshchenko " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 71798883332STimur Tabi 7182ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 7198a364f09SNikita V. Youshchenko "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 72098883332STimur Tabi "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 7217a78f148STimur Tabi "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 7227a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 72314d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 72414d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 72514d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 72614d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 72714d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 72805f91a65SKim Phillips "fdtaddr=780000\0" \ 7297a78f148STimur Tabi "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 730bf0b542dSKim Phillips 731bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 7327a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 733bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 7347a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 735bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 736bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 737bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 738bf0b542dSKim Phillips 739bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 740bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 7417a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 742bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 743bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 744bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 745bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 7462ad6b513STimur Tabi 7472ad6b513STimur Tabi #undef MK_STR 7482ad6b513STimur Tabi #undef XMK_STR 7492ad6b513STimur Tabi 7502ad6b513STimur Tabi #endif 751