12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 52ad6b513STimur Tabi */ 62ad6b513STimur Tabi 72ad6b513STimur Tabi /* 87a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 92ad6b513STimur Tabi 102ad6b513STimur Tabi Memory map: 112ad6b513STimur Tabi 122ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 132ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 142ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 152ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 162ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 172ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 187a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 192ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 207a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 217a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 227a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 232ad6b513STimur Tabi 242ad6b513STimur Tabi I2C address list: 252ad6b513STimur Tabi Align. Board 262ad6b513STimur Tabi Bus Addr Part No. Description Length Location 272ad6b513STimur Tabi ---------------------------------------------------------------- 28be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 292ad6b513STimur Tabi 30be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 31be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 32be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 33be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 34be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 35be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 362ad6b513STimur Tabi 372ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 382ad6b513STimur Tabi */ 392ad6b513STimur Tabi 402ad6b513STimur Tabi #ifndef __CONFIG_H 412ad6b513STimur Tabi #define __CONFIG_H 422ad6b513STimur Tabi 4314d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 457a78f148STimur Tabi #endif 462ad6b513STimur Tabi 472ad6b513STimur Tabi /* 482ad6b513STimur Tabi * High Level Configuration Options 492ad6b513STimur Tabi */ 501a2e203bSKim Phillips #define CONFIG_MPC83xx 1 512c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 522ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 532ad6b513STimur Tabi 542ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 552ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFEF00000 562ae18241SWolfgang Denk #endif 572ae18241SWolfgang Denk 586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 592ad6b513STimur Tabi 6089c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 6189c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 627a78f148STimur Tabi 6389c7784eSTimur Tabi /* 6489c7784eSTimur Tabi * On-board devices 6589c7784eSTimur Tabi */ 667a78f148STimur Tabi 677a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 68396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 69396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 7089c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 71c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 72c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 737a78f148STimur Tabi #endif 747a78f148STimur Tabi 757a78f148STimur Tabi #define CONFIG_PCI 762ad6b513STimur Tabi #define CONFIG_RTC_DS1337 777a78f148STimur Tabi #define CONFIG_HARD_I2C 787a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 797a78f148STimur Tabi 807a78f148STimur Tabi /* 817a78f148STimur Tabi * Device configurations 827a78f148STimur Tabi */ 832ad6b513STimur Tabi 842ad6b513STimur Tabi /* I2C */ 852ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 862ad6b513STimur Tabi 87be5e6181STimur Tabi #define CONFIG_FSL_I2C 882ad6b513STimur Tabi #define CONFIG_I2C_MULTI_BUS 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 92b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 932ad6b513STimur Tabi 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 100be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1012ad6b513STimur Tabi 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 1042ad6b513STimur Tabi 1052ad6b513STimur Tabi /* Don't probe these addresses: */ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1102ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 111396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 112396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1132ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1142ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1152ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1162ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1172ad6b513STimur Tabi 1182ad6b513STimur Tabi #undef CONFIG_SOFT_I2C 1192ad6b513STimur Tabi 1202ad6b513STimur Tabi #endif 1212ad6b513STimur Tabi 1227a78f148STimur Tabi /* Compact Flash */ 1232ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1242ad6b513STimur Tabi 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1272ad6b513STimur Tabi 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1342ad6b513STimur Tabi 135396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 136396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1372ad6b513STimur Tabi 138c9e34fe2SValeriy Glushkov #endif 139c9e34fe2SValeriy Glushkov 140c9e34fe2SValeriy Glushkov /* 141c9e34fe2SValeriy Glushkov * SATA 142c9e34fe2SValeriy Glushkov */ 143c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 144c9e34fe2SValeriy Glushkov 145c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 146c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 147c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1482ad6b513STimur Tabi 1497a78f148STimur Tabi #endif 1502ad6b513STimur Tabi 151c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 152c31e1326SValeriy Glushkov /* 153c31e1326SValeriy Glushkov * Support USB 154c31e1326SValeriy Glushkov */ 155c31e1326SValeriy Glushkov #define CONFIG_CMD_USB 156c31e1326SValeriy Glushkov #define CONFIG_USB_STORAGE 157c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 158c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 159c31e1326SValeriy Glushkov 160c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 161c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 162c31e1326SValeriy Glushkov #if 1 163c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 164c31e1326SValeriy Glushkov #else 165c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 166c31e1326SValeriy Glushkov #endif 167c31e1326SValeriy Glushkov 168c31e1326SValeriy Glushkov #endif 169c31e1326SValeriy Glushkov 1707a78f148STimur Tabi /* 1717a78f148STimur Tabi * DDR Setup 1727a78f148STimur Tabi */ 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1797a78f148STimur Tabi 180396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 181396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 182f64702b7STimur Tabi 183b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 184b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 185b7be63abSValeriy Glushkov 1867a78f148STimur Tabi #ifdef CONFIG_HARD_I2C 1877a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1887a78f148STimur Tabi #endif 1897a78f148STimur Tabi 190396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 191396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 1932e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 194396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 195396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 1967a78f148STimur Tabi 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1997a78f148STimur Tabi #endif 2007a78f148STimur Tabi 2017a78f148STimur Tabi /* 2027a78f148STimur Tabi *Flash on the Local Bus 2037a78f148STimur Tabi */ 2047a78f148STimur Tabi 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20600b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 209396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 210396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2147a78f148STimur Tabi 2157a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2167a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 219396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 220396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2237a78f148STimur Tabi 22489c7784eSTimur Tabi /* Vitesse 7385 */ 22589c7784eSTimur Tabi 22689c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 22789c7784eSTimur Tabi 22889c7784eSTimur Tabi #define CONFIG_TSEC2 22989c7784eSTimur Tabi 23089c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 23189c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 23289c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 23389c7784eSTimur Tabi 23489c7784eSTimur Tabi #endif 23589c7784eSTimur Tabi 2367a78f148STimur Tabi /* 2377a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2387a78f148STimur Tabi */ 2397a78f148STimur Tabi 2407a78f148STimur Tabi /* Flash */ 2417a78f148STimur Tabi 2427d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2437d6a0982SJoe Hershberger | BR_PS_16 \ 2447d6a0982SJoe Hershberger | BR_MS_GPCM \ 2457d6a0982SJoe Hershberger | BR_V) 2467d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 247396abba2SJoe Hershberger | OR_UPM_XAM \ 248396abba2SJoe Hershberger | OR_GPCM_CSNT \ 249396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 250396abba2SJoe Hershberger | OR_GPCM_XACS \ 251396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2527d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2537d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 254396abba2SJoe Hershberger | OR_GPCM_EAD) 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2567d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2577a78f148STimur Tabi 2587a78f148STimur Tabi /* Vitesse 7385 */ 2597a78f148STimur Tabi 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2617a78f148STimur Tabi 26289c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 26389c7784eSTimur Tabi 2647d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2657d6a0982SJoe Hershberger | BR_PS_8 \ 2667d6a0982SJoe Hershberger | BR_MS_GPCM \ 2677d6a0982SJoe Hershberger | BR_V) 268396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 269396abba2SJoe Hershberger | OR_GPCM_CSNT \ 270396abba2SJoe Hershberger | OR_GPCM_XACS \ 271396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 272396abba2SJoe Hershberger | OR_GPCM_SETA \ 2737d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2747d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 275396abba2SJoe Hershberger | OR_GPCM_EAD) 2767a78f148STimur Tabi 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2797a78f148STimur Tabi 2807a78f148STimur Tabi #endif 2817a78f148STimur Tabi 2827a78f148STimur Tabi /* LED */ 2837a78f148STimur Tabi 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2857d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 2867d6a0982SJoe Hershberger | BR_PS_8 \ 2877d6a0982SJoe Hershberger | BR_MS_GPCM \ 2887d6a0982SJoe Hershberger | BR_V) 289396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 290396abba2SJoe Hershberger | OR_GPCM_CSNT \ 291396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 292396abba2SJoe Hershberger | OR_GPCM_XACS \ 293396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 2947d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2957d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 296396abba2SJoe Hershberger | OR_GPCM_EAD) 2977a78f148STimur Tabi 2987a78f148STimur Tabi /* Compact Flash */ 2997a78f148STimur Tabi 3007a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 3017a78f148STimur Tabi 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 3037a78f148STimur Tabi 304396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 305396abba2SJoe Hershberger | BR_PS_16 \ 306396abba2SJoe Hershberger | BR_MS_UPMA \ 307396abba2SJoe Hershberger | BR_V) 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 3097a78f148STimur Tabi 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 3127a78f148STimur Tabi 3137a78f148STimur Tabi #endif 3147a78f148STimur Tabi 3157a78f148STimur Tabi /* 3167a78f148STimur Tabi * U-Boot memory configuration 3177a78f148STimur Tabi */ 31814d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3192ad6b513STimur Tabi 3206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3222ad6b513STimur Tabi #else 3236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3242ad6b513STimur Tabi #endif 3252ad6b513STimur Tabi 3266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 327396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 328553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3292ad6b513STimur Tabi 330396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 331396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3332ad6b513STimur Tabi 3346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 3354a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 336c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3372ad6b513STimur Tabi 3382ad6b513STimur Tabi /* 3392ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3402ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3412ad6b513STimur Tabi * External Local Bus rate is 3422ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3432ad6b513STimur Tabi */ 344c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 345c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3472ad6b513STimur Tabi 348396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 349396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 350396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 351396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3522ad6b513STimur Tabi 3532ad6b513STimur Tabi /* 3542ad6b513STimur Tabi * Serial Port 3552ad6b513STimur Tabi */ 3562ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3612ad6b513STimur Tabi 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3632ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3642ad6b513STimur Tabi 3658a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3667a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3677a78f148STimur Tabi 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3702ad6b513STimur Tabi 371bf0b542dSKim Phillips /* pass open firmware flat tree */ 37235cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 3735b8bc606SKim Phillips #define CONFIG_OF_BOARD_SETUP 1 3745b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3752ad6b513STimur Tabi 3767a78f148STimur Tabi /* 3777a78f148STimur Tabi * PCI 3787a78f148STimur Tabi */ 3792ad6b513STimur Tabi #ifdef CONFIG_PCI 380842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3812ad6b513STimur Tabi 3822ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3832ad6b513STimur Tabi 3842ad6b513STimur Tabi /* 3852ad6b513STimur Tabi * General PCI 3862ad6b513STimur Tabi * Addresses are mapped 1-1. 3872ad6b513STimur Tabi */ 3886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 391396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 392396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3982ad6b513STimur Tabi 3992ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 400396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 401396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 404396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 405396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 4066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 409396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 410396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 4122ad6b513STimur Tabi #endif 4132ad6b513STimur Tabi 4142ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4152ad6b513STimur Tabi 4162ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 4172ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 4192ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 4202ad6b513STimur Tabi #endif 4212ad6b513STimur Tabi 4222ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 4232ad6b513STimur Tabi 4242ad6b513STimur Tabi #endif 4252ad6b513STimur Tabi 4262ae18241SWolfgang Denk #define CONFIG_PCI_66M 4272ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4287a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4297a78f148STimur Tabi #else 4307a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4317a78f148STimur Tabi #endif 4327a78f148STimur Tabi 4332ad6b513STimur Tabi /* TSEC */ 4342ad6b513STimur Tabi 4352ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4362ad6b513STimur Tabi 4372ad6b513STimur Tabi #define CONFIG_MII 438659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4392ad6b513STimur Tabi 440255a3577SKim Phillips #define CONFIG_TSEC1 4412ad6b513STimur Tabi 442255a3577SKim Phillips #ifdef CONFIG_TSEC1 44310327dc5SAndy Fleming #define CONFIG_HAS_ETH0 444255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4462ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4472ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4483a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4492ad6b513STimur Tabi #endif 4502ad6b513STimur Tabi 451255a3577SKim Phillips #ifdef CONFIG_TSEC2 4527a78f148STimur Tabi #define CONFIG_HAS_ETH1 453255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 45589c7784eSTimur Tabi 4562ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4572ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4583a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4592ad6b513STimur Tabi #endif 4602ad6b513STimur Tabi 4612ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4622ad6b513STimur Tabi 4632ad6b513STimur Tabi #endif 4642ad6b513STimur Tabi 4652ad6b513STimur Tabi /* 4662ad6b513STimur Tabi * Environment 4672ad6b513STimur Tabi */ 4687a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4697a78f148STimur Tabi 4706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4715a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 472396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 473396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4740e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4750e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4762ad6b513STimur Tabi #else 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 47800b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 47993f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4810e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4822ad6b513STimur Tabi #endif 4832ad6b513STimur Tabi 4842ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4862ad6b513STimur Tabi 4878ea5499aSJon Loeliger /* 488659e2f67SJon Loeliger * BOOTP options 489659e2f67SJon Loeliger */ 490659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 491659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 492659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 493659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 494659e2f67SJon Loeliger 495659e2f67SJon Loeliger 496659e2f67SJon Loeliger /* 4978ea5499aSJon Loeliger * Command line configuration. 4988ea5499aSJon Loeliger */ 4998ea5499aSJon Loeliger #include <config_cmd_default.h> 5008ea5499aSJon Loeliger 5018ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 5028ea5499aSJon Loeliger #define CONFIG_CMD_DATE 5038ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 5048ea5499aSJon Loeliger #define CONFIG_CMD_NET 5058ea5499aSJon Loeliger #define CONFIG_CMD_PING 506b7be63abSValeriy Glushkov #define CONFIG_CMD_DHCP 5078ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 5082ad6b513STimur Tabi 509c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 510c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 511c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 512c9e34fe2SValeriy Glushkov #define CONFIG_CMD_FAT 513c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 514c9e34fe2SValeriy Glushkov #endif 515c9e34fe2SValeriy Glushkov 5162ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 5178ea5499aSJon Loeliger #define CONFIG_CMD_IDE 518c9e34fe2SValeriy Glushkov #endif 519c9e34fe2SValeriy Glushkov 520c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 521c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 522c31e1326SValeriy Glushkov #endif 523c31e1326SValeriy Glushkov 524c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 525c9e34fe2SValeriy Glushkov #define CONFIG_CMD_EXT2 5262ad6b513STimur Tabi #endif 5272ad6b513STimur Tabi 5282ad6b513STimur Tabi #ifdef CONFIG_PCI 5298ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5302ad6b513STimur Tabi #endif 5312ad6b513STimur Tabi 5322ad6b513STimur Tabi #ifdef CONFIG_HARD_I2C 5338ea5499aSJon Loeliger #define CONFIG_CMD_I2C 5342ad6b513STimur Tabi #endif 5352ad6b513STimur Tabi 5362ad6b513STimur Tabi /* Watchdog */ 5372ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5382ad6b513STimur Tabi 5392ad6b513STimur Tabi /* 5402ad6b513STimur Tabi * Miscellaneous configurable options 5412ad6b513STimur Tabi */ 5426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5437a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 544a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 5467a78f148STimur Tabi 5476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 54805f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5497a78f148STimur Tabi 5507a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 5516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5527a78f148STimur Tabi #else 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 5547a78f148STimur Tabi #endif 5552ad6b513STimur Tabi 5568ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5582ad6b513STimur Tabi #else 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5602ad6b513STimur Tabi #endif 5612ad6b513STimur Tabi 562396abba2SJoe Hershberger /* Print Buffer Size */ 563396abba2SJoe Hershberger #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 565396abba2SJoe Hershberger /* Boot Argument Buffer Size */ 566396abba2SJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 5682ad6b513STimur Tabi 5692ad6b513STimur Tabi /* 5702ad6b513STimur Tabi * For booting Linux, the board info and command line data 5719f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 5722ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5732ad6b513STimur Tabi */ 574396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 575396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 5762ad6b513STimur Tabi 5776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5782ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5792ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5802ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5812ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5822ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5832ad6b513STimur Tabi 5846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5862ad6b513STimur Tabi HRCWH_PCI_HOST |\ 5877a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 5882ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 5897a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5902ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5912ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 5922ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5932ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5942ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5952ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5962ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5972ad6b513STimur Tabi #else 5986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 5992ad6b513STimur Tabi HRCWH_PCI_HOST |\ 6002ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 6012ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 6027a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 6032ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 6042ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 6052ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 6062ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 6072ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 6082ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 6092ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 6102ad6b513STimur Tabi #endif 6112ad6b513STimur Tabi 6127a78f148STimur Tabi /* 6137a78f148STimur Tabi * System performance 6147a78f148STimur Tabi */ 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 6166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 621c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 622c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 6232ad6b513STimur Tabi 6247a78f148STimur Tabi /* 6257a78f148STimur Tabi * System IO Config 6267a78f148STimur Tabi */ 627396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 628396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 629396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 630396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 6312ad6b513STimur Tabi 6321a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 6331a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 6342ad6b513STimur Tabi 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 63631d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6372ad6b513STimur Tabi 6387a78f148STimur Tabi /* DDR */ 639396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 64072cd4087SJoe Hershberger | BATL_PP_RW \ 641396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 642396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 643396abba2SJoe Hershberger | BATU_BL_256M \ 644396abba2SJoe Hershberger | BATU_VS \ 645396abba2SJoe Hershberger | BATU_VP) 6462ad6b513STimur Tabi 6477a78f148STimur Tabi /* PCI */ 6482ad6b513STimur Tabi #ifdef CONFIG_PCI 649396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 65072cd4087SJoe Hershberger | BATL_PP_RW \ 651396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 652396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 653396abba2SJoe Hershberger | BATU_BL_256M \ 654396abba2SJoe Hershberger | BATU_VS \ 655396abba2SJoe Hershberger | BATU_VP) 656396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 65772cd4087SJoe Hershberger | BATL_PP_RW \ 658396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 659396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 660396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 661396abba2SJoe Hershberger | BATU_BL_256M \ 662396abba2SJoe Hershberger | BATU_VS \ 663396abba2SJoe Hershberger | BATU_VP) 6642ad6b513STimur Tabi #else 6656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6692ad6b513STimur Tabi #endif 6702ad6b513STimur Tabi 6712ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 672396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 67372cd4087SJoe Hershberger | BATL_PP_RW \ 674396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 675396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 676396abba2SJoe Hershberger | BATU_BL_256M \ 677396abba2SJoe Hershberger | BATU_VS \ 678396abba2SJoe Hershberger | BATU_VP) 679396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 68072cd4087SJoe Hershberger | BATL_PP_RW \ 681396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 682396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 683396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 684396abba2SJoe Hershberger | BATU_BL_256M \ 685396abba2SJoe Hershberger | BATU_VS \ 686396abba2SJoe Hershberger | BATU_VP) 6872ad6b513STimur Tabi #else 6886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 6896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 6906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 6916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 6922ad6b513STimur Tabi #endif 6932ad6b513STimur Tabi 6942ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 695396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 69672cd4087SJoe Hershberger | BATL_PP_RW \ 697396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 698396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 699396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 700396abba2SJoe Hershberger | BATU_BL_256M \ 701396abba2SJoe Hershberger | BATU_VS \ 702396abba2SJoe Hershberger | BATU_VP) 7032ad6b513STimur Tabi 7042ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 705396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 70672cd4087SJoe Hershberger | BATL_PP_RW \ 707396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 708396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 709396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 710396abba2SJoe Hershberger | BATU_BL_256M \ 711396abba2SJoe Hershberger | BATU_VS \ 712396abba2SJoe Hershberger | BATU_VP) 7132ad6b513STimur Tabi 7146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 7156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 7162ad6b513STimur Tabi 7176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 7186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 7196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 7206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 7216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 7226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 7236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 7246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 7256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 7266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 7276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 7286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 7296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 7306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 7316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 7326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 7332ad6b513STimur Tabi 7348ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 7352ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 7362ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 7372ad6b513STimur Tabi #endif 7382ad6b513STimur Tabi 7392ad6b513STimur Tabi 7402ad6b513STimur Tabi /* 7412ad6b513STimur Tabi * Environment Configuration 7422ad6b513STimur Tabi */ 7432ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 7442ad6b513STimur Tabi 745396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 7462ad6b513STimur Tabi 7477a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 748396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitx" 7497a78f148STimur Tabi #else 750396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitxgp" 7517a78f148STimur Tabi #endif 7527a78f148STimur Tabi 7537a78f148STimur Tabi /* Default path and filenames */ 7548b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 755b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 756396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 757396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 7582ad6b513STimur Tabi 7597a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 760396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 7612ad6b513STimur Tabi #else 762396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 7632ad6b513STimur Tabi #endif 7642ad6b513STimur Tabi 76505f91a65SKim Phillips #define CONFIG_BOOTDELAY 6 7667a78f148STimur Tabi 76798883332STimur Tabi #define CONFIG_BOOTARGS \ 76898883332STimur Tabi "root=/dev/nfs rw" \ 7695368c55dSMarek Vasut " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 7705368c55dSMarek Vasut " ip=" __stringify(CONFIG_IPADDR) ":" \ 7715368c55dSMarek Vasut __stringify(CONFIG_SERVERIP) ":" \ 7725368c55dSMarek Vasut __stringify(CONFIG_GATEWAYIP) ":" \ 7735368c55dSMarek Vasut __stringify(CONFIG_NETMASK) ":" \ 774396abba2SJoe Hershberger CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 7755368c55dSMarek Vasut " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 77698883332STimur Tabi 7772ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 7785368c55dSMarek Vasut "console=" __stringify(CONFIG_CONSOLE) "\0" \ 779396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 780396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 7817a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 7825368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7835368c55dSMarek Vasut " +$filesize; " \ 7845368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7855368c55dSMarek Vasut " +$filesize; " \ 7865368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7875368c55dSMarek Vasut " $filesize; " \ 7885368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7895368c55dSMarek Vasut " +$filesize; " \ 7905368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7915368c55dSMarek Vasut " $filesize\0" \ 79205f91a65SKim Phillips "fdtaddr=780000\0" \ 793396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 794bf0b542dSKim Phillips 795bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 7967a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 797bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 7987a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 799bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 800bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 801bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 802bf0b542dSKim Phillips 803bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 804bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 8057a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 806bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 807bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 808bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 809bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 8102ad6b513STimur Tabi 8112ad6b513STimur Tabi #endif 812