12ad6b513STimur Tabi /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 32ad6b513STimur Tabi * 42ad6b513STimur Tabi * See file CREDITS for list of people who contributed to this 52ad6b513STimur Tabi * project. 62ad6b513STimur Tabi * 72ad6b513STimur Tabi * This program is free software; you can redistribute it and/or 82ad6b513STimur Tabi * modify it under the terms of the GNU General Public License as 92ad6b513STimur Tabi * published by the Free Software Foundation; either version 2 of 102ad6b513STimur Tabi * the License, or (at your option) any later version. 112ad6b513STimur Tabi * 122ad6b513STimur Tabi * This program is distributed in the hope that it will be useful, 132ad6b513STimur Tabi * but WITHOUT ANY WARRANTY; without even the implied warranty of 142ad6b513STimur Tabi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152ad6b513STimur Tabi * GNU General Public License for more details. 162ad6b513STimur Tabi * 172ad6b513STimur Tabi * You should have received a copy of the GNU General Public License 182ad6b513STimur Tabi * along with this program; if not, write to the Free Software 192ad6b513STimur Tabi * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 202ad6b513STimur Tabi * MA 02111-1307 USA 212ad6b513STimur Tabi */ 222ad6b513STimur Tabi 232ad6b513STimur Tabi /* 247a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 252ad6b513STimur Tabi 262ad6b513STimur Tabi Memory map: 272ad6b513STimur Tabi 282ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 292ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 302ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 312ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 322ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 332ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 347a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 352ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 367a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 377a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 387a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 392ad6b513STimur Tabi 402ad6b513STimur Tabi I2C address list: 412ad6b513STimur Tabi Align. Board 422ad6b513STimur Tabi Bus Addr Part No. Description Length Location 432ad6b513STimur Tabi ---------------------------------------------------------------- 44be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 452ad6b513STimur Tabi 46be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 47be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 48be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 49be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 50be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 51be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 522ad6b513STimur Tabi 532ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 542ad6b513STimur Tabi */ 552ad6b513STimur Tabi 562ad6b513STimur Tabi #ifndef __CONFIG_H 572ad6b513STimur Tabi #define __CONFIG_H 582ad6b513STimur Tabi 5914d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 617a78f148STimur Tabi #endif 622ad6b513STimur Tabi 632ad6b513STimur Tabi /* 642ad6b513STimur Tabi * High Level Configuration Options 652ad6b513STimur Tabi */ 661a2e203bSKim Phillips #define CONFIG_MPC83xx 1 672c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 682ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 692ad6b513STimur Tabi 702ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 712ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFEF00000 722ae18241SWolfgang Denk #endif 732ae18241SWolfgang Denk 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 752ad6b513STimur Tabi 7689c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 7789c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 787a78f148STimur Tabi 7989c7784eSTimur Tabi /* 8089c7784eSTimur Tabi * On-board devices 8189c7784eSTimur Tabi */ 827a78f148STimur Tabi 837a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 84396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 85396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 8689c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 87c9e34fe2SValeriy Glushkov #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 88c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 897a78f148STimur Tabi #endif 907a78f148STimur Tabi 917a78f148STimur Tabi #define CONFIG_PCI 922ad6b513STimur Tabi #define CONFIG_RTC_DS1337 93*00f792e0SHeiko Schocher #define CONFIG_SYS_I2C 947a78f148STimur Tabi #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 957a78f148STimur Tabi 967a78f148STimur Tabi /* 977a78f148STimur Tabi * Device configurations 987a78f148STimur Tabi */ 992ad6b513STimur Tabi 1002ad6b513STimur Tabi /* I2C */ 101*00f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 102*00f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 103*00f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 104*00f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 105*00f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 106*00f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 107*00f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 108*00f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 1092ad6b513STimur Tabi 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 111b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 1122ad6b513STimur Tabi 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 119be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 1202ad6b513STimur Tabi 1212ad6b513STimur Tabi /* Don't probe these addresses: */ 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1262ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 127396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 128396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1292ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1302ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1312ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1322ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1332ad6b513STimur Tabi 1342ad6b513STimur Tabi #endif 1352ad6b513STimur Tabi 1367a78f148STimur Tabi /* Compact Flash */ 1372ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1382ad6b513STimur Tabi 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1412ad6b513STimur Tabi 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1482ad6b513STimur Tabi 149396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 150396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1512ad6b513STimur Tabi 152c9e34fe2SValeriy Glushkov #endif 153c9e34fe2SValeriy Glushkov 154c9e34fe2SValeriy Glushkov /* 155c9e34fe2SValeriy Glushkov * SATA 156c9e34fe2SValeriy Glushkov */ 157c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 158c9e34fe2SValeriy Glushkov 159c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 160c9e34fe2SValeriy Glushkov #define CONFIG_LIBATA 161c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1622ad6b513STimur Tabi 1637a78f148STimur Tabi #endif 1642ad6b513STimur Tabi 165c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 166c31e1326SValeriy Glushkov /* 167c31e1326SValeriy Glushkov * Support USB 168c31e1326SValeriy Glushkov */ 169c31e1326SValeriy Glushkov #define CONFIG_CMD_USB 170c31e1326SValeriy Glushkov #define CONFIG_USB_STORAGE 171c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI 172c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 173c31e1326SValeriy Glushkov 174c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 175c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 176c31e1326SValeriy Glushkov #if 1 177c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 178c31e1326SValeriy Glushkov #else 179c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 180c31e1326SValeriy Glushkov #endif 181c31e1326SValeriy Glushkov 182c31e1326SValeriy Glushkov #endif 183c31e1326SValeriy Glushkov 1847a78f148STimur Tabi /* 1857a78f148STimur Tabi * DDR Setup 1867a78f148STimur Tabi */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1937a78f148STimur Tabi 194396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 195396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 196f64702b7STimur Tabi 197b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 198b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 199b7be63abSValeriy Glushkov 200*00f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 2017a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 2027a78f148STimur Tabi #endif 2037a78f148STimur Tabi 204396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 205396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 2072e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 208396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 209396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 2107a78f148STimur Tabi 2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 2137a78f148STimur Tabi #endif 2147a78f148STimur Tabi 2157a78f148STimur Tabi /* 2167a78f148STimur Tabi *Flash on the Local Bus 2177a78f148STimur Tabi */ 2187a78f148STimur Tabi 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 22000b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 223396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 224396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2287a78f148STimur Tabi 2297a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 2307a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 233396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 234396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2377a78f148STimur Tabi 23889c7784eSTimur Tabi /* Vitesse 7385 */ 23989c7784eSTimur Tabi 24089c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 24189c7784eSTimur Tabi 24289c7784eSTimur Tabi #define CONFIG_TSEC2 24389c7784eSTimur Tabi 24489c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 24589c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 24689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 24789c7784eSTimur Tabi 24889c7784eSTimur Tabi #endif 24989c7784eSTimur Tabi 2507a78f148STimur Tabi /* 2517a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2527a78f148STimur Tabi */ 2537a78f148STimur Tabi 2547a78f148STimur Tabi /* Flash */ 2557a78f148STimur Tabi 2567d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2577d6a0982SJoe Hershberger | BR_PS_16 \ 2587d6a0982SJoe Hershberger | BR_MS_GPCM \ 2597d6a0982SJoe Hershberger | BR_V) 2607d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 261396abba2SJoe Hershberger | OR_UPM_XAM \ 262396abba2SJoe Hershberger | OR_GPCM_CSNT \ 263396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 264396abba2SJoe Hershberger | OR_GPCM_XACS \ 265396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2667d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2677d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 268396abba2SJoe Hershberger | OR_GPCM_EAD) 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2707d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2717a78f148STimur Tabi 2727a78f148STimur Tabi /* Vitesse 7385 */ 2737a78f148STimur Tabi 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2757a78f148STimur Tabi 27689c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 27789c7784eSTimur Tabi 2787d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2797d6a0982SJoe Hershberger | BR_PS_8 \ 2807d6a0982SJoe Hershberger | BR_MS_GPCM \ 2817d6a0982SJoe Hershberger | BR_V) 282396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 283396abba2SJoe Hershberger | OR_GPCM_CSNT \ 284396abba2SJoe Hershberger | OR_GPCM_XACS \ 285396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 286396abba2SJoe Hershberger | OR_GPCM_SETA \ 2877d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2887d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 289396abba2SJoe Hershberger | OR_GPCM_EAD) 2907a78f148STimur Tabi 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2937a78f148STimur Tabi 2947a78f148STimur Tabi #endif 2957a78f148STimur Tabi 2967a78f148STimur Tabi /* LED */ 2977a78f148STimur Tabi 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2997d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 3007d6a0982SJoe Hershberger | BR_PS_8 \ 3017d6a0982SJoe Hershberger | BR_MS_GPCM \ 3027d6a0982SJoe Hershberger | BR_V) 303396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 304396abba2SJoe Hershberger | OR_GPCM_CSNT \ 305396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 306396abba2SJoe Hershberger | OR_GPCM_XACS \ 307396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 3087d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3097d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 310396abba2SJoe Hershberger | OR_GPCM_EAD) 3117a78f148STimur Tabi 3127a78f148STimur Tabi /* Compact Flash */ 3137a78f148STimur Tabi 3147a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 3157a78f148STimur Tabi 3166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 3177a78f148STimur Tabi 318396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 319396abba2SJoe Hershberger | BR_PS_16 \ 320396abba2SJoe Hershberger | BR_MS_UPMA \ 321396abba2SJoe Hershberger | BR_V) 3226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 3237a78f148STimur Tabi 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 3267a78f148STimur Tabi 3277a78f148STimur Tabi #endif 3287a78f148STimur Tabi 3297a78f148STimur Tabi /* 3307a78f148STimur Tabi * U-Boot memory configuration 3317a78f148STimur Tabi */ 33214d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3332ad6b513STimur Tabi 3346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3362ad6b513STimur Tabi #else 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3382ad6b513STimur Tabi #endif 3392ad6b513STimur Tabi 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 341396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 342553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3432ad6b513STimur Tabi 344396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 345396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3472ad6b513STimur Tabi 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 3494a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 350c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3512ad6b513STimur Tabi 3522ad6b513STimur Tabi /* 3532ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3542ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3552ad6b513STimur Tabi * External Local Bus rate is 3562ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3572ad6b513STimur Tabi */ 358c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 359c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3612ad6b513STimur Tabi 362396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 363396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 364396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 365396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3662ad6b513STimur Tabi 3672ad6b513STimur Tabi /* 3682ad6b513STimur Tabi * Serial Port 3692ad6b513STimur Tabi */ 3702ad6b513STimur Tabi #define CONFIG_CONS_INDEX 1 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3752ad6b513STimur Tabi 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3772ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3782ad6b513STimur Tabi 3798a364f09SNikita V. Youshchenko #define CONFIG_CONSOLE ttyS0 3807a78f148STimur Tabi #define CONFIG_BAUDRATE 115200 3817a78f148STimur Tabi 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3842ad6b513STimur Tabi 385bf0b542dSKim Phillips /* pass open firmware flat tree */ 38635cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 3875b8bc606SKim Phillips #define CONFIG_OF_BOARD_SETUP 1 3885b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3892ad6b513STimur Tabi 3907a78f148STimur Tabi /* 3917a78f148STimur Tabi * PCI 3927a78f148STimur Tabi */ 3932ad6b513STimur Tabi #ifdef CONFIG_PCI 394842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3952ad6b513STimur Tabi 3962ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3972ad6b513STimur Tabi 3982ad6b513STimur Tabi /* 3992ad6b513STimur Tabi * General PCI 4002ad6b513STimur Tabi * Addresses are mapped 1-1. 4012ad6b513STimur Tabi */ 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 405396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 406396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 4122ad6b513STimur Tabi 4132ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 414396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 415396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 4176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 418396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 419396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 4226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 423396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 424396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 4262ad6b513STimur Tabi #endif 4272ad6b513STimur Tabi 4282ad6b513STimur Tabi #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4292ad6b513STimur Tabi 4302ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 4312ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 4326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 4332ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 4342ad6b513STimur Tabi #endif 4352ad6b513STimur Tabi 4362ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 4372ad6b513STimur Tabi 4382ad6b513STimur Tabi #endif 4392ad6b513STimur Tabi 4402ae18241SWolfgang Denk #define CONFIG_PCI_66M 4412ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 4427a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4437a78f148STimur Tabi #else 4447a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4457a78f148STimur Tabi #endif 4467a78f148STimur Tabi 4472ad6b513STimur Tabi /* TSEC */ 4482ad6b513STimur Tabi 4492ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 4502ad6b513STimur Tabi 4512ad6b513STimur Tabi #define CONFIG_MII 452659e2f67SJon Loeliger #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 4532ad6b513STimur Tabi 454255a3577SKim Phillips #define CONFIG_TSEC1 4552ad6b513STimur Tabi 456255a3577SKim Phillips #ifdef CONFIG_TSEC1 45710327dc5SAndy Fleming #define CONFIG_HAS_ETH0 458255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4602ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4612ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4623a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4632ad6b513STimur Tabi #endif 4642ad6b513STimur Tabi 465255a3577SKim Phillips #ifdef CONFIG_TSEC2 4667a78f148STimur Tabi #define CONFIG_HAS_ETH1 467255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 46989c7784eSTimur Tabi 4702ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4712ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4723a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4732ad6b513STimur Tabi #endif 4742ad6b513STimur Tabi 4752ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4762ad6b513STimur Tabi 4772ad6b513STimur Tabi #endif 4782ad6b513STimur Tabi 4792ad6b513STimur Tabi /* 4802ad6b513STimur Tabi * Environment 4812ad6b513STimur Tabi */ 4827a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4837a78f148STimur Tabi 4846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 4855a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 486396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 487396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4880e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4890e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4902ad6b513STimur Tabi #else 4916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 49200b1883aSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_FLASH_CFI_DRIVER 49393f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 4946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4950e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4962ad6b513STimur Tabi #endif 4972ad6b513STimur Tabi 4982ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 5002ad6b513STimur Tabi 5018ea5499aSJon Loeliger /* 502659e2f67SJon Loeliger * BOOTP options 503659e2f67SJon Loeliger */ 504659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 505659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTPATH 506659e2f67SJon Loeliger #define CONFIG_BOOTP_GATEWAY 507659e2f67SJon Loeliger #define CONFIG_BOOTP_HOSTNAME 508659e2f67SJon Loeliger 509659e2f67SJon Loeliger 510659e2f67SJon Loeliger /* 5118ea5499aSJon Loeliger * Command line configuration. 5128ea5499aSJon Loeliger */ 5138ea5499aSJon Loeliger #include <config_cmd_default.h> 5148ea5499aSJon Loeliger 5158ea5499aSJon Loeliger #define CONFIG_CMD_CACHE 5168ea5499aSJon Loeliger #define CONFIG_CMD_DATE 5178ea5499aSJon Loeliger #define CONFIG_CMD_IRQ 5188ea5499aSJon Loeliger #define CONFIG_CMD_NET 5198ea5499aSJon Loeliger #define CONFIG_CMD_PING 520b7be63abSValeriy Glushkov #define CONFIG_CMD_DHCP 5218ea5499aSJon Loeliger #define CONFIG_CMD_SDRAM 5222ad6b513STimur Tabi 523c31e1326SValeriy Glushkov #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 524c31e1326SValeriy Glushkov || defined(CONFIG_USB_STORAGE) 525c9e34fe2SValeriy Glushkov #define CONFIG_DOS_PARTITION 526c9e34fe2SValeriy Glushkov #define CONFIG_CMD_FAT 527c31e1326SValeriy Glushkov #define CONFIG_SUPPORT_VFAT 528c9e34fe2SValeriy Glushkov #endif 529c9e34fe2SValeriy Glushkov 5302ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 5318ea5499aSJon Loeliger #define CONFIG_CMD_IDE 532c9e34fe2SValeriy Glushkov #endif 533c9e34fe2SValeriy Glushkov 534c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 535c9e34fe2SValeriy Glushkov #define CONFIG_CMD_SATA 536c31e1326SValeriy Glushkov #endif 537c31e1326SValeriy Glushkov 538c31e1326SValeriy Glushkov #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 539c9e34fe2SValeriy Glushkov #define CONFIG_CMD_EXT2 5402ad6b513STimur Tabi #endif 5412ad6b513STimur Tabi 5422ad6b513STimur Tabi #ifdef CONFIG_PCI 5438ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5442ad6b513STimur Tabi #endif 5452ad6b513STimur Tabi 546*00f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 5478ea5499aSJon Loeliger #define CONFIG_CMD_I2C 5482ad6b513STimur Tabi #endif 5492ad6b513STimur Tabi 5502ad6b513STimur Tabi /* Watchdog */ 5512ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 5522ad6b513STimur Tabi 5532ad6b513STimur Tabi /* 5542ad6b513STimur Tabi * Miscellaneous configurable options 5552ad6b513STimur Tabi */ 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5577a78f148STimur Tabi #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 558a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 5607a78f148STimur Tabi 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 56205f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5637a78f148STimur Tabi 5647a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 5667a78f148STimur Tabi #else 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 5687a78f148STimur Tabi #endif 5692ad6b513STimur Tabi 5708ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 5722ad6b513STimur Tabi #else 5736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 5742ad6b513STimur Tabi #endif 5752ad6b513STimur Tabi 576396abba2SJoe Hershberger /* Print Buffer Size */ 577396abba2SJoe Hershberger #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 5786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 579396abba2SJoe Hershberger /* Boot Argument Buffer Size */ 580396abba2SJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 5822ad6b513STimur Tabi 5832ad6b513STimur Tabi /* 5842ad6b513STimur Tabi * For booting Linux, the board info and command line data 5859f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 5862ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 5872ad6b513STimur Tabi */ 588396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 589396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 5902ad6b513STimur Tabi 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 5922ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 5932ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 5942ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 5952ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 5962ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 5972ad6b513STimur Tabi 5986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 5996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 6002ad6b513STimur Tabi HRCWH_PCI_HOST |\ 6017a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 6022ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 6037a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 6042ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 6052ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 6062ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 6072ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 6082ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 6092ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 6102ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 6112ad6b513STimur Tabi #else 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 6132ad6b513STimur Tabi HRCWH_PCI_HOST |\ 6142ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 6152ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 6167a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 6172ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 6182ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 6192ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 6202ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 6212ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 6222ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 6232ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 6242ad6b513STimur Tabi #endif 6252ad6b513STimur Tabi 6267a78f148STimur Tabi /* 6277a78f148STimur Tabi * System performance 6287a78f148STimur Tabi */ 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 6316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 6326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 635c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 636c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 6372ad6b513STimur Tabi 6387a78f148STimur Tabi /* 6397a78f148STimur Tabi * System IO Config 6407a78f148STimur Tabi */ 641396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 642396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 643396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 644396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 6452ad6b513STimur Tabi 6461a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 6471a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 6482ad6b513STimur Tabi 6496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 65031d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 6512ad6b513STimur Tabi 6527a78f148STimur Tabi /* DDR */ 653396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 65472cd4087SJoe Hershberger | BATL_PP_RW \ 655396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 656396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 657396abba2SJoe Hershberger | BATU_BL_256M \ 658396abba2SJoe Hershberger | BATU_VS \ 659396abba2SJoe Hershberger | BATU_VP) 6602ad6b513STimur Tabi 6617a78f148STimur Tabi /* PCI */ 6622ad6b513STimur Tabi #ifdef CONFIG_PCI 663396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 66472cd4087SJoe Hershberger | BATL_PP_RW \ 665396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 666396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 667396abba2SJoe Hershberger | BATU_BL_256M \ 668396abba2SJoe Hershberger | BATU_VS \ 669396abba2SJoe Hershberger | BATU_VP) 670396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 67172cd4087SJoe Hershberger | BATL_PP_RW \ 672396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 673396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 674396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 675396abba2SJoe Hershberger | BATU_BL_256M \ 676396abba2SJoe Hershberger | BATU_VS \ 677396abba2SJoe Hershberger | BATU_VP) 6782ad6b513STimur Tabi #else 6796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 6806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 6816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 6826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 6832ad6b513STimur Tabi #endif 6842ad6b513STimur Tabi 6852ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 686396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 68772cd4087SJoe Hershberger | BATL_PP_RW \ 688396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 689396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 690396abba2SJoe Hershberger | BATU_BL_256M \ 691396abba2SJoe Hershberger | BATU_VS \ 692396abba2SJoe Hershberger | BATU_VP) 693396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 69472cd4087SJoe Hershberger | BATL_PP_RW \ 695396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 696396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 697396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 698396abba2SJoe Hershberger | BATU_BL_256M \ 699396abba2SJoe Hershberger | BATU_VS \ 700396abba2SJoe Hershberger | BATU_VP) 7012ad6b513STimur Tabi #else 7026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 7036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 7046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 7056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 7062ad6b513STimur Tabi #endif 7072ad6b513STimur Tabi 7082ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 709396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 71072cd4087SJoe Hershberger | BATL_PP_RW \ 711396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 712396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 713396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 714396abba2SJoe Hershberger | BATU_BL_256M \ 715396abba2SJoe Hershberger | BATU_VS \ 716396abba2SJoe Hershberger | BATU_VP) 7172ad6b513STimur Tabi 7182ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 719396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 72072cd4087SJoe Hershberger | BATL_PP_RW \ 721396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 722396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 723396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 724396abba2SJoe Hershberger | BATU_BL_256M \ 725396abba2SJoe Hershberger | BATU_VS \ 726396abba2SJoe Hershberger | BATU_VP) 7272ad6b513STimur Tabi 7286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 7296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 7302ad6b513STimur Tabi 7316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 7326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 7336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 7346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 7356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 7366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 7376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 7386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 7396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 7406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 7416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 7426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 7436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 7446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 7456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 7466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 7472ad6b513STimur Tabi 7488ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 7492ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 7502ad6b513STimur Tabi #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 7512ad6b513STimur Tabi #endif 7522ad6b513STimur Tabi 7532ad6b513STimur Tabi 7542ad6b513STimur Tabi /* 7552ad6b513STimur Tabi * Environment Configuration 7562ad6b513STimur Tabi */ 7572ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 7582ad6b513STimur Tabi 759396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 7602ad6b513STimur Tabi 7617a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 762396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitx" 7637a78f148STimur Tabi #else 764396abba2SJoe Hershberger #define CONFIG_HOSTNAME "mpc8349emitxgp" 7657a78f148STimur Tabi #endif 7667a78f148STimur Tabi 7677a78f148STimur Tabi /* Default path and filenames */ 7688b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 769b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 770396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 771396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 7722ad6b513STimur Tabi 7737a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 774396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 7752ad6b513STimur Tabi #else 776396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 7772ad6b513STimur Tabi #endif 7782ad6b513STimur Tabi 77905f91a65SKim Phillips #define CONFIG_BOOTDELAY 6 7807a78f148STimur Tabi 78198883332STimur Tabi #define CONFIG_BOOTARGS \ 78298883332STimur Tabi "root=/dev/nfs rw" \ 7835368c55dSMarek Vasut " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 7845368c55dSMarek Vasut " ip=" __stringify(CONFIG_IPADDR) ":" \ 7855368c55dSMarek Vasut __stringify(CONFIG_SERVERIP) ":" \ 7865368c55dSMarek Vasut __stringify(CONFIG_GATEWAYIP) ":" \ 7875368c55dSMarek Vasut __stringify(CONFIG_NETMASK) ":" \ 788396abba2SJoe Hershberger CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 7895368c55dSMarek Vasut " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 79098883332STimur Tabi 7912ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 7925368c55dSMarek Vasut "console=" __stringify(CONFIG_CONSOLE) "\0" \ 793396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 794396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 7957a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 7965368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7975368c55dSMarek Vasut " +$filesize; " \ 7985368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7995368c55dSMarek Vasut " +$filesize; " \ 8005368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 8015368c55dSMarek Vasut " $filesize; " \ 8025368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 8035368c55dSMarek Vasut " +$filesize; " \ 8045368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 8055368c55dSMarek Vasut " $filesize\0" \ 80605f91a65SKim Phillips "fdtaddr=780000\0" \ 807396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 808bf0b542dSKim Phillips 809bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 8107a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 811bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 8127a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 813bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 814bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 815bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 816bf0b542dSKim Phillips 817bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 818bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 8197a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 820bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 821bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 822bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 823bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 8242ad6b513STimur Tabi 8252ad6b513STimur Tabi #endif 826