1 /* 2 * (C) Copyright 2006-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * mpc8349emds board configuration file 10 * 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 /* E300 Family */ 20 #define CONFIG_MPC834x 1 /* MPC834x family */ 21 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 22 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 23 24 #define CONFIG_SYS_TEXT_BASE 0xFE000000 25 26 #define CONFIG_PCI_66M 27 #ifdef CONFIG_PCI_66M 28 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 29 #else 30 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 31 #endif 32 33 #ifdef CONFIG_PCISLAVE 34 #define CONFIG_PCI 35 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 36 #endif /* CONFIG_PCISLAVE */ 37 38 #ifndef CONFIG_SYS_CLK_FREQ 39 #ifdef CONFIG_PCI_66M 40 #define CONFIG_SYS_CLK_FREQ 66000000 41 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 42 #else 43 #define CONFIG_SYS_CLK_FREQ 33000000 44 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 45 #endif 46 #endif 47 48 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 49 50 #define CONFIG_SYS_IMMR 0xE0000000 51 52 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 53 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 54 #define CONFIG_SYS_MEMTEST_END 0x00100000 55 56 /* 57 * DDR Setup 58 */ 59 #define CONFIG_DDR_ECC /* support DDR ECC function */ 60 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 61 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 62 63 /* 64 * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver 65 * undefine it to use old spd_sdram.c 66 */ 67 #define CONFIG_SYS_FSL_DDR2 68 #ifdef CONFIG_SYS_FSL_DDR2 69 #define CONFIG_SYS_FSL_DDRC_GEN2 70 #define CONFIG_SYS_SPD_BUS_NUM 0 71 #define SPD_EEPROM_ADDRESS1 0x52 72 #define SPD_EEPROM_ADDRESS2 0x51 73 #define CONFIG_NUM_DDR_CONTROLLERS 1 74 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 75 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 76 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 77 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 78 #endif 79 80 /* 81 * 32-bit data path mode. 82 * 83 * Please note that using this mode for devices with the real density of 64-bit 84 * effectively reduces the amount of available memory due to the effect of 85 * wrapping around while translating address to row/columns, for example in the 86 * 256MB module the upper 128MB get aliased with contents of the lower 87 * 128MB); normally this define should be used for devices with real 32-bit 88 * data path. 89 */ 90 #undef CONFIG_DDR_32BIT 91 92 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 94 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 96 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 97 #undef CONFIG_DDR_2T_TIMING 98 99 /* 100 * DDRCDR - DDR Control Driver Register 101 */ 102 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 103 104 #if defined(CONFIG_SPD_EEPROM) 105 /* 106 * Determine DDR configuration from I2C interface. 107 */ 108 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 109 #else 110 /* 111 * Manually set up DDR parameters 112 */ 113 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 114 #if defined(CONFIG_DDR_II) 115 #define CONFIG_SYS_DDRCDR 0x80080001 116 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 117 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 118 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 119 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 120 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 122 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 123 #define CONFIG_SYS_DDR_MODE 0x47d00432 124 #define CONFIG_SYS_DDR_MODE2 0x8000c000 125 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 126 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 127 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 128 #else 129 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 130 | CSCONFIG_ROW_BIT_13 \ 131 | CSCONFIG_COL_BIT_10) 132 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 133 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 134 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 135 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 136 137 #if defined(CONFIG_DDR_32BIT) 138 /* set burst length to 8 for 32-bit data path */ 139 /* DLL,normal,seq,4/2.5, 8 burst len */ 140 #define CONFIG_SYS_DDR_MODE 0x00000023 141 #else 142 /* the default burst length is 4 - for 64-bit data path */ 143 /* DLL,normal,seq,4/2.5, 4 burst len */ 144 #define CONFIG_SYS_DDR_MODE 0x00000022 145 #endif 146 #endif 147 #endif 148 149 /* 150 * SDRAM on the Local Bus 151 */ 152 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 153 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 154 155 /* 156 * FLASH on the Local Bus 157 */ 158 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 159 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 160 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 161 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 162 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 163 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 164 165 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 166 | BR_PS_16 /* 16 bit port */ \ 167 | BR_MS_GPCM /* MSEL = GPCM */ \ 168 | BR_V) /* valid */ 169 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 170 | OR_UPM_XAM \ 171 | OR_GPCM_CSNT \ 172 | OR_GPCM_ACS_DIV2 \ 173 | OR_GPCM_XACS \ 174 | OR_GPCM_SCY_15 \ 175 | OR_GPCM_TRLX_SET \ 176 | OR_GPCM_EHTR_SET \ 177 | OR_GPCM_EAD) 178 179 /* window base at flash base */ 180 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 181 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 182 183 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 184 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 185 186 #undef CONFIG_SYS_FLASH_CHECKSUM 187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 189 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 191 192 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 193 #define CONFIG_SYS_RAMBOOT 194 #else 195 #undef CONFIG_SYS_RAMBOOT 196 #endif 197 198 /* 199 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 200 */ 201 #define CONFIG_SYS_BCSR 0xE2400000 202 /* Access window base at BCSR base */ 203 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 204 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 205 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 206 | BR_PS_8 \ 207 | BR_MS_GPCM \ 208 | BR_V) 209 /* 0x00000801 */ 210 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 211 | OR_GPCM_XAM \ 212 | OR_GPCM_CSNT \ 213 | OR_GPCM_SCY_15 \ 214 | OR_GPCM_TRLX_CLEAR \ 215 | OR_GPCM_EHTR_CLEAR) 216 /* 0xFFFFE8F0 */ 217 218 #define CONFIG_SYS_INIT_RAM_LOCK 1 219 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 220 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 221 222 #define CONFIG_SYS_GBL_DATA_OFFSET \ 223 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225 226 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 227 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 228 229 /* 230 * Local Bus LCRR and LBCR regs 231 * LCRR: DLL bypass, Clock divider is 4 232 * External Local Bus rate is 233 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 234 */ 235 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 236 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 237 #define CONFIG_SYS_LBC_LBCR 0x00000000 238 239 /* 240 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 241 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 242 */ 243 #undef CONFIG_SYS_LB_SDRAM 244 245 #ifdef CONFIG_SYS_LB_SDRAM 246 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 247 /* 248 * Base Register 2 and Option Register 2 configure SDRAM. 249 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 250 * 251 * For BR2, need: 252 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 253 * port-size = 32-bits = BR2[19:20] = 11 254 * no parity checking = BR2[21:22] = 00 255 * SDRAM for MSEL = BR2[24:26] = 011 256 * Valid = BR[31] = 1 257 * 258 * 0 4 8 12 16 20 24 28 259 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 260 */ 261 262 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 263 | BR_PS_32 /* 32-bit port */ \ 264 | BR_MS_SDRAM /* MSEL = SDRAM */ \ 265 | BR_V) /* Valid */ 266 /* 0xF0001861 */ 267 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 268 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 269 270 /* 271 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 272 * 273 * For OR2, need: 274 * 64MB mask for AM, OR2[0:7] = 1111 1100 275 * XAM, OR2[17:18] = 11 276 * 9 columns OR2[19-21] = 010 277 * 13 rows OR2[23-25] = 100 278 * EAD set for extra time OR[31] = 1 279 * 280 * 0 4 8 12 16 20 24 28 281 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 282 */ 283 284 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ 285 | OR_SDRAM_XAM \ 286 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 287 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 288 | OR_SDRAM_EAD) 289 /* 0xFC006901 */ 290 291 /* LB sdram refresh timer, about 6us */ 292 #define CONFIG_SYS_LBC_LSRT 0x32000000 293 /* LB refresh timer prescal, 266MHz/32 */ 294 #define CONFIG_SYS_LBC_MRTPR 0x20000000 295 296 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 297 | LSDMR_BSMA1516 \ 298 | LSDMR_RFCR8 \ 299 | LSDMR_PRETOACT6 \ 300 | LSDMR_ACTTORW3 \ 301 | LSDMR_BL8 \ 302 | LSDMR_WRC3 \ 303 | LSDMR_CL3) 304 305 /* 306 * SDRAM Controller configuration sequence. 307 */ 308 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 309 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 310 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 311 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 312 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 313 #endif 314 315 /* 316 * Serial Port 317 */ 318 #define CONFIG_CONS_INDEX 1 319 #define CONFIG_SYS_NS16550 320 #define CONFIG_SYS_NS16550_SERIAL 321 #define CONFIG_SYS_NS16550_REG_SIZE 1 322 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 323 324 #define CONFIG_SYS_BAUDRATE_TABLE \ 325 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 326 327 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 328 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 329 330 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 331 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 332 /* Use the HUSH parser */ 333 #define CONFIG_SYS_HUSH_PARSER 334 335 /* pass open firmware flat tree */ 336 #define CONFIG_OF_LIBFDT 1 337 #define CONFIG_OF_BOARD_SETUP 1 338 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 339 340 /* I2C */ 341 #define CONFIG_SYS_I2C 342 #define CONFIG_SYS_I2C_FSL 343 #define CONFIG_SYS_FSL_I2C_SPEED 400000 344 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 345 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 346 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 347 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 348 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 349 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 350 351 /* SPI */ 352 #define CONFIG_MPC8XXX_SPI 353 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 354 355 /* GPIOs. Used as SPI chip selects */ 356 #define CONFIG_SYS_GPIO1_PRELIM 357 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 358 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 359 360 /* TSEC */ 361 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 362 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 363 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 364 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 365 366 /* USB */ 367 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 368 369 /* 370 * General PCI 371 * Addresses are mapped 1-1. 372 */ 373 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 374 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 375 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 376 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 377 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 378 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 379 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 380 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 381 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 382 383 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 384 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 385 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 386 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 387 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 388 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 389 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 390 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 391 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 392 393 #if defined(CONFIG_PCI) 394 395 #define PCI_ONE_PCI1 396 #if defined(PCI_64BIT) 397 #undef PCI_ALL_PCI1 398 #undef PCI_TWO_PCI1 399 #undef PCI_ONE_PCI1 400 #endif 401 402 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 403 #define CONFIG_83XX_PCI_STREAMING 404 405 #undef CONFIG_EEPRO100 406 #undef CONFIG_TULIP 407 408 #if !defined(CONFIG_PCI_PNP) 409 #define PCI_ENET0_IOADDR 0xFIXME 410 #define PCI_ENET0_MEMADDR 0xFIXME 411 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 412 #endif 413 414 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 415 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 416 417 #endif /* CONFIG_PCI */ 418 419 /* 420 * TSEC configuration 421 */ 422 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 423 424 #if defined(CONFIG_TSEC_ENET) 425 426 #define CONFIG_GMII 1 /* MII PHY management */ 427 #define CONFIG_TSEC1 1 428 #define CONFIG_TSEC1_NAME "TSEC0" 429 #define CONFIG_TSEC2 1 430 #define CONFIG_TSEC2_NAME "TSEC1" 431 #define TSEC1_PHY_ADDR 0 432 #define TSEC2_PHY_ADDR 1 433 #define TSEC1_PHYIDX 0 434 #define TSEC2_PHYIDX 0 435 #define TSEC1_FLAGS TSEC_GIGABIT 436 #define TSEC2_FLAGS TSEC_GIGABIT 437 438 /* Options are: TSEC[0-1] */ 439 #define CONFIG_ETHPRIME "TSEC0" 440 441 #endif /* CONFIG_TSEC_ENET */ 442 443 /* 444 * Configure on-board RTC 445 */ 446 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 447 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 448 449 /* 450 * Environment 451 */ 452 #ifndef CONFIG_SYS_RAMBOOT 453 #define CONFIG_ENV_IS_IN_FLASH 1 454 #define CONFIG_ENV_ADDR \ 455 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 456 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 457 #define CONFIG_ENV_SIZE 0x2000 458 459 /* Address and size of Redundant Environment Sector */ 460 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 461 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 462 463 #else 464 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 465 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 466 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 467 #define CONFIG_ENV_SIZE 0x2000 468 #endif 469 470 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 471 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 472 473 474 /* 475 * BOOTP options 476 */ 477 #define CONFIG_BOOTP_BOOTFILESIZE 478 #define CONFIG_BOOTP_BOOTPATH 479 #define CONFIG_BOOTP_GATEWAY 480 #define CONFIG_BOOTP_HOSTNAME 481 482 483 /* 484 * Command line configuration. 485 */ 486 #include <config_cmd_default.h> 487 488 #define CONFIG_CMD_PING 489 #define CONFIG_CMD_I2C 490 #define CONFIG_CMD_DATE 491 #define CONFIG_CMD_MII 492 493 #if defined(CONFIG_PCI) 494 #define CONFIG_CMD_PCI 495 #endif 496 497 #if defined(CONFIG_SYS_RAMBOOT) 498 #undef CONFIG_CMD_SAVEENV 499 #undef CONFIG_CMD_LOADS 500 #endif 501 502 503 #undef CONFIG_WATCHDOG /* watchdog disabled */ 504 505 /* 506 * Miscellaneous configurable options 507 */ 508 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 509 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 510 511 #if defined(CONFIG_CMD_KGDB) 512 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 513 #else 514 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 515 #endif 516 517 /* Print Buffer Size */ 518 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 519 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 520 /* Boot Argument Buffer Size */ 521 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 522 523 /* 524 * For booting Linux, the board info and command line data 525 * have to be in the first 256 MB of memory, since this is 526 * the maximum mapped by the Linux kernel during initialization. 527 */ 528 /* Initial Memory map for Linux*/ 529 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 530 531 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 532 533 #if 1 /*528/264*/ 534 #define CONFIG_SYS_HRCW_LOW (\ 535 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 536 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 537 HRCWL_CSB_TO_CLKIN |\ 538 HRCWL_VCO_1X2 |\ 539 HRCWL_CORE_TO_CSB_2X1) 540 #elif 0 /*396/132*/ 541 #define CONFIG_SYS_HRCW_LOW (\ 542 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 543 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 544 HRCWL_CSB_TO_CLKIN |\ 545 HRCWL_VCO_1X4 |\ 546 HRCWL_CORE_TO_CSB_3X1) 547 #elif 0 /*264/132*/ 548 #define CONFIG_SYS_HRCW_LOW (\ 549 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 550 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 551 HRCWL_CSB_TO_CLKIN |\ 552 HRCWL_VCO_1X4 |\ 553 HRCWL_CORE_TO_CSB_2X1) 554 #elif 0 /*132/132*/ 555 #define CONFIG_SYS_HRCW_LOW (\ 556 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 557 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 558 HRCWL_CSB_TO_CLKIN |\ 559 HRCWL_VCO_1X4 |\ 560 HRCWL_CORE_TO_CSB_1X1) 561 #elif 0 /*264/264 */ 562 #define CONFIG_SYS_HRCW_LOW (\ 563 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 564 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 565 HRCWL_CSB_TO_CLKIN |\ 566 HRCWL_VCO_1X4 |\ 567 HRCWL_CORE_TO_CSB_1X1) 568 #endif 569 570 #ifdef CONFIG_PCISLAVE 571 #define CONFIG_SYS_HRCW_HIGH (\ 572 HRCWH_PCI_AGENT |\ 573 HRCWH_64_BIT_PCI |\ 574 HRCWH_PCI1_ARBITER_DISABLE |\ 575 HRCWH_PCI2_ARBITER_DISABLE |\ 576 HRCWH_CORE_ENABLE |\ 577 HRCWH_FROM_0X00000100 |\ 578 HRCWH_BOOTSEQ_DISABLE |\ 579 HRCWH_SW_WATCHDOG_DISABLE |\ 580 HRCWH_ROM_LOC_LOCAL_16BIT |\ 581 HRCWH_TSEC1M_IN_GMII |\ 582 HRCWH_TSEC2M_IN_GMII) 583 #else 584 #if defined(PCI_64BIT) 585 #define CONFIG_SYS_HRCW_HIGH (\ 586 HRCWH_PCI_HOST |\ 587 HRCWH_64_BIT_PCI |\ 588 HRCWH_PCI1_ARBITER_ENABLE |\ 589 HRCWH_PCI2_ARBITER_DISABLE |\ 590 HRCWH_CORE_ENABLE |\ 591 HRCWH_FROM_0X00000100 |\ 592 HRCWH_BOOTSEQ_DISABLE |\ 593 HRCWH_SW_WATCHDOG_DISABLE |\ 594 HRCWH_ROM_LOC_LOCAL_16BIT |\ 595 HRCWH_TSEC1M_IN_GMII |\ 596 HRCWH_TSEC2M_IN_GMII) 597 #else 598 #define CONFIG_SYS_HRCW_HIGH (\ 599 HRCWH_PCI_HOST |\ 600 HRCWH_32_BIT_PCI |\ 601 HRCWH_PCI1_ARBITER_ENABLE |\ 602 HRCWH_PCI2_ARBITER_ENABLE |\ 603 HRCWH_CORE_ENABLE |\ 604 HRCWH_FROM_0X00000100 |\ 605 HRCWH_BOOTSEQ_DISABLE |\ 606 HRCWH_SW_WATCHDOG_DISABLE |\ 607 HRCWH_ROM_LOC_LOCAL_16BIT |\ 608 HRCWH_TSEC1M_IN_GMII |\ 609 HRCWH_TSEC2M_IN_GMII) 610 #endif /* PCI_64BIT */ 611 #endif /* CONFIG_PCISLAVE */ 612 613 /* 614 * System performance 615 */ 616 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 617 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 618 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 619 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 620 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 621 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 622 623 /* System IO Config */ 624 #define CONFIG_SYS_SICRH 0 625 #define CONFIG_SYS_SICRL SICRL_LDP_A 626 627 #define CONFIG_SYS_HID0_INIT 0x000000000 628 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 629 | HID0_ENABLE_INSTRUCTION_CACHE) 630 631 /* #define CONFIG_SYS_HID0_FINAL (\ 632 HID0_ENABLE_INSTRUCTION_CACHE |\ 633 HID0_ENABLE_M_BIT |\ 634 HID0_ENABLE_ADDRESS_BROADCAST) */ 635 636 637 #define CONFIG_SYS_HID2 HID2_HBE 638 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 639 640 /* DDR @ 0x00000000 */ 641 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 642 | BATL_PP_RW \ 643 | BATL_MEMCOHERENCE) 644 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 645 | BATU_BL_256M \ 646 | BATU_VS \ 647 | BATU_VP) 648 649 /* PCI @ 0x80000000 */ 650 #ifdef CONFIG_PCI 651 #define CONFIG_PCI_INDIRECT_BRIDGE 652 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 653 | BATL_PP_RW \ 654 | BATL_MEMCOHERENCE) 655 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 656 | BATU_BL_256M \ 657 | BATU_VS \ 658 | BATU_VP) 659 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 660 | BATL_PP_RW \ 661 | BATL_CACHEINHIBIT \ 662 | BATL_GUARDEDSTORAGE) 663 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 664 | BATU_BL_256M \ 665 | BATU_VS \ 666 | BATU_VP) 667 #else 668 #define CONFIG_SYS_IBAT1L (0) 669 #define CONFIG_SYS_IBAT1U (0) 670 #define CONFIG_SYS_IBAT2L (0) 671 #define CONFIG_SYS_IBAT2U (0) 672 #endif 673 674 #ifdef CONFIG_MPC83XX_PCI2 675 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 676 | BATL_PP_RW \ 677 | BATL_MEMCOHERENCE) 678 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 679 | BATU_BL_256M \ 680 | BATU_VS \ 681 | BATU_VP) 682 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 683 | BATL_PP_RW \ 684 | BATL_CACHEINHIBIT \ 685 | BATL_GUARDEDSTORAGE) 686 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 687 | BATU_BL_256M \ 688 | BATU_VS \ 689 | BATU_VP) 690 #else 691 #define CONFIG_SYS_IBAT3L (0) 692 #define CONFIG_SYS_IBAT3U (0) 693 #define CONFIG_SYS_IBAT4L (0) 694 #define CONFIG_SYS_IBAT4U (0) 695 #endif 696 697 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 698 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 699 | BATL_PP_RW \ 700 | BATL_CACHEINHIBIT \ 701 | BATL_GUARDEDSTORAGE) 702 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 703 | BATU_BL_256M \ 704 | BATU_VS \ 705 | BATU_VP) 706 707 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 708 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 709 | BATL_PP_RW \ 710 | BATL_MEMCOHERENCE \ 711 | BATL_GUARDEDSTORAGE) 712 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 713 | BATU_BL_256M \ 714 | BATU_VS \ 715 | BATU_VP) 716 717 #define CONFIG_SYS_IBAT7L (0) 718 #define CONFIG_SYS_IBAT7U (0) 719 720 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 721 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 722 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 723 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 724 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 725 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 726 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 727 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 728 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 729 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 730 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 731 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 732 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 733 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 734 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 735 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 736 737 #if defined(CONFIG_CMD_KGDB) 738 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 739 #endif 740 741 /* 742 * Environment Configuration 743 */ 744 #define CONFIG_ENV_OVERWRITE 745 746 #if defined(CONFIG_TSEC_ENET) 747 #define CONFIG_HAS_ETH1 748 #define CONFIG_HAS_ETH0 749 #endif 750 751 #define CONFIG_HOSTNAME mpc8349emds 752 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 753 #define CONFIG_BOOTFILE "uImage" 754 755 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 756 757 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 758 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 759 760 #define CONFIG_BAUDRATE 115200 761 762 #define CONFIG_PREBOOT "echo;" \ 763 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 764 "echo" 765 766 #define CONFIG_EXTRA_ENV_SETTINGS \ 767 "netdev=eth0\0" \ 768 "hostname=mpc8349emds\0" \ 769 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 770 "nfsroot=${serverip}:${rootpath}\0" \ 771 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 772 "addip=setenv bootargs ${bootargs} " \ 773 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 774 ":${hostname}:${netdev}:off panic=1\0" \ 775 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 776 "flash_nfs=run nfsargs addip addtty;" \ 777 "bootm ${kernel_addr}\0" \ 778 "flash_self=run ramargs addip addtty;" \ 779 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 780 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 781 "bootm\0" \ 782 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 783 "update=protect off fe000000 fe03ffff; " \ 784 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 785 "upd=run load update\0" \ 786 "fdtaddr=780000\0" \ 787 "fdtfile=mpc834x_mds.dtb\0" \ 788 "" 789 790 #define CONFIG_NFSBOOTCOMMAND \ 791 "setenv bootargs root=/dev/nfs rw " \ 792 "nfsroot=$serverip:$rootpath " \ 793 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 794 "$netdev:off " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $loadaddr $bootfile;" \ 797 "tftp $fdtaddr $fdtfile;" \ 798 "bootm $loadaddr - $fdtaddr" 799 800 #define CONFIG_RAMBOOTCOMMAND \ 801 "setenv bootargs root=/dev/ram rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "tftp $ramdiskaddr $ramdiskfile;" \ 804 "tftp $loadaddr $bootfile;" \ 805 "tftp $fdtaddr $fdtfile;" \ 806 "bootm $loadaddr $ramdiskaddr $fdtaddr" 807 808 #define CONFIG_BOOTCOMMAND "run flash_self" 809 810 #endif /* __CONFIG_H */ 811