1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * mpc8349emds board configuration file 9 * 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x family */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 22 #define CONFIG_PCI_66M 23 #ifdef CONFIG_PCI_66M 24 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 25 #else 26 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 27 #endif 28 29 #ifdef CONFIG_PCISLAVE 30 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 31 #endif /* CONFIG_PCISLAVE */ 32 33 #ifndef CONFIG_SYS_CLK_FREQ 34 #ifdef CONFIG_PCI_66M 35 #define CONFIG_SYS_CLK_FREQ 66000000 36 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 37 #else 38 #define CONFIG_SYS_CLK_FREQ 33000000 39 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 40 #endif 41 #endif 42 43 #define CONFIG_SYS_IMMR 0xE0000000 44 45 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 46 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 47 #define CONFIG_SYS_MEMTEST_END 0x00100000 48 49 /* 50 * DDR Setup 51 */ 52 #define CONFIG_DDR_ECC /* support DDR ECC function */ 53 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 54 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 55 56 /* 57 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver 58 * unselect it to use old spd_sdram.c 59 */ 60 #define CONFIG_SYS_SPD_BUS_NUM 0 61 #define SPD_EEPROM_ADDRESS1 0x52 62 #define SPD_EEPROM_ADDRESS2 0x51 63 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 64 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 66 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 67 68 /* 69 * 32-bit data path mode. 70 * 71 * Please note that using this mode for devices with the real density of 64-bit 72 * effectively reduces the amount of available memory due to the effect of 73 * wrapping around while translating address to row/columns, for example in the 74 * 256MB module the upper 128MB get aliased with contents of the lower 75 * 128MB); normally this define should be used for devices with real 32-bit 76 * data path. 77 */ 78 #undef CONFIG_DDR_32BIT 79 80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 82 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 83 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 84 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 85 #undef CONFIG_DDR_2T_TIMING 86 87 /* 88 * DDRCDR - DDR Control Driver Register 89 */ 90 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 91 92 #if defined(CONFIG_SPD_EEPROM) 93 /* 94 * Determine DDR configuration from I2C interface. 95 */ 96 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 97 #else 98 /* 99 * Manually set up DDR parameters 100 */ 101 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 102 #if defined(CONFIG_DDR_II) 103 #define CONFIG_SYS_DDRCDR 0x80080001 104 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 105 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 106 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 107 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 108 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 109 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 110 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 111 #define CONFIG_SYS_DDR_MODE 0x47d00432 112 #define CONFIG_SYS_DDR_MODE2 0x8000c000 113 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 114 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 115 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 116 #else 117 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 118 | CSCONFIG_ROW_BIT_13 \ 119 | CSCONFIG_COL_BIT_10) 120 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 122 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 123 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 124 125 #if defined(CONFIG_DDR_32BIT) 126 /* set burst length to 8 for 32-bit data path */ 127 /* DLL,normal,seq,4/2.5, 8 burst len */ 128 #define CONFIG_SYS_DDR_MODE 0x00000023 129 #else 130 /* the default burst length is 4 - for 64-bit data path */ 131 /* DLL,normal,seq,4/2.5, 4 burst len */ 132 #define CONFIG_SYS_DDR_MODE 0x00000022 133 #endif 134 #endif 135 #endif 136 137 /* 138 * SDRAM on the Local Bus 139 */ 140 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 141 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 142 143 /* 144 * FLASH on the Local Bus 145 */ 146 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 147 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 148 149 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 150 | BR_PS_16 /* 16 bit port */ \ 151 | BR_MS_GPCM /* MSEL = GPCM */ \ 152 | BR_V) /* valid */ 153 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 154 | OR_UPM_XAM \ 155 | OR_GPCM_CSNT \ 156 | OR_GPCM_ACS_DIV2 \ 157 | OR_GPCM_XACS \ 158 | OR_GPCM_SCY_15 \ 159 | OR_GPCM_TRLX_SET \ 160 | OR_GPCM_EHTR_SET \ 161 | OR_GPCM_EAD) 162 163 /* window base at flash base */ 164 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 165 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 166 167 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 168 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 169 170 #undef CONFIG_SYS_FLASH_CHECKSUM 171 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 172 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 173 174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 175 176 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 177 #define CONFIG_SYS_RAMBOOT 178 #else 179 #undef CONFIG_SYS_RAMBOOT 180 #endif 181 182 /* 183 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 184 */ 185 #define CONFIG_SYS_BCSR 0xE2400000 186 /* Access window base at BCSR base */ 187 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 188 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 189 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 190 | BR_PS_8 \ 191 | BR_MS_GPCM \ 192 | BR_V) 193 /* 0x00000801 */ 194 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 195 | OR_GPCM_XAM \ 196 | OR_GPCM_CSNT \ 197 | OR_GPCM_SCY_15 \ 198 | OR_GPCM_TRLX_CLEAR \ 199 | OR_GPCM_EHTR_CLEAR) 200 /* 0xFFFFE8F0 */ 201 202 #define CONFIG_SYS_INIT_RAM_LOCK 1 203 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 204 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 205 206 #define CONFIG_SYS_GBL_DATA_OFFSET \ 207 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 208 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 209 210 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 211 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 212 213 /* 214 * Local Bus LCRR and LBCR regs 215 * LCRR: DLL bypass, Clock divider is 4 216 * External Local Bus rate is 217 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 218 */ 219 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 220 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 221 #define CONFIG_SYS_LBC_LBCR 0x00000000 222 223 /* 224 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 225 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 226 */ 227 #undef CONFIG_SYS_LB_SDRAM 228 229 #ifdef CONFIG_SYS_LB_SDRAM 230 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 231 /* 232 * Base Register 2 and Option Register 2 configure SDRAM. 233 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 234 * 235 * For BR2, need: 236 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 237 * port-size = 32-bits = BR2[19:20] = 11 238 * no parity checking = BR2[21:22] = 00 239 * SDRAM for MSEL = BR2[24:26] = 011 240 * Valid = BR[31] = 1 241 * 242 * 0 4 8 12 16 20 24 28 243 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 244 */ 245 246 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 247 | BR_PS_32 /* 32-bit port */ \ 248 | BR_MS_SDRAM /* MSEL = SDRAM */ \ 249 | BR_V) /* Valid */ 250 /* 0xF0001861 */ 251 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 252 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 253 254 /* 255 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 256 * 257 * For OR2, need: 258 * 64MB mask for AM, OR2[0:7] = 1111 1100 259 * XAM, OR2[17:18] = 11 260 * 9 columns OR2[19-21] = 010 261 * 13 rows OR2[23-25] = 100 262 * EAD set for extra time OR[31] = 1 263 * 264 * 0 4 8 12 16 20 24 28 265 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 266 */ 267 268 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ 269 | OR_SDRAM_XAM \ 270 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 271 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 272 | OR_SDRAM_EAD) 273 /* 0xFC006901 */ 274 275 /* LB sdram refresh timer, about 6us */ 276 #define CONFIG_SYS_LBC_LSRT 0x32000000 277 /* LB refresh timer prescal, 266MHz/32 */ 278 #define CONFIG_SYS_LBC_MRTPR 0x20000000 279 280 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 281 | LSDMR_BSMA1516 \ 282 | LSDMR_RFCR8 \ 283 | LSDMR_PRETOACT6 \ 284 | LSDMR_ACTTORW3 \ 285 | LSDMR_BL8 \ 286 | LSDMR_WRC3 \ 287 | LSDMR_CL3) 288 289 /* 290 * SDRAM Controller configuration sequence. 291 */ 292 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 293 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 294 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 295 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 296 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 297 #endif 298 299 /* 300 * Serial Port 301 */ 302 #define CONFIG_SYS_NS16550_SERIAL 303 #define CONFIG_SYS_NS16550_REG_SIZE 1 304 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 305 306 #define CONFIG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 308 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 311 312 /* I2C */ 313 #define CONFIG_SYS_I2C 314 #define CONFIG_SYS_I2C_FSL 315 #define CONFIG_SYS_FSL_I2C_SPEED 400000 316 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 317 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 318 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 319 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 320 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 321 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 322 323 /* SPI */ 324 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 325 326 /* GPIOs. Used as SPI chip selects */ 327 #define CONFIG_SYS_GPIO1_PRELIM 328 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 329 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 330 331 /* TSEC */ 332 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 333 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 334 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 335 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 336 337 /* USB */ 338 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 339 340 /* 341 * General PCI 342 * Addresses are mapped 1-1. 343 */ 344 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 345 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 346 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 347 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 348 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 349 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 350 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 351 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 352 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 353 354 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 355 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 356 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 357 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 358 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 359 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 360 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 361 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 362 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 363 364 #if defined(CONFIG_PCI) 365 366 #define PCI_ONE_PCI1 367 #if defined(PCI_64BIT) 368 #undef PCI_ALL_PCI1 369 #undef PCI_TWO_PCI1 370 #undef PCI_ONE_PCI1 371 #endif 372 373 #define CONFIG_83XX_PCI_STREAMING 374 375 #undef CONFIG_EEPRO100 376 #undef CONFIG_TULIP 377 378 #if !defined(CONFIG_PCI_PNP) 379 #define PCI_ENET0_IOADDR 0xFIXME 380 #define PCI_ENET0_MEMADDR 0xFIXME 381 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 382 #endif 383 384 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 385 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 386 387 #endif /* CONFIG_PCI */ 388 389 /* 390 * TSEC configuration 391 */ 392 393 #if defined(CONFIG_TSEC_ENET) 394 395 #define CONFIG_GMII 1 /* MII PHY management */ 396 #define CONFIG_TSEC1 1 397 #define CONFIG_TSEC1_NAME "TSEC0" 398 #define CONFIG_TSEC2 1 399 #define CONFIG_TSEC2_NAME "TSEC1" 400 #define TSEC1_PHY_ADDR 0 401 #define TSEC2_PHY_ADDR 1 402 #define TSEC1_PHYIDX 0 403 #define TSEC2_PHYIDX 0 404 #define TSEC1_FLAGS TSEC_GIGABIT 405 #define TSEC2_FLAGS TSEC_GIGABIT 406 407 /* Options are: TSEC[0-1] */ 408 #define CONFIG_ETHPRIME "TSEC0" 409 410 #endif /* CONFIG_TSEC_ENET */ 411 412 /* 413 * Configure on-board RTC 414 */ 415 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 416 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 417 418 /* 419 * Environment 420 */ 421 #ifndef CONFIG_SYS_RAMBOOT 422 #define CONFIG_ENV_ADDR \ 423 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 424 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 425 #define CONFIG_ENV_SIZE 0x2000 426 427 /* Address and size of Redundant Environment Sector */ 428 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 429 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 430 431 #else 432 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 433 #define CONFIG_ENV_SIZE 0x2000 434 #endif 435 436 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 437 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 438 439 /* 440 * BOOTP options 441 */ 442 #define CONFIG_BOOTP_BOOTFILESIZE 443 444 /* 445 * Command line configuration. 446 */ 447 448 #undef CONFIG_WATCHDOG /* watchdog disabled */ 449 450 /* 451 * Miscellaneous configurable options 452 */ 453 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 454 455 /* 456 * For booting Linux, the board info and command line data 457 * have to be in the first 256 MB of memory, since this is 458 * the maximum mapped by the Linux kernel during initialization. 459 */ 460 /* Initial Memory map for Linux*/ 461 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 462 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 463 464 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 465 466 #if 1 /*528/264*/ 467 #define CONFIG_SYS_HRCW_LOW (\ 468 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 469 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 470 HRCWL_CSB_TO_CLKIN |\ 471 HRCWL_VCO_1X2 |\ 472 HRCWL_CORE_TO_CSB_2X1) 473 #elif 0 /*396/132*/ 474 #define CONFIG_SYS_HRCW_LOW (\ 475 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 476 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 477 HRCWL_CSB_TO_CLKIN |\ 478 HRCWL_VCO_1X4 |\ 479 HRCWL_CORE_TO_CSB_3X1) 480 #elif 0 /*264/132*/ 481 #define CONFIG_SYS_HRCW_LOW (\ 482 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 483 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 484 HRCWL_CSB_TO_CLKIN |\ 485 HRCWL_VCO_1X4 |\ 486 HRCWL_CORE_TO_CSB_2X1) 487 #elif 0 /*132/132*/ 488 #define CONFIG_SYS_HRCW_LOW (\ 489 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 490 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 491 HRCWL_CSB_TO_CLKIN |\ 492 HRCWL_VCO_1X4 |\ 493 HRCWL_CORE_TO_CSB_1X1) 494 #elif 0 /*264/264 */ 495 #define CONFIG_SYS_HRCW_LOW (\ 496 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 497 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 498 HRCWL_CSB_TO_CLKIN |\ 499 HRCWL_VCO_1X4 |\ 500 HRCWL_CORE_TO_CSB_1X1) 501 #endif 502 503 #ifdef CONFIG_PCISLAVE 504 #define CONFIG_SYS_HRCW_HIGH (\ 505 HRCWH_PCI_AGENT |\ 506 HRCWH_64_BIT_PCI |\ 507 HRCWH_PCI1_ARBITER_DISABLE |\ 508 HRCWH_PCI2_ARBITER_DISABLE |\ 509 HRCWH_CORE_ENABLE |\ 510 HRCWH_FROM_0X00000100 |\ 511 HRCWH_BOOTSEQ_DISABLE |\ 512 HRCWH_SW_WATCHDOG_DISABLE |\ 513 HRCWH_ROM_LOC_LOCAL_16BIT |\ 514 HRCWH_TSEC1M_IN_GMII |\ 515 HRCWH_TSEC2M_IN_GMII) 516 #else 517 #if defined(PCI_64BIT) 518 #define CONFIG_SYS_HRCW_HIGH (\ 519 HRCWH_PCI_HOST |\ 520 HRCWH_64_BIT_PCI |\ 521 HRCWH_PCI1_ARBITER_ENABLE |\ 522 HRCWH_PCI2_ARBITER_DISABLE |\ 523 HRCWH_CORE_ENABLE |\ 524 HRCWH_FROM_0X00000100 |\ 525 HRCWH_BOOTSEQ_DISABLE |\ 526 HRCWH_SW_WATCHDOG_DISABLE |\ 527 HRCWH_ROM_LOC_LOCAL_16BIT |\ 528 HRCWH_TSEC1M_IN_GMII |\ 529 HRCWH_TSEC2M_IN_GMII) 530 #else 531 #define CONFIG_SYS_HRCW_HIGH (\ 532 HRCWH_PCI_HOST |\ 533 HRCWH_32_BIT_PCI |\ 534 HRCWH_PCI1_ARBITER_ENABLE |\ 535 HRCWH_PCI2_ARBITER_ENABLE |\ 536 HRCWH_CORE_ENABLE |\ 537 HRCWH_FROM_0X00000100 |\ 538 HRCWH_BOOTSEQ_DISABLE |\ 539 HRCWH_SW_WATCHDOG_DISABLE |\ 540 HRCWH_ROM_LOC_LOCAL_16BIT |\ 541 HRCWH_TSEC1M_IN_GMII |\ 542 HRCWH_TSEC2M_IN_GMII) 543 #endif /* PCI_64BIT */ 544 #endif /* CONFIG_PCISLAVE */ 545 546 /* 547 * System performance 548 */ 549 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 550 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 551 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 552 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 553 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 554 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 555 556 /* System IO Config */ 557 #define CONFIG_SYS_SICRH 0 558 #define CONFIG_SYS_SICRL SICRL_LDP_A 559 560 #define CONFIG_SYS_HID0_INIT 0x000000000 561 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 562 | HID0_ENABLE_INSTRUCTION_CACHE) 563 564 /* #define CONFIG_SYS_HID0_FINAL (\ 565 HID0_ENABLE_INSTRUCTION_CACHE |\ 566 HID0_ENABLE_M_BIT |\ 567 HID0_ENABLE_ADDRESS_BROADCAST) */ 568 569 #define CONFIG_SYS_HID2 HID2_HBE 570 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 571 572 /* DDR @ 0x00000000 */ 573 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 574 | BATL_PP_RW \ 575 | BATL_MEMCOHERENCE) 576 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 577 | BATU_BL_256M \ 578 | BATU_VS \ 579 | BATU_VP) 580 581 /* PCI @ 0x80000000 */ 582 #ifdef CONFIG_PCI 583 #define CONFIG_PCI_INDIRECT_BRIDGE 584 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 585 | BATL_PP_RW \ 586 | BATL_MEMCOHERENCE) 587 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 588 | BATU_BL_256M \ 589 | BATU_VS \ 590 | BATU_VP) 591 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 592 | BATL_PP_RW \ 593 | BATL_CACHEINHIBIT \ 594 | BATL_GUARDEDSTORAGE) 595 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 596 | BATU_BL_256M \ 597 | BATU_VS \ 598 | BATU_VP) 599 #else 600 #define CONFIG_SYS_IBAT1L (0) 601 #define CONFIG_SYS_IBAT1U (0) 602 #define CONFIG_SYS_IBAT2L (0) 603 #define CONFIG_SYS_IBAT2U (0) 604 #endif 605 606 #ifdef CONFIG_MPC83XX_PCI2 607 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 608 | BATL_PP_RW \ 609 | BATL_MEMCOHERENCE) 610 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 611 | BATU_BL_256M \ 612 | BATU_VS \ 613 | BATU_VP) 614 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 615 | BATL_PP_RW \ 616 | BATL_CACHEINHIBIT \ 617 | BATL_GUARDEDSTORAGE) 618 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 619 | BATU_BL_256M \ 620 | BATU_VS \ 621 | BATU_VP) 622 #else 623 #define CONFIG_SYS_IBAT3L (0) 624 #define CONFIG_SYS_IBAT3U (0) 625 #define CONFIG_SYS_IBAT4L (0) 626 #define CONFIG_SYS_IBAT4U (0) 627 #endif 628 629 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 630 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 631 | BATL_PP_RW \ 632 | BATL_CACHEINHIBIT \ 633 | BATL_GUARDEDSTORAGE) 634 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 635 | BATU_BL_256M \ 636 | BATU_VS \ 637 | BATU_VP) 638 639 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 640 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 641 | BATL_PP_RW \ 642 | BATL_MEMCOHERENCE \ 643 | BATL_GUARDEDSTORAGE) 644 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 645 | BATU_BL_256M \ 646 | BATU_VS \ 647 | BATU_VP) 648 649 #define CONFIG_SYS_IBAT7L (0) 650 #define CONFIG_SYS_IBAT7U (0) 651 652 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 653 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 654 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 655 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 656 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 657 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 658 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 659 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 660 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 661 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 662 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 663 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 664 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 665 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 666 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 667 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 668 669 #if defined(CONFIG_CMD_KGDB) 670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 671 #endif 672 673 /* 674 * Environment Configuration 675 */ 676 #define CONFIG_ENV_OVERWRITE 677 678 #if defined(CONFIG_TSEC_ENET) 679 #define CONFIG_HAS_ETH1 680 #define CONFIG_HAS_ETH0 681 #endif 682 683 #define CONFIG_HOSTNAME "mpc8349emds" 684 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 685 #define CONFIG_BOOTFILE "uImage" 686 687 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 688 689 #define CONFIG_PREBOOT "echo;" \ 690 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 691 "echo" 692 693 #define CONFIG_EXTRA_ENV_SETTINGS \ 694 "netdev=eth0\0" \ 695 "hostname=mpc8349emds\0" \ 696 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 697 "nfsroot=${serverip}:${rootpath}\0" \ 698 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 699 "addip=setenv bootargs ${bootargs} " \ 700 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 701 ":${hostname}:${netdev}:off panic=1\0" \ 702 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 703 "flash_nfs=run nfsargs addip addtty;" \ 704 "bootm ${kernel_addr}\0" \ 705 "flash_self=run ramargs addip addtty;" \ 706 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 707 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 708 "bootm\0" \ 709 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 710 "update=protect off fe000000 fe03ffff; " \ 711 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 712 "upd=run load update\0" \ 713 "fdtaddr=780000\0" \ 714 "fdtfile=mpc834x_mds.dtb\0" \ 715 "" 716 717 #define CONFIG_NFSBOOTCOMMAND \ 718 "setenv bootargs root=/dev/nfs rw " \ 719 "nfsroot=$serverip:$rootpath " \ 720 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 721 "$netdev:off " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr - $fdtaddr" 726 727 #define CONFIG_RAMBOOTCOMMAND \ 728 "setenv bootargs root=/dev/ram rw " \ 729 "console=$consoledev,$baudrate $othbootargs;" \ 730 "tftp $ramdiskaddr $ramdiskfile;" \ 731 "tftp $loadaddr $bootfile;" \ 732 "tftp $fdtaddr $fdtfile;" \ 733 "bootm $loadaddr $ramdiskaddr $fdtaddr" 734 735 #define CONFIG_BOOTCOMMAND "run flash_self" 736 737 #endif /* __CONFIG_H */ 738