1 /*
2  * (C) Copyright 2006-2010
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * mpc8349emds board configuration file
10  *
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 #define CONFIG_DISPLAY_BOARDINFO
17 
18 /*
19  * High Level Configuration Options
20  */
21 #define CONFIG_E300		1	/* E300 Family */
22 #define CONFIG_MPC834x		1	/* MPC834x family */
23 #define CONFIG_MPC8349		1	/* MPC8349 specific */
24 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
25 
26 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
27 
28 #define CONFIG_PCI_66M
29 #ifdef CONFIG_PCI_66M
30 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
31 #else
32 #define CONFIG_83XX_CLKIN	33000000	/* in Hz */
33 #endif
34 
35 #ifdef CONFIG_PCISLAVE
36 #define CONFIG_PCI
37 #define CONFIG_83XX_PCICLK	66666666	/* in Hz */
38 #endif /* CONFIG_PCISLAVE */
39 
40 #ifndef CONFIG_SYS_CLK_FREQ
41 #ifdef CONFIG_PCI_66M
42 #define CONFIG_SYS_CLK_FREQ	66000000
43 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
44 #else
45 #define CONFIG_SYS_CLK_FREQ	33000000
46 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
47 #endif
48 #endif
49 
50 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
51 
52 #define CONFIG_SYS_IMMR		0xE0000000
53 
54 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
55 #define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
56 #define CONFIG_SYS_MEMTEST_END		0x00100000
57 
58 /*
59  * DDR Setup
60  */
61 #define CONFIG_DDR_ECC			/* support DDR ECC function */
62 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
63 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
64 
65 /*
66  * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
67  * undefine it to use old spd_sdram.c
68  */
69 #define CONFIG_SYS_FSL_DDR2
70 #ifdef CONFIG_SYS_FSL_DDR2
71 #define CONFIG_SYS_FSL_DDRC_GEN2
72 #define CONFIG_SYS_SPD_BUS_NUM	0
73 #define SPD_EEPROM_ADDRESS1	0x52
74 #define SPD_EEPROM_ADDRESS2	0x51
75 #define CONFIG_NUM_DDR_CONTROLLERS	1
76 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
77 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
79 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
80 #endif
81 
82 /*
83  * 32-bit data path mode.
84  *
85  * Please note that using this mode for devices with the real density of 64-bit
86  * effectively reduces the amount of available memory due to the effect of
87  * wrapping around while translating address to row/columns, for example in the
88  * 256MB module the upper 128MB get aliased with contents of the lower
89  * 128MB); normally this define should be used for devices with real 32-bit
90  * data path.
91  */
92 #undef CONFIG_DDR_32BIT
93 
94 #define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory*/
95 #define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
96 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
97 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
98 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
99 #undef  CONFIG_DDR_2T_TIMING
100 
101 /*
102  * DDRCDR - DDR Control Driver Register
103  */
104 #define CONFIG_SYS_DDRCDR_VALUE	0x80080001
105 
106 #if defined(CONFIG_SPD_EEPROM)
107 /*
108  * Determine DDR configuration from I2C interface.
109  */
110 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
111 #else
112 /*
113  * Manually set up DDR parameters
114  */
115 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
116 #if defined(CONFIG_DDR_II)
117 #define CONFIG_SYS_DDRCDR		0x80080001
118 #define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
119 #define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
120 #define CONFIG_SYS_DDR_TIMING_0		0x00220802
121 #define CONFIG_SYS_DDR_TIMING_1		0x38357322
122 #define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
123 #define CONFIG_SYS_DDR_TIMING_3		0x00000000
124 #define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
125 #define CONFIG_SYS_DDR_MODE		0x47d00432
126 #define CONFIG_SYS_DDR_MODE2		0x8000c000
127 #define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
128 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
129 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
130 #else
131 #define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
132 				| CSCONFIG_ROW_BIT_13 \
133 				| CSCONFIG_COL_BIT_10)
134 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
135 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
136 #define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
137 #define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
138 
139 #if defined(CONFIG_DDR_32BIT)
140 /* set burst length to 8 for 32-bit data path */
141 				/* DLL,normal,seq,4/2.5, 8 burst len */
142 #define CONFIG_SYS_DDR_MODE	0x00000023
143 #else
144 /* the default burst length is 4 - for 64-bit data path */
145 				/* DLL,normal,seq,4/2.5, 4 burst len */
146 #define CONFIG_SYS_DDR_MODE	0x00000022
147 #endif
148 #endif
149 #endif
150 
151 /*
152  * SDRAM on the Local Bus
153  */
154 #define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
155 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
156 
157 /*
158  * FLASH on the Local Bus
159  */
160 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
161 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
162 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
163 #define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */
164 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
165 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
166 
167 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
168 				| BR_PS_16	/* 16 bit port  */ \
169 				| BR_MS_GPCM	/* MSEL = GPCM */ \
170 				| BR_V)		/* valid */
171 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
172 				| OR_UPM_XAM \
173 				| OR_GPCM_CSNT \
174 				| OR_GPCM_ACS_DIV2 \
175 				| OR_GPCM_XACS \
176 				| OR_GPCM_SCY_15 \
177 				| OR_GPCM_TRLX_SET \
178 				| OR_GPCM_EHTR_SET \
179 				| OR_GPCM_EAD)
180 
181 					/* window base at flash base */
182 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
183 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
184 
185 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
187 
188 #undef CONFIG_SYS_FLASH_CHECKSUM
189 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
190 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
191 
192 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
193 
194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195 #define CONFIG_SYS_RAMBOOT
196 #else
197 #undef  CONFIG_SYS_RAMBOOT
198 #endif
199 
200 /*
201  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
202  */
203 #define CONFIG_SYS_BCSR			0xE2400000
204 					/* Access window base at BCSR base */
205 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
206 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
207 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
208 					| BR_PS_8 \
209 					| BR_MS_GPCM \
210 					| BR_V)
211 					/* 0x00000801 */
212 #define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
213 					| OR_GPCM_XAM \
214 					| OR_GPCM_CSNT \
215 					| OR_GPCM_SCY_15 \
216 					| OR_GPCM_TRLX_CLEAR \
217 					| OR_GPCM_EHTR_CLEAR)
218 					/* 0xFFFFE8F0 */
219 
220 #define CONFIG_SYS_INIT_RAM_LOCK	1
221 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
222 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
223 
224 #define CONFIG_SYS_GBL_DATA_OFFSET	\
225 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
227 
228 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
229 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
230 
231 /*
232  * Local Bus LCRR and LBCR regs
233  *    LCRR:  DLL bypass, Clock divider is 4
234  * External Local Bus rate is
235  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
236  */
237 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
238 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
239 #define CONFIG_SYS_LBC_LBCR	0x00000000
240 
241 /*
242  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
243  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
244  */
245 #undef CONFIG_SYS_LB_SDRAM
246 
247 #ifdef CONFIG_SYS_LB_SDRAM
248 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
249 /*
250  * Base Register 2 and Option Register 2 configure SDRAM.
251  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
252  *
253  * For BR2, need:
254  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
255  *    port-size = 32-bits = BR2[19:20] = 11
256  *    no parity checking = BR2[21:22] = 00
257  *    SDRAM for MSEL = BR2[24:26] = 011
258  *    Valid = BR[31] = 1
259  *
260  * 0    4    8    12   16   20   24   28
261  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
262  */
263 
264 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LBC_SDRAM_BASE \
265 					| BR_PS_32	/* 32-bit port */ \
266 					| BR_MS_SDRAM	/* MSEL = SDRAM */ \
267 					| BR_V)		/* Valid */
268 					/* 0xF0001861 */
269 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
270 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
271 
272 /*
273  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
274  *
275  * For OR2, need:
276  *    64MB mask for AM, OR2[0:7] = 1111 1100
277  *                 XAM, OR2[17:18] = 11
278  *    9 columns OR2[19-21] = 010
279  *    13 rows   OR2[23-25] = 100
280  *    EAD set for extra time OR[31] = 1
281  *
282  * 0    4    8    12   16   20   24   28
283  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
284  */
285 
286 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_64MB \
287 			| OR_SDRAM_XAM \
288 			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
289 			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
290 			| OR_SDRAM_EAD)
291 			/* 0xFC006901 */
292 
293 				/* LB sdram refresh timer, about 6us */
294 #define CONFIG_SYS_LBC_LSRT	0x32000000
295 				/* LB refresh timer prescal, 266MHz/32 */
296 #define CONFIG_SYS_LBC_MRTPR	0x20000000
297 
298 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN	\
299 				| LSDMR_BSMA1516	\
300 				| LSDMR_RFCR8		\
301 				| LSDMR_PRETOACT6	\
302 				| LSDMR_ACTTORW3	\
303 				| LSDMR_BL8		\
304 				| LSDMR_WRC3		\
305 				| LSDMR_CL3)
306 
307 /*
308  * SDRAM Controller configuration sequence.
309  */
310 #define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
311 #define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
312 #define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
313 #define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
314 #define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
315 #endif
316 
317 /*
318  * Serial Port
319  */
320 #define CONFIG_CONS_INDEX     1
321 #define CONFIG_SYS_NS16550
322 #define CONFIG_SYS_NS16550_SERIAL
323 #define CONFIG_SYS_NS16550_REG_SIZE    1
324 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
325 
326 #define CONFIG_SYS_BAUDRATE_TABLE  \
327 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
328 
329 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
330 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
331 
332 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
333 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
334 /* Use the HUSH parser */
335 #define CONFIG_SYS_HUSH_PARSER
336 
337 /* pass open firmware flat tree */
338 #define CONFIG_OF_LIBFDT	1
339 #define CONFIG_OF_BOARD_SETUP	1
340 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
341 
342 /* I2C */
343 #define CONFIG_SYS_I2C
344 #define CONFIG_SYS_I2C_FSL
345 #define CONFIG_SYS_FSL_I2C_SPEED	400000
346 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
347 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
348 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
349 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
350 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
351 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
352 
353 /* SPI */
354 #define CONFIG_MPC8XXX_SPI
355 #undef CONFIG_SOFT_SPI			/* SPI bit-banged */
356 
357 /* GPIOs.  Used as SPI chip selects */
358 #define CONFIG_SYS_GPIO1_PRELIM
359 #define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
360 #define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
361 
362 /* TSEC */
363 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
364 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
365 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
366 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
367 
368 /* USB */
369 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
370 
371 /*
372  * General PCI
373  * Addresses are mapped 1-1.
374  */
375 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
376 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
377 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
378 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
379 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
380 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
381 #define CONFIG_SYS_PCI1_IO_BASE		0x00000000
382 #define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
383 #define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
384 
385 #define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
386 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
387 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
388 #define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
389 #define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
390 #define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
391 #define CONFIG_SYS_PCI2_IO_BASE		0x00000000
392 #define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
393 #define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
394 
395 #if defined(CONFIG_PCI)
396 
397 #define PCI_ONE_PCI1
398 #if defined(PCI_64BIT)
399 #undef PCI_ALL_PCI1
400 #undef PCI_TWO_PCI1
401 #undef PCI_ONE_PCI1
402 #endif
403 
404 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
405 #define CONFIG_83XX_PCI_STREAMING
406 
407 #undef CONFIG_EEPRO100
408 #undef CONFIG_TULIP
409 
410 #if !defined(CONFIG_PCI_PNP)
411 	#define PCI_ENET0_IOADDR	0xFIXME
412 	#define PCI_ENET0_MEMADDR	0xFIXME
413 	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
414 #endif
415 
416 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
417 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
418 
419 #endif	/* CONFIG_PCI */
420 
421 /*
422  * TSEC configuration
423  */
424 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
425 
426 #if defined(CONFIG_TSEC_ENET)
427 
428 #define CONFIG_GMII		1	/* MII PHY management */
429 #define CONFIG_TSEC1		1
430 #define CONFIG_TSEC1_NAME	"TSEC0"
431 #define CONFIG_TSEC2		1
432 #define CONFIG_TSEC2_NAME	"TSEC1"
433 #define TSEC1_PHY_ADDR		0
434 #define TSEC2_PHY_ADDR		1
435 #define TSEC1_PHYIDX		0
436 #define TSEC2_PHYIDX		0
437 #define TSEC1_FLAGS		TSEC_GIGABIT
438 #define TSEC2_FLAGS		TSEC_GIGABIT
439 
440 /* Options are: TSEC[0-1] */
441 #define CONFIG_ETHPRIME		"TSEC0"
442 
443 #endif	/* CONFIG_TSEC_ENET */
444 
445 /*
446  * Configure on-board RTC
447  */
448 #define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
449 #define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
450 
451 /*
452  * Environment
453  */
454 #ifndef CONFIG_SYS_RAMBOOT
455 	#define CONFIG_ENV_IS_IN_FLASH	1
456 	#define CONFIG_ENV_ADDR		\
457 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
458 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
459 	#define CONFIG_ENV_SIZE		0x2000
460 
461 /* Address and size of Redundant Environment Sector	*/
462 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
463 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
464 
465 #else
466 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
467 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
468 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
469 	#define CONFIG_ENV_SIZE		0x2000
470 #endif
471 
472 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
473 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
474 
475 
476 /*
477  * BOOTP options
478  */
479 #define CONFIG_BOOTP_BOOTFILESIZE
480 #define CONFIG_BOOTP_BOOTPATH
481 #define CONFIG_BOOTP_GATEWAY
482 #define CONFIG_BOOTP_HOSTNAME
483 
484 
485 /*
486  * Command line configuration.
487  */
488 #define CONFIG_CMD_PING
489 #define CONFIG_CMD_I2C
490 #define CONFIG_CMD_DATE
491 #define CONFIG_CMD_MII
492 
493 #if defined(CONFIG_PCI)
494     #define CONFIG_CMD_PCI
495 #endif
496 
497 #undef CONFIG_WATCHDOG			/* watchdog disabled */
498 
499 /*
500  * Miscellaneous configurable options
501  */
502 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
503 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
504 
505 #if defined(CONFIG_CMD_KGDB)
506 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
507 #else
508 	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
509 #endif
510 
511 				/* Print Buffer Size */
512 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
513 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
514 				/* Boot Argument Buffer Size */
515 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
516 
517 /*
518  * For booting Linux, the board info and command line data
519  * have to be in the first 256 MB of memory, since this is
520  * the maximum mapped by the Linux kernel during initialization.
521  */
522 				/* Initial Memory map for Linux*/
523 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
524 
525 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
526 
527 #if 1 /*528/264*/
528 #define CONFIG_SYS_HRCW_LOW (\
529 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
530 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
531 	HRCWL_CSB_TO_CLKIN |\
532 	HRCWL_VCO_1X2 |\
533 	HRCWL_CORE_TO_CSB_2X1)
534 #elif 0 /*396/132*/
535 #define CONFIG_SYS_HRCW_LOW (\
536 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
537 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
538 	HRCWL_CSB_TO_CLKIN |\
539 	HRCWL_VCO_1X4 |\
540 	HRCWL_CORE_TO_CSB_3X1)
541 #elif 0 /*264/132*/
542 #define CONFIG_SYS_HRCW_LOW (\
543 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
544 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
545 	HRCWL_CSB_TO_CLKIN |\
546 	HRCWL_VCO_1X4 |\
547 	HRCWL_CORE_TO_CSB_2X1)
548 #elif 0 /*132/132*/
549 #define CONFIG_SYS_HRCW_LOW (\
550 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
551 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
552 	HRCWL_CSB_TO_CLKIN |\
553 	HRCWL_VCO_1X4 |\
554 	HRCWL_CORE_TO_CSB_1X1)
555 #elif 0 /*264/264 */
556 #define CONFIG_SYS_HRCW_LOW (\
557 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
558 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
559 	HRCWL_CSB_TO_CLKIN |\
560 	HRCWL_VCO_1X4 |\
561 	HRCWL_CORE_TO_CSB_1X1)
562 #endif
563 
564 #ifdef CONFIG_PCISLAVE
565 #define CONFIG_SYS_HRCW_HIGH (\
566 	HRCWH_PCI_AGENT |\
567 	HRCWH_64_BIT_PCI |\
568 	HRCWH_PCI1_ARBITER_DISABLE |\
569 	HRCWH_PCI2_ARBITER_DISABLE |\
570 	HRCWH_CORE_ENABLE |\
571 	HRCWH_FROM_0X00000100 |\
572 	HRCWH_BOOTSEQ_DISABLE |\
573 	HRCWH_SW_WATCHDOG_DISABLE |\
574 	HRCWH_ROM_LOC_LOCAL_16BIT |\
575 	HRCWH_TSEC1M_IN_GMII |\
576 	HRCWH_TSEC2M_IN_GMII)
577 #else
578 #if defined(PCI_64BIT)
579 #define CONFIG_SYS_HRCW_HIGH (\
580 	HRCWH_PCI_HOST |\
581 	HRCWH_64_BIT_PCI |\
582 	HRCWH_PCI1_ARBITER_ENABLE |\
583 	HRCWH_PCI2_ARBITER_DISABLE |\
584 	HRCWH_CORE_ENABLE |\
585 	HRCWH_FROM_0X00000100 |\
586 	HRCWH_BOOTSEQ_DISABLE |\
587 	HRCWH_SW_WATCHDOG_DISABLE |\
588 	HRCWH_ROM_LOC_LOCAL_16BIT |\
589 	HRCWH_TSEC1M_IN_GMII |\
590 	HRCWH_TSEC2M_IN_GMII)
591 #else
592 #define CONFIG_SYS_HRCW_HIGH (\
593 	HRCWH_PCI_HOST |\
594 	HRCWH_32_BIT_PCI |\
595 	HRCWH_PCI1_ARBITER_ENABLE |\
596 	HRCWH_PCI2_ARBITER_ENABLE |\
597 	HRCWH_CORE_ENABLE |\
598 	HRCWH_FROM_0X00000100 |\
599 	HRCWH_BOOTSEQ_DISABLE |\
600 	HRCWH_SW_WATCHDOG_DISABLE |\
601 	HRCWH_ROM_LOC_LOCAL_16BIT |\
602 	HRCWH_TSEC1M_IN_GMII |\
603 	HRCWH_TSEC2M_IN_GMII)
604 #endif /* PCI_64BIT */
605 #endif /* CONFIG_PCISLAVE */
606 
607 /*
608  * System performance
609  */
610 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
611 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
612 #define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
613 #define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
614 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
615 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
616 
617 /* System IO Config */
618 #define CONFIG_SYS_SICRH 0
619 #define CONFIG_SYS_SICRL SICRL_LDP_A
620 
621 #define CONFIG_SYS_HID0_INIT	0x000000000
622 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
623 				| HID0_ENABLE_INSTRUCTION_CACHE)
624 
625 /* #define CONFIG_SYS_HID0_FINAL	(\
626 	HID0_ENABLE_INSTRUCTION_CACHE |\
627 	HID0_ENABLE_M_BIT |\
628 	HID0_ENABLE_ADDRESS_BROADCAST) */
629 
630 
631 #define CONFIG_SYS_HID2 HID2_HBE
632 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
633 
634 /* DDR @ 0x00000000 */
635 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
636 				| BATL_PP_RW \
637 				| BATL_MEMCOHERENCE)
638 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
639 				| BATU_BL_256M \
640 				| BATU_VS \
641 				| BATU_VP)
642 
643 /* PCI @ 0x80000000 */
644 #ifdef CONFIG_PCI
645 #define CONFIG_PCI_INDIRECT_BRIDGE
646 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
647 				| BATL_PP_RW \
648 				| BATL_MEMCOHERENCE)
649 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
650 				| BATU_BL_256M \
651 				| BATU_VS \
652 				| BATU_VP)
653 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
654 				| BATL_PP_RW \
655 				| BATL_CACHEINHIBIT \
656 				| BATL_GUARDEDSTORAGE)
657 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
658 				| BATU_BL_256M \
659 				| BATU_VS \
660 				| BATU_VP)
661 #else
662 #define CONFIG_SYS_IBAT1L	(0)
663 #define CONFIG_SYS_IBAT1U	(0)
664 #define CONFIG_SYS_IBAT2L	(0)
665 #define CONFIG_SYS_IBAT2U	(0)
666 #endif
667 
668 #ifdef CONFIG_MPC83XX_PCI2
669 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
670 				| BATL_PP_RW \
671 				| BATL_MEMCOHERENCE)
672 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
673 				| BATU_BL_256M \
674 				| BATU_VS \
675 				| BATU_VP)
676 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
677 				| BATL_PP_RW \
678 				| BATL_CACHEINHIBIT \
679 				| BATL_GUARDEDSTORAGE)
680 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
681 				| BATU_BL_256M \
682 				| BATU_VS \
683 				| BATU_VP)
684 #else
685 #define CONFIG_SYS_IBAT3L	(0)
686 #define CONFIG_SYS_IBAT3U	(0)
687 #define CONFIG_SYS_IBAT4L	(0)
688 #define CONFIG_SYS_IBAT4U	(0)
689 #endif
690 
691 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
692 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
693 				| BATL_PP_RW \
694 				| BATL_CACHEINHIBIT \
695 				| BATL_GUARDEDSTORAGE)
696 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
697 				| BATU_BL_256M \
698 				| BATU_VS \
699 				| BATU_VP)
700 
701 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
702 #define CONFIG_SYS_IBAT6L	(0xF0000000 \
703 				| BATL_PP_RW \
704 				| BATL_MEMCOHERENCE \
705 				| BATL_GUARDEDSTORAGE)
706 #define CONFIG_SYS_IBAT6U	(0xF0000000 \
707 				| BATU_BL_256M \
708 				| BATU_VS \
709 				| BATU_VP)
710 
711 #define CONFIG_SYS_IBAT7L	(0)
712 #define CONFIG_SYS_IBAT7U	(0)
713 
714 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
715 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
716 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
717 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
718 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
719 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
720 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
721 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
722 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
723 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
724 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
725 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
726 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
727 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
728 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
729 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
730 
731 #if defined(CONFIG_CMD_KGDB)
732 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
733 #endif
734 
735 /*
736  * Environment Configuration
737  */
738 #define CONFIG_ENV_OVERWRITE
739 
740 #if defined(CONFIG_TSEC_ENET)
741 #define CONFIG_HAS_ETH1
742 #define CONFIG_HAS_ETH0
743 #endif
744 
745 #define CONFIG_HOSTNAME		mpc8349emds
746 #define CONFIG_ROOTPATH		"/nfsroot/rootfs"
747 #define CONFIG_BOOTFILE		"uImage"
748 
749 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
750 
751 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
752 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
753 
754 #define CONFIG_BAUDRATE	 115200
755 
756 #define CONFIG_PREBOOT	"echo;"	\
757 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
758 	"echo"
759 
760 #define	CONFIG_EXTRA_ENV_SETTINGS					\
761 	"netdev=eth0\0"							\
762 	"hostname=mpc8349emds\0"					\
763 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
764 		"nfsroot=${serverip}:${rootpath}\0"			\
765 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
766 	"addip=setenv bootargs ${bootargs} "				\
767 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
768 		":${hostname}:${netdev}:off panic=1\0"			\
769 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
770 	"flash_nfs=run nfsargs addip addtty;"				\
771 		"bootm ${kernel_addr}\0"				\
772 	"flash_self=run ramargs addip addtty;"				\
773 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
774 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
775 		"bootm\0"						\
776 	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
777 	"update=protect off fe000000 fe03ffff; "			\
778 		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
779 	"upd=run load update\0"						\
780 	"fdtaddr=780000\0"						\
781 	"fdtfile=mpc834x_mds.dtb\0"					\
782 	""
783 
784 #define CONFIG_NFSBOOTCOMMAND						\
785 	"setenv bootargs root=/dev/nfs rw "				\
786 		"nfsroot=$serverip:$rootpath "				\
787 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
788 							"$netdev:off "	\
789 		"console=$consoledev,$baudrate $othbootargs;"		\
790 	"tftp $loadaddr $bootfile;"					\
791 	"tftp $fdtaddr $fdtfile;"					\
792 	"bootm $loadaddr - $fdtaddr"
793 
794 #define CONFIG_RAMBOOTCOMMAND						\
795 	"setenv bootargs root=/dev/ram rw "				\
796 		"console=$consoledev,$baudrate $othbootargs;"		\
797 	"tftp $ramdiskaddr $ramdiskfile;"				\
798 	"tftp $loadaddr $bootfile;"					\
799 	"tftp $fdtaddr $fdtfile;"					\
800 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
801 
802 #define CONFIG_BOOTCOMMAND	"run flash_self"
803 
804 #endif	/* __CONFIG_H */
805