1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 /* E300 Family */ 36 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 37 #define CONFIG_MPC834X 1 /* MPC834X family */ 38 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 39 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 40 41 #undef CONFIG_PCI 42 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 43 44 #define PCI_66M 45 #ifdef PCI_66M 46 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 47 #else 48 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 49 #endif 50 51 #ifdef CONFIG_PCISLAVE 52 #define CONFIG_PCI 53 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 54 #endif /* CONFIG_PCISLAVE */ 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #ifdef PCI_66M 58 #define CONFIG_SYS_CLK_FREQ 66000000 59 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 60 #else 61 #define CONFIG_SYS_CLK_FREQ 33000000 62 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 63 #endif 64 #endif 65 66 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 67 68 #define CFG_IMMR 0xE0000000 69 70 #undef CFG_DRAM_TEST /* memory test, takes time */ 71 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 72 #define CFG_MEMTEST_END 0x00100000 73 74 /* 75 * DDR Setup 76 */ 77 #define CONFIG_DDR_ECC /* support DDR ECC function */ 78 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 79 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 80 81 /* 82 * 32-bit data path mode. 83 * 84 * Please note that using this mode for devices with the real density of 64-bit 85 * effectively reduces the amount of available memory due to the effect of 86 * wrapping around while translating address to row/columns, for example in the 87 * 256MB module the upper 128MB get aliased with contents of the lower 88 * 128MB); normally this define should be used for devices with real 32-bit 89 * data path. 90 */ 91 #undef CONFIG_DDR_32BIT 92 93 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 94 #define CFG_SDRAM_BASE CFG_DDR_BASE 95 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 96 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 97 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 98 #undef CONFIG_DDR_2T_TIMING 99 100 /* 101 * DDRCDR - DDR Control Driver Register 102 */ 103 #define CFG_DDRCDR_VALUE 0x80080001 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 110 #else 111 /* 112 * Manually set up DDR parameters 113 */ 114 #define CFG_DDR_SIZE 256 /* MB */ 115 #if defined(CONFIG_DDR_II) 116 #define CFG_DDRCDR 0x80080001 117 #define CFG_DDR_CS2_BNDS 0x0000000f 118 #define CFG_DDR_CS2_CONFIG 0x80330102 119 #define CFG_DDR_TIMING_0 0x00220802 120 #define CFG_DDR_TIMING_1 0x38357322 121 #define CFG_DDR_TIMING_2 0x2f9048c8 122 #define CFG_DDR_TIMING_3 0x00000000 123 #define CFG_DDR_CLK_CNTL 0x02000000 124 #define CFG_DDR_MODE 0x47d00432 125 #define CFG_DDR_MODE2 0x8000c000 126 #define CFG_DDR_INTERVAL 0x03cf0080 127 #define CFG_DDR_SDRAM_CFG 0x43000000 128 #define CFG_DDR_SDRAM_CFG2 0x00401000 129 #else 130 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 131 #define CFG_DDR_TIMING_1 0x36332321 132 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 133 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 134 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 135 136 #if defined(CONFIG_DDR_32BIT) 137 /* set burst length to 8 for 32-bit data path */ 138 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 139 #else 140 /* the default burst length is 4 - for 64-bit data path */ 141 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 142 #endif 143 #endif 144 #endif 145 146 /* 147 * SDRAM on the Local Bus 148 */ 149 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 150 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 151 152 /* 153 * FLASH on the Local Bus 154 */ 155 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 156 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 157 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 158 #define CFG_FLASH_SIZE 32 /* max flash size in MB */ 159 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 160 161 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 162 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 163 BR_V) /* valid */ 164 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 165 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 166 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 167 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 168 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ 169 170 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 171 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ 172 173 #undef CFG_FLASH_CHECKSUM 174 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 175 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 176 177 #define CFG_MID_FLASH_JUMP 0x7F000000 178 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 179 180 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 181 #define CFG_RAMBOOT 182 #else 183 #undef CFG_RAMBOOT 184 #endif 185 186 /* 187 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 188 */ 189 #define CFG_BCSR 0xE2400000 190 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 191 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 192 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 193 #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 194 195 #define CONFIG_L1_INIT_RAM 196 #define CFG_INIT_RAM_LOCK 1 197 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 198 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 199 200 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 201 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 202 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 203 204 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 205 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 206 207 /* 208 * Local Bus LCRR and LBCR regs 209 * LCRR: DLL bypass, Clock divider is 4 210 * External Local Bus rate is 211 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 212 */ 213 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 214 #define CFG_LBC_LBCR 0x00000000 215 216 /* 217 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 218 * if board has SRDAM on local bus, you can define CFG_LB_SDRAM 219 */ 220 #undef CFG_LB_SDRAM 221 222 #ifdef CFG_LB_SDRAM 223 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 224 /* 225 * Base Register 2 and Option Register 2 configure SDRAM. 226 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 227 * 228 * For BR2, need: 229 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 230 * port-size = 32-bits = BR2[19:20] = 11 231 * no parity checking = BR2[21:22] = 00 232 * SDRAM for MSEL = BR2[24:26] = 011 233 * Valid = BR[31] = 1 234 * 235 * 0 4 8 12 16 20 24 28 236 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 237 * 238 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 239 * FIXME: the top 17 bits of BR2. 240 */ 241 242 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 243 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 244 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 245 246 /* 247 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 248 * 249 * For OR2, need: 250 * 64MB mask for AM, OR2[0:7] = 1111 1100 251 * XAM, OR2[17:18] = 11 252 * 9 columns OR2[19-21] = 010 253 * 13 rows OR2[23-25] = 100 254 * EAD set for extra time OR[31] = 1 255 * 256 * 0 4 8 12 16 20 24 28 257 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 258 */ 259 260 #define CFG_OR2_PRELIM 0xFC006901 261 262 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 263 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 264 265 /* 266 * LSDMR masks 267 */ 268 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 269 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 270 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 271 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 272 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 273 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 274 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 275 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 276 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 277 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 278 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 279 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 280 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 281 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 282 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 283 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 284 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 285 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 286 287 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 288 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 289 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 290 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 291 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 292 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 293 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 294 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 295 296 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 297 | CFG_LBC_LSDMR_BSMA1516 \ 298 | CFG_LBC_LSDMR_RFCR8 \ 299 | CFG_LBC_LSDMR_PRETOACT6 \ 300 | CFG_LBC_LSDMR_ACTTORW3 \ 301 | CFG_LBC_LSDMR_BL8 \ 302 | CFG_LBC_LSDMR_WRC3 \ 303 | CFG_LBC_LSDMR_CL3 \ 304 ) 305 306 /* 307 * SDRAM Controller configuration sequence. 308 */ 309 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 310 | CFG_LBC_LSDMR_OP_PCHALL) 311 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 312 | CFG_LBC_LSDMR_OP_ARFRSH) 313 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 314 | CFG_LBC_LSDMR_OP_ARFRSH) 315 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 316 | CFG_LBC_LSDMR_OP_MRW) 317 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 318 | CFG_LBC_LSDMR_OP_NORMAL) 319 #endif 320 321 /* 322 * Serial Port 323 */ 324 #define CONFIG_CONS_INDEX 1 325 #undef CONFIG_SERIAL_SOFTWARE_FIFO 326 #define CFG_NS16550 327 #define CFG_NS16550_SERIAL 328 #define CFG_NS16550_REG_SIZE 1 329 #define CFG_NS16550_CLK get_bus_freq(0) 330 331 #define CFG_BAUDRATE_TABLE \ 332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 333 334 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 335 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 336 337 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 338 /* Use the HUSH parser */ 339 #define CFG_HUSH_PARSER 340 #ifdef CFG_HUSH_PARSER 341 #define CFG_PROMPT_HUSH_PS2 "> " 342 #endif 343 344 /* pass open firmware flat tree */ 345 #define CONFIG_OF_LIBFDT 1 346 #define CONFIG_OF_BOARD_SETUP 1 347 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 348 349 /* I2C */ 350 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 351 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 352 #define CONFIG_FSL_I2C 353 #define CONFIG_I2C_MULTI_BUS 354 #define CONFIG_I2C_CMD_TREE 355 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 356 #define CFG_I2C_SLAVE 0x7F 357 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 358 #define CFG_I2C_OFFSET 0x3000 359 #define CFG_I2C2_OFFSET 0x3100 360 361 /* SPI */ 362 #define CONFIG_MPC8XXX_SPI 363 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 364 365 /* GPIOs. Used as SPI chip selects */ 366 #define CFG_GPIO1_PRELIM 367 #define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 368 #define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 369 370 /* TSEC */ 371 #define CFG_TSEC1_OFFSET 0x24000 372 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 373 #define CFG_TSEC2_OFFSET 0x25000 374 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 375 376 /* USB */ 377 #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 378 379 /* 380 * General PCI 381 * Addresses are mapped 1-1. 382 */ 383 #define CFG_PCI1_MEM_BASE 0x80000000 384 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 385 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 386 #define CFG_PCI1_MMIO_BASE 0x90000000 387 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 388 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 389 #define CFG_PCI1_IO_BASE 0x00000000 390 #define CFG_PCI1_IO_PHYS 0xE2000000 391 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 392 393 #define CFG_PCI2_MEM_BASE 0xA0000000 394 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 395 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 396 #define CFG_PCI2_MMIO_BASE 0xB0000000 397 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 398 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 399 #define CFG_PCI2_IO_BASE 0x00000000 400 #define CFG_PCI2_IO_PHYS 0xE2100000 401 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 402 403 #if defined(CONFIG_PCI) 404 405 #define PCI_ONE_PCI1 406 #if defined(PCI_64BIT) 407 #undef PCI_ALL_PCI1 408 #undef PCI_TWO_PCI1 409 #undef PCI_ONE_PCI1 410 #endif 411 412 #define CONFIG_NET_MULTI 413 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 414 #define CONFIG_83XX_GENERIC_PCI 415 #define CONFIG_83XX_PCI_STREAMING 416 417 #undef CONFIG_EEPRO100 418 #undef CONFIG_TULIP 419 420 #if !defined(CONFIG_PCI_PNP) 421 #define PCI_ENET0_IOADDR 0xFIXME 422 #define PCI_ENET0_MEMADDR 0xFIXME 423 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 424 #endif 425 426 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 427 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 428 429 #endif /* CONFIG_PCI */ 430 431 /* 432 * TSEC configuration 433 */ 434 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 435 436 #if defined(CONFIG_TSEC_ENET) 437 #ifndef CONFIG_NET_MULTI 438 #define CONFIG_NET_MULTI 1 439 #endif 440 441 #define CONFIG_GMII 1 /* MII PHY management */ 442 #define CONFIG_TSEC1 1 443 #define CONFIG_TSEC1_NAME "TSEC0" 444 #define CONFIG_TSEC2 1 445 #define CONFIG_TSEC2_NAME "TSEC1" 446 #define TSEC1_PHY_ADDR 0 447 #define TSEC2_PHY_ADDR 1 448 #define TSEC1_PHYIDX 0 449 #define TSEC2_PHYIDX 0 450 #define TSEC1_FLAGS TSEC_GIGABIT 451 #define TSEC2_FLAGS TSEC_GIGABIT 452 453 /* Options are: TSEC[0-1] */ 454 #define CONFIG_ETHPRIME "TSEC0" 455 456 #endif /* CONFIG_TSEC_ENET */ 457 458 /* 459 * Configure on-board RTC 460 */ 461 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 462 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 463 464 /* 465 * Environment 466 */ 467 #ifndef CFG_RAMBOOT 468 #define CFG_ENV_IS_IN_FLASH 1 469 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 470 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 471 #define CFG_ENV_SIZE 0x2000 472 473 /* Address and size of Redundant Environment Sector */ 474 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 475 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 476 477 #else 478 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 479 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 480 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 481 #define CFG_ENV_SIZE 0x2000 482 #endif 483 484 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 485 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 486 487 488 /* 489 * BOOTP options 490 */ 491 #define CONFIG_BOOTP_BOOTFILESIZE 492 #define CONFIG_BOOTP_BOOTPATH 493 #define CONFIG_BOOTP_GATEWAY 494 #define CONFIG_BOOTP_HOSTNAME 495 496 497 /* 498 * Command line configuration. 499 */ 500 #include <config_cmd_default.h> 501 502 #define CONFIG_CMD_PING 503 #define CONFIG_CMD_I2C 504 #define CONFIG_CMD_DATE 505 #define CONFIG_CMD_MII 506 507 #if defined(CONFIG_PCI) 508 #define CONFIG_CMD_PCI 509 #endif 510 511 #if defined(CFG_RAMBOOT) 512 #undef CONFIG_CMD_ENV 513 #undef CONFIG_CMD_LOADS 514 #endif 515 516 517 #undef CONFIG_WATCHDOG /* watchdog disabled */ 518 519 /* 520 * Miscellaneous configurable options 521 */ 522 #define CFG_LONGHELP /* undef to save memory */ 523 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 524 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 528 #else 529 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 530 #endif 531 532 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 533 #define CFG_MAXARGS 16 /* max number of command args */ 534 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 535 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 536 537 /* 538 * For booting Linux, the board info and command line data 539 * have to be in the first 8 MB of memory, since this is 540 * the maximum mapped by the Linux kernel during initialization. 541 */ 542 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 543 544 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 545 546 #if 1 /*528/264*/ 547 #define CFG_HRCW_LOW (\ 548 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 549 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 550 HRCWL_CSB_TO_CLKIN |\ 551 HRCWL_VCO_1X2 |\ 552 HRCWL_CORE_TO_CSB_2X1) 553 #elif 0 /*396/132*/ 554 #define CFG_HRCW_LOW (\ 555 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 556 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 557 HRCWL_CSB_TO_CLKIN |\ 558 HRCWL_VCO_1X4 |\ 559 HRCWL_CORE_TO_CSB_3X1) 560 #elif 0 /*264/132*/ 561 #define CFG_HRCW_LOW (\ 562 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 563 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 564 HRCWL_CSB_TO_CLKIN |\ 565 HRCWL_VCO_1X4 |\ 566 HRCWL_CORE_TO_CSB_2X1) 567 #elif 0 /*132/132*/ 568 #define CFG_HRCW_LOW (\ 569 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 570 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 571 HRCWL_CSB_TO_CLKIN |\ 572 HRCWL_VCO_1X4 |\ 573 HRCWL_CORE_TO_CSB_1X1) 574 #elif 0 /*264/264 */ 575 #define CFG_HRCW_LOW (\ 576 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 577 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 578 HRCWL_CSB_TO_CLKIN |\ 579 HRCWL_VCO_1X4 |\ 580 HRCWL_CORE_TO_CSB_1X1) 581 #endif 582 583 #ifdef CONFIG_PCISLAVE 584 #define CFG_HRCW_HIGH (\ 585 HRCWH_PCI_AGENT |\ 586 HRCWH_64_BIT_PCI |\ 587 HRCWH_PCI1_ARBITER_DISABLE |\ 588 HRCWH_PCI2_ARBITER_DISABLE |\ 589 HRCWH_CORE_ENABLE |\ 590 HRCWH_FROM_0X00000100 |\ 591 HRCWH_BOOTSEQ_DISABLE |\ 592 HRCWH_SW_WATCHDOG_DISABLE |\ 593 HRCWH_ROM_LOC_LOCAL_16BIT |\ 594 HRCWH_TSEC1M_IN_GMII |\ 595 HRCWH_TSEC2M_IN_GMII ) 596 #else 597 #if defined(PCI_64BIT) 598 #define CFG_HRCW_HIGH (\ 599 HRCWH_PCI_HOST |\ 600 HRCWH_64_BIT_PCI |\ 601 HRCWH_PCI1_ARBITER_ENABLE |\ 602 HRCWH_PCI2_ARBITER_DISABLE |\ 603 HRCWH_CORE_ENABLE |\ 604 HRCWH_FROM_0X00000100 |\ 605 HRCWH_BOOTSEQ_DISABLE |\ 606 HRCWH_SW_WATCHDOG_DISABLE |\ 607 HRCWH_ROM_LOC_LOCAL_16BIT |\ 608 HRCWH_TSEC1M_IN_GMII |\ 609 HRCWH_TSEC2M_IN_GMII ) 610 #else 611 #define CFG_HRCW_HIGH (\ 612 HRCWH_PCI_HOST |\ 613 HRCWH_32_BIT_PCI |\ 614 HRCWH_PCI1_ARBITER_ENABLE |\ 615 HRCWH_PCI2_ARBITER_ENABLE |\ 616 HRCWH_CORE_ENABLE |\ 617 HRCWH_FROM_0X00000100 |\ 618 HRCWH_BOOTSEQ_DISABLE |\ 619 HRCWH_SW_WATCHDOG_DISABLE |\ 620 HRCWH_ROM_LOC_LOCAL_16BIT |\ 621 HRCWH_TSEC1M_IN_GMII |\ 622 HRCWH_TSEC2M_IN_GMII ) 623 #endif /* PCI_64BIT */ 624 #endif /* CONFIG_PCISLAVE */ 625 626 /* 627 * System performance 628 */ 629 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 630 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 631 #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 632 #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 633 #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 634 #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 635 636 /* System IO Config */ 637 #define CFG_SICRH SICRH_TSOBI1 638 #define CFG_SICRL SICRL_LDP_A 639 640 #define CFG_HID0_INIT 0x000000000 641 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 642 643 /* #define CFG_HID0_FINAL (\ 644 HID0_ENABLE_INSTRUCTION_CACHE |\ 645 HID0_ENABLE_M_BIT |\ 646 HID0_ENABLE_ADDRESS_BROADCAST ) */ 647 648 649 #define CFG_HID2 HID2_HBE 650 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 651 652 /* DDR @ 0x00000000 */ 653 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 654 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 655 656 /* PCI @ 0x80000000 */ 657 #ifdef CONFIG_PCI 658 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 659 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 660 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 661 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 662 #else 663 #define CFG_IBAT1L (0) 664 #define CFG_IBAT1U (0) 665 #define CFG_IBAT2L (0) 666 #define CFG_IBAT2U (0) 667 #endif 668 669 #ifdef CONFIG_MPC83XX_PCI2 670 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 671 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 672 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 673 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 674 #else 675 #define CFG_IBAT3L (0) 676 #define CFG_IBAT3U (0) 677 #define CFG_IBAT4L (0) 678 #define CFG_IBAT4U (0) 679 #endif 680 681 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 682 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 683 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 684 685 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 686 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 687 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 688 689 #define CFG_IBAT7L (0) 690 #define CFG_IBAT7U (0) 691 692 #define CFG_DBAT0L CFG_IBAT0L 693 #define CFG_DBAT0U CFG_IBAT0U 694 #define CFG_DBAT1L CFG_IBAT1L 695 #define CFG_DBAT1U CFG_IBAT1U 696 #define CFG_DBAT2L CFG_IBAT2L 697 #define CFG_DBAT2U CFG_IBAT2U 698 #define CFG_DBAT3L CFG_IBAT3L 699 #define CFG_DBAT3U CFG_IBAT3U 700 #define CFG_DBAT4L CFG_IBAT4L 701 #define CFG_DBAT4U CFG_IBAT4U 702 #define CFG_DBAT5L CFG_IBAT5L 703 #define CFG_DBAT5U CFG_IBAT5U 704 #define CFG_DBAT6L CFG_IBAT6L 705 #define CFG_DBAT6U CFG_IBAT6U 706 #define CFG_DBAT7L CFG_IBAT7L 707 #define CFG_DBAT7U CFG_IBAT7U 708 709 /* 710 * Internal Definitions 711 * 712 * Boot Flags 713 */ 714 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 715 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 716 717 #if defined(CONFIG_CMD_KGDB) 718 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 719 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 720 #endif 721 722 /* 723 * Environment Configuration 724 */ 725 #define CONFIG_ENV_OVERWRITE 726 727 #if defined(CONFIG_TSEC_ENET) 728 #define CONFIG_ETHADDR 00:04:9f:ef:23:33 729 #define CONFIG_HAS_ETH1 730 #define CONFIG_HAS_ETH0 731 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 732 #endif 733 734 #define CONFIG_IPADDR 192.168.1.253 735 736 #define CONFIG_HOSTNAME mpc8349emds 737 #define CONFIG_ROOTPATH /nfsroot/rootfs 738 #define CONFIG_BOOTFILE uImage 739 740 #define CONFIG_SERVERIP 192.168.1.1 741 #define CONFIG_GATEWAYIP 192.168.1.1 742 #define CONFIG_NETMASK 255.255.255.0 743 744 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 745 746 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 747 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 748 749 #define CONFIG_BAUDRATE 115200 750 751 #define CONFIG_PREBOOT "echo;" \ 752 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 753 "echo" 754 755 #define CONFIG_EXTRA_ENV_SETTINGS \ 756 "netdev=eth0\0" \ 757 "hostname=mpc8349emds\0" \ 758 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 759 "nfsroot=${serverip}:${rootpath}\0" \ 760 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 761 "addip=setenv bootargs ${bootargs} " \ 762 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 763 ":${hostname}:${netdev}:off panic=1\0" \ 764 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 765 "flash_nfs=run nfsargs addip addtty;" \ 766 "bootm ${kernel_addr}\0" \ 767 "flash_self=run ramargs addip addtty;" \ 768 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 769 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 770 "bootm\0" \ 771 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 772 "update=protect off fe000000 fe03ffff; " \ 773 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 774 "upd=run load update\0" \ 775 "fdtaddr=400000\0" \ 776 "fdtfile=mpc8349emds.dtb\0" \ 777 "" 778 779 #define CONFIG_NFSBOOTCOMMAND \ 780 "setenv bootargs root=/dev/nfs rw " \ 781 "nfsroot=$serverip:$rootpath " \ 782 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 783 "console=$consoledev,$baudrate $othbootargs;" \ 784 "tftp $loadaddr $bootfile;" \ 785 "tftp $fdtaddr $fdtfile;" \ 786 "bootm $loadaddr - $fdtaddr" 787 788 #define CONFIG_RAMBOOTCOMMAND \ 789 "setenv bootargs root=/dev/ram rw " \ 790 "console=$consoledev,$baudrate $othbootargs;" \ 791 "tftp $ramdiskaddr $ramdiskfile;" \ 792 "tftp $loadaddr $bootfile;" \ 793 "tftp $fdtaddr $fdtfile;" \ 794 "bootm $loadaddr $ramdiskaddr $fdtaddr" 795 796 #define CONFIG_BOOTCOMMAND "run flash_self" 797 798 #endif /* __CONFIG_H */ 799