1 /* 2 * (C) Copyright 2006-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * mpc8349emds board configuration file 10 * 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 /* E300 Family */ 20 #define CONFIG_MPC834x 1 /* MPC834x family */ 21 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 22 23 #define CONFIG_PCI_66M 24 #ifdef CONFIG_PCI_66M 25 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 26 #else 27 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 28 #endif 29 30 #ifdef CONFIG_PCISLAVE 31 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 32 #endif /* CONFIG_PCISLAVE */ 33 34 #ifndef CONFIG_SYS_CLK_FREQ 35 #ifdef CONFIG_PCI_66M 36 #define CONFIG_SYS_CLK_FREQ 66000000 37 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 38 #else 39 #define CONFIG_SYS_CLK_FREQ 33000000 40 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 41 #endif 42 #endif 43 44 #define CONFIG_SYS_IMMR 0xE0000000 45 46 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 47 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 48 #define CONFIG_SYS_MEMTEST_END 0x00100000 49 50 /* 51 * DDR Setup 52 */ 53 #define CONFIG_DDR_ECC /* support DDR ECC function */ 54 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 55 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 56 57 /* 58 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver 59 * unselect it to use old spd_sdram.c 60 */ 61 #define CONFIG_SYS_SPD_BUS_NUM 0 62 #define SPD_EEPROM_ADDRESS1 0x52 63 #define SPD_EEPROM_ADDRESS2 0x51 64 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 65 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 67 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 68 69 /* 70 * 32-bit data path mode. 71 * 72 * Please note that using this mode for devices with the real density of 64-bit 73 * effectively reduces the amount of available memory due to the effect of 74 * wrapping around while translating address to row/columns, for example in the 75 * 256MB module the upper 128MB get aliased with contents of the lower 76 * 128MB); normally this define should be used for devices with real 32-bit 77 * data path. 78 */ 79 #undef CONFIG_DDR_32BIT 80 81 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 82 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 83 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 84 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 85 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 86 #undef CONFIG_DDR_2T_TIMING 87 88 /* 89 * DDRCDR - DDR Control Driver Register 90 */ 91 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 92 93 #if defined(CONFIG_SPD_EEPROM) 94 /* 95 * Determine DDR configuration from I2C interface. 96 */ 97 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 98 #else 99 /* 100 * Manually set up DDR parameters 101 */ 102 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 103 #if defined(CONFIG_DDR_II) 104 #define CONFIG_SYS_DDRCDR 0x80080001 105 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 106 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 107 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 108 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 109 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 110 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 111 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 112 #define CONFIG_SYS_DDR_MODE 0x47d00432 113 #define CONFIG_SYS_DDR_MODE2 0x8000c000 114 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 115 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 116 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 117 #else 118 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 119 | CSCONFIG_ROW_BIT_13 \ 120 | CSCONFIG_COL_BIT_10) 121 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 122 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 123 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 124 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 125 126 #if defined(CONFIG_DDR_32BIT) 127 /* set burst length to 8 for 32-bit data path */ 128 /* DLL,normal,seq,4/2.5, 8 burst len */ 129 #define CONFIG_SYS_DDR_MODE 0x00000023 130 #else 131 /* the default burst length is 4 - for 64-bit data path */ 132 /* DLL,normal,seq,4/2.5, 4 burst len */ 133 #define CONFIG_SYS_DDR_MODE 0x00000022 134 #endif 135 #endif 136 #endif 137 138 /* 139 * SDRAM on the Local Bus 140 */ 141 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 142 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 143 144 /* 145 * FLASH on the Local Bus 146 */ 147 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 148 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 149 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 150 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 151 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 152 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 153 154 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 155 | BR_PS_16 /* 16 bit port */ \ 156 | BR_MS_GPCM /* MSEL = GPCM */ \ 157 | BR_V) /* valid */ 158 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 159 | OR_UPM_XAM \ 160 | OR_GPCM_CSNT \ 161 | OR_GPCM_ACS_DIV2 \ 162 | OR_GPCM_XACS \ 163 | OR_GPCM_SCY_15 \ 164 | OR_GPCM_TRLX_SET \ 165 | OR_GPCM_EHTR_SET \ 166 | OR_GPCM_EAD) 167 168 /* window base at flash base */ 169 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 170 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 171 172 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 173 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 174 175 #undef CONFIG_SYS_FLASH_CHECKSUM 176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 178 179 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 180 181 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 182 #define CONFIG_SYS_RAMBOOT 183 #else 184 #undef CONFIG_SYS_RAMBOOT 185 #endif 186 187 /* 188 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 189 */ 190 #define CONFIG_SYS_BCSR 0xE2400000 191 /* Access window base at BCSR base */ 192 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 193 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 194 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 195 | BR_PS_8 \ 196 | BR_MS_GPCM \ 197 | BR_V) 198 /* 0x00000801 */ 199 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 200 | OR_GPCM_XAM \ 201 | OR_GPCM_CSNT \ 202 | OR_GPCM_SCY_15 \ 203 | OR_GPCM_TRLX_CLEAR \ 204 | OR_GPCM_EHTR_CLEAR) 205 /* 0xFFFFE8F0 */ 206 207 #define CONFIG_SYS_INIT_RAM_LOCK 1 208 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 209 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 210 211 #define CONFIG_SYS_GBL_DATA_OFFSET \ 212 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 213 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 214 215 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 216 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 217 218 /* 219 * Local Bus LCRR and LBCR regs 220 * LCRR: DLL bypass, Clock divider is 4 221 * External Local Bus rate is 222 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 223 */ 224 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 225 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 226 #define CONFIG_SYS_LBC_LBCR 0x00000000 227 228 /* 229 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 230 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 231 */ 232 #undef CONFIG_SYS_LB_SDRAM 233 234 #ifdef CONFIG_SYS_LB_SDRAM 235 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 236 /* 237 * Base Register 2 and Option Register 2 configure SDRAM. 238 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 239 * 240 * For BR2, need: 241 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 242 * port-size = 32-bits = BR2[19:20] = 11 243 * no parity checking = BR2[21:22] = 00 244 * SDRAM for MSEL = BR2[24:26] = 011 245 * Valid = BR[31] = 1 246 * 247 * 0 4 8 12 16 20 24 28 248 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 249 */ 250 251 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 252 | BR_PS_32 /* 32-bit port */ \ 253 | BR_MS_SDRAM /* MSEL = SDRAM */ \ 254 | BR_V) /* Valid */ 255 /* 0xF0001861 */ 256 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 257 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 258 259 /* 260 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 261 * 262 * For OR2, need: 263 * 64MB mask for AM, OR2[0:7] = 1111 1100 264 * XAM, OR2[17:18] = 11 265 * 9 columns OR2[19-21] = 010 266 * 13 rows OR2[23-25] = 100 267 * EAD set for extra time OR[31] = 1 268 * 269 * 0 4 8 12 16 20 24 28 270 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 271 */ 272 273 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ 274 | OR_SDRAM_XAM \ 275 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 276 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 277 | OR_SDRAM_EAD) 278 /* 0xFC006901 */ 279 280 /* LB sdram refresh timer, about 6us */ 281 #define CONFIG_SYS_LBC_LSRT 0x32000000 282 /* LB refresh timer prescal, 266MHz/32 */ 283 #define CONFIG_SYS_LBC_MRTPR 0x20000000 284 285 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 286 | LSDMR_BSMA1516 \ 287 | LSDMR_RFCR8 \ 288 | LSDMR_PRETOACT6 \ 289 | LSDMR_ACTTORW3 \ 290 | LSDMR_BL8 \ 291 | LSDMR_WRC3 \ 292 | LSDMR_CL3) 293 294 /* 295 * SDRAM Controller configuration sequence. 296 */ 297 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 298 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 299 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 300 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 301 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 302 #endif 303 304 /* 305 * Serial Port 306 */ 307 #define CONFIG_SYS_NS16550_SERIAL 308 #define CONFIG_SYS_NS16550_REG_SIZE 1 309 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 310 311 #define CONFIG_SYS_BAUDRATE_TABLE \ 312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 313 314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 316 317 /* I2C */ 318 #define CONFIG_SYS_I2C 319 #define CONFIG_SYS_I2C_FSL 320 #define CONFIG_SYS_FSL_I2C_SPEED 400000 321 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 322 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 323 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 324 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 325 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 326 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 327 328 /* SPI */ 329 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 330 331 /* GPIOs. Used as SPI chip selects */ 332 #define CONFIG_SYS_GPIO1_PRELIM 333 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 334 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 335 336 /* TSEC */ 337 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 338 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 339 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 340 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 341 342 /* USB */ 343 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 344 345 /* 346 * General PCI 347 * Addresses are mapped 1-1. 348 */ 349 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 350 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 351 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 352 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 353 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 354 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 355 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 356 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 357 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 358 359 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 360 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 361 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 362 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 363 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 364 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 365 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 366 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 367 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 368 369 #if defined(CONFIG_PCI) 370 371 #define PCI_ONE_PCI1 372 #if defined(PCI_64BIT) 373 #undef PCI_ALL_PCI1 374 #undef PCI_TWO_PCI1 375 #undef PCI_ONE_PCI1 376 #endif 377 378 #define CONFIG_83XX_PCI_STREAMING 379 380 #undef CONFIG_EEPRO100 381 #undef CONFIG_TULIP 382 383 #if !defined(CONFIG_PCI_PNP) 384 #define PCI_ENET0_IOADDR 0xFIXME 385 #define PCI_ENET0_MEMADDR 0xFIXME 386 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 387 #endif 388 389 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 390 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 391 392 #endif /* CONFIG_PCI */ 393 394 /* 395 * TSEC configuration 396 */ 397 398 #if defined(CONFIG_TSEC_ENET) 399 400 #define CONFIG_GMII 1 /* MII PHY management */ 401 #define CONFIG_TSEC1 1 402 #define CONFIG_TSEC1_NAME "TSEC0" 403 #define CONFIG_TSEC2 1 404 #define CONFIG_TSEC2_NAME "TSEC1" 405 #define TSEC1_PHY_ADDR 0 406 #define TSEC2_PHY_ADDR 1 407 #define TSEC1_PHYIDX 0 408 #define TSEC2_PHYIDX 0 409 #define TSEC1_FLAGS TSEC_GIGABIT 410 #define TSEC2_FLAGS TSEC_GIGABIT 411 412 /* Options are: TSEC[0-1] */ 413 #define CONFIG_ETHPRIME "TSEC0" 414 415 #endif /* CONFIG_TSEC_ENET */ 416 417 /* 418 * Configure on-board RTC 419 */ 420 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 421 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 422 423 /* 424 * Environment 425 */ 426 #ifndef CONFIG_SYS_RAMBOOT 427 #define CONFIG_ENV_ADDR \ 428 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 429 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 430 #define CONFIG_ENV_SIZE 0x2000 431 432 /* Address and size of Redundant Environment Sector */ 433 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 434 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 435 436 #else 437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 438 #define CONFIG_ENV_SIZE 0x2000 439 #endif 440 441 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 442 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 443 444 /* 445 * BOOTP options 446 */ 447 #define CONFIG_BOOTP_BOOTFILESIZE 448 449 /* 450 * Command line configuration. 451 */ 452 453 #undef CONFIG_WATCHDOG /* watchdog disabled */ 454 455 /* 456 * Miscellaneous configurable options 457 */ 458 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 459 460 /* 461 * For booting Linux, the board info and command line data 462 * have to be in the first 256 MB of memory, since this is 463 * the maximum mapped by the Linux kernel during initialization. 464 */ 465 /* Initial Memory map for Linux*/ 466 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 467 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 468 469 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 470 471 #if 1 /*528/264*/ 472 #define CONFIG_SYS_HRCW_LOW (\ 473 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 474 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 475 HRCWL_CSB_TO_CLKIN |\ 476 HRCWL_VCO_1X2 |\ 477 HRCWL_CORE_TO_CSB_2X1) 478 #elif 0 /*396/132*/ 479 #define CONFIG_SYS_HRCW_LOW (\ 480 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 481 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 482 HRCWL_CSB_TO_CLKIN |\ 483 HRCWL_VCO_1X4 |\ 484 HRCWL_CORE_TO_CSB_3X1) 485 #elif 0 /*264/132*/ 486 #define CONFIG_SYS_HRCW_LOW (\ 487 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 488 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 489 HRCWL_CSB_TO_CLKIN |\ 490 HRCWL_VCO_1X4 |\ 491 HRCWL_CORE_TO_CSB_2X1) 492 #elif 0 /*132/132*/ 493 #define CONFIG_SYS_HRCW_LOW (\ 494 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 495 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 496 HRCWL_CSB_TO_CLKIN |\ 497 HRCWL_VCO_1X4 |\ 498 HRCWL_CORE_TO_CSB_1X1) 499 #elif 0 /*264/264 */ 500 #define CONFIG_SYS_HRCW_LOW (\ 501 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 502 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 503 HRCWL_CSB_TO_CLKIN |\ 504 HRCWL_VCO_1X4 |\ 505 HRCWL_CORE_TO_CSB_1X1) 506 #endif 507 508 #ifdef CONFIG_PCISLAVE 509 #define CONFIG_SYS_HRCW_HIGH (\ 510 HRCWH_PCI_AGENT |\ 511 HRCWH_64_BIT_PCI |\ 512 HRCWH_PCI1_ARBITER_DISABLE |\ 513 HRCWH_PCI2_ARBITER_DISABLE |\ 514 HRCWH_CORE_ENABLE |\ 515 HRCWH_FROM_0X00000100 |\ 516 HRCWH_BOOTSEQ_DISABLE |\ 517 HRCWH_SW_WATCHDOG_DISABLE |\ 518 HRCWH_ROM_LOC_LOCAL_16BIT |\ 519 HRCWH_TSEC1M_IN_GMII |\ 520 HRCWH_TSEC2M_IN_GMII) 521 #else 522 #if defined(PCI_64BIT) 523 #define CONFIG_SYS_HRCW_HIGH (\ 524 HRCWH_PCI_HOST |\ 525 HRCWH_64_BIT_PCI |\ 526 HRCWH_PCI1_ARBITER_ENABLE |\ 527 HRCWH_PCI2_ARBITER_DISABLE |\ 528 HRCWH_CORE_ENABLE |\ 529 HRCWH_FROM_0X00000100 |\ 530 HRCWH_BOOTSEQ_DISABLE |\ 531 HRCWH_SW_WATCHDOG_DISABLE |\ 532 HRCWH_ROM_LOC_LOCAL_16BIT |\ 533 HRCWH_TSEC1M_IN_GMII |\ 534 HRCWH_TSEC2M_IN_GMII) 535 #else 536 #define CONFIG_SYS_HRCW_HIGH (\ 537 HRCWH_PCI_HOST |\ 538 HRCWH_32_BIT_PCI |\ 539 HRCWH_PCI1_ARBITER_ENABLE |\ 540 HRCWH_PCI2_ARBITER_ENABLE |\ 541 HRCWH_CORE_ENABLE |\ 542 HRCWH_FROM_0X00000100 |\ 543 HRCWH_BOOTSEQ_DISABLE |\ 544 HRCWH_SW_WATCHDOG_DISABLE |\ 545 HRCWH_ROM_LOC_LOCAL_16BIT |\ 546 HRCWH_TSEC1M_IN_GMII |\ 547 HRCWH_TSEC2M_IN_GMII) 548 #endif /* PCI_64BIT */ 549 #endif /* CONFIG_PCISLAVE */ 550 551 /* 552 * System performance 553 */ 554 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 555 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 556 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 557 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 558 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 559 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 560 561 /* System IO Config */ 562 #define CONFIG_SYS_SICRH 0 563 #define CONFIG_SYS_SICRL SICRL_LDP_A 564 565 #define CONFIG_SYS_HID0_INIT 0x000000000 566 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 567 | HID0_ENABLE_INSTRUCTION_CACHE) 568 569 /* #define CONFIG_SYS_HID0_FINAL (\ 570 HID0_ENABLE_INSTRUCTION_CACHE |\ 571 HID0_ENABLE_M_BIT |\ 572 HID0_ENABLE_ADDRESS_BROADCAST) */ 573 574 #define CONFIG_SYS_HID2 HID2_HBE 575 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 576 577 /* DDR @ 0x00000000 */ 578 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 579 | BATL_PP_RW \ 580 | BATL_MEMCOHERENCE) 581 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 582 | BATU_BL_256M \ 583 | BATU_VS \ 584 | BATU_VP) 585 586 /* PCI @ 0x80000000 */ 587 #ifdef CONFIG_PCI 588 #define CONFIG_PCI_INDIRECT_BRIDGE 589 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 590 | BATL_PP_RW \ 591 | BATL_MEMCOHERENCE) 592 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 593 | BATU_BL_256M \ 594 | BATU_VS \ 595 | BATU_VP) 596 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 597 | BATL_PP_RW \ 598 | BATL_CACHEINHIBIT \ 599 | BATL_GUARDEDSTORAGE) 600 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 601 | BATU_BL_256M \ 602 | BATU_VS \ 603 | BATU_VP) 604 #else 605 #define CONFIG_SYS_IBAT1L (0) 606 #define CONFIG_SYS_IBAT1U (0) 607 #define CONFIG_SYS_IBAT2L (0) 608 #define CONFIG_SYS_IBAT2U (0) 609 #endif 610 611 #ifdef CONFIG_MPC83XX_PCI2 612 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 613 | BATL_PP_RW \ 614 | BATL_MEMCOHERENCE) 615 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 616 | BATU_BL_256M \ 617 | BATU_VS \ 618 | BATU_VP) 619 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 620 | BATL_PP_RW \ 621 | BATL_CACHEINHIBIT \ 622 | BATL_GUARDEDSTORAGE) 623 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 624 | BATU_BL_256M \ 625 | BATU_VS \ 626 | BATU_VP) 627 #else 628 #define CONFIG_SYS_IBAT3L (0) 629 #define CONFIG_SYS_IBAT3U (0) 630 #define CONFIG_SYS_IBAT4L (0) 631 #define CONFIG_SYS_IBAT4U (0) 632 #endif 633 634 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 635 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 636 | BATL_PP_RW \ 637 | BATL_CACHEINHIBIT \ 638 | BATL_GUARDEDSTORAGE) 639 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 640 | BATU_BL_256M \ 641 | BATU_VS \ 642 | BATU_VP) 643 644 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 645 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 646 | BATL_PP_RW \ 647 | BATL_MEMCOHERENCE \ 648 | BATL_GUARDEDSTORAGE) 649 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 650 | BATU_BL_256M \ 651 | BATU_VS \ 652 | BATU_VP) 653 654 #define CONFIG_SYS_IBAT7L (0) 655 #define CONFIG_SYS_IBAT7U (0) 656 657 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 658 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 659 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 660 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 661 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 662 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 663 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 664 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 665 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 666 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 667 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 668 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 669 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 670 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 671 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 672 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 673 674 #if defined(CONFIG_CMD_KGDB) 675 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 676 #endif 677 678 /* 679 * Environment Configuration 680 */ 681 #define CONFIG_ENV_OVERWRITE 682 683 #if defined(CONFIG_TSEC_ENET) 684 #define CONFIG_HAS_ETH1 685 #define CONFIG_HAS_ETH0 686 #endif 687 688 #define CONFIG_HOSTNAME "mpc8349emds" 689 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 690 #define CONFIG_BOOTFILE "uImage" 691 692 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 693 694 #define CONFIG_PREBOOT "echo;" \ 695 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 696 "echo" 697 698 #define CONFIG_EXTRA_ENV_SETTINGS \ 699 "netdev=eth0\0" \ 700 "hostname=mpc8349emds\0" \ 701 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 702 "nfsroot=${serverip}:${rootpath}\0" \ 703 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 704 "addip=setenv bootargs ${bootargs} " \ 705 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 706 ":${hostname}:${netdev}:off panic=1\0" \ 707 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 708 "flash_nfs=run nfsargs addip addtty;" \ 709 "bootm ${kernel_addr}\0" \ 710 "flash_self=run ramargs addip addtty;" \ 711 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 712 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 713 "bootm\0" \ 714 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 715 "update=protect off fe000000 fe03ffff; " \ 716 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 717 "upd=run load update\0" \ 718 "fdtaddr=780000\0" \ 719 "fdtfile=mpc834x_mds.dtb\0" \ 720 "" 721 722 #define CONFIG_NFSBOOTCOMMAND \ 723 "setenv bootargs root=/dev/nfs rw " \ 724 "nfsroot=$serverip:$rootpath " \ 725 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 726 "$netdev:off " \ 727 "console=$consoledev,$baudrate $othbootargs;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr - $fdtaddr" 731 732 #define CONFIG_RAMBOOTCOMMAND \ 733 "setenv bootargs root=/dev/ram rw " \ 734 "console=$consoledev,$baudrate $othbootargs;" \ 735 "tftp $ramdiskaddr $ramdiskfile;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr $ramdiskaddr $fdtaddr" 739 740 #define CONFIG_BOOTCOMMAND "run flash_self" 741 742 #endif /* __CONFIG_H */ 743