1 /* 2 * (C) Copyright 2006-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * mpc8349emds board configuration file 10 * 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 /* E300 Family */ 20 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 21 #define CONFIG_MPC834x 1 /* MPC834x family */ 22 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 23 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 24 25 #define CONFIG_SYS_TEXT_BASE 0xFE000000 26 27 #define CONFIG_PCI_66M 28 #ifdef CONFIG_PCI_66M 29 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 30 #else 31 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 32 #endif 33 34 #ifdef CONFIG_PCISLAVE 35 #define CONFIG_PCI 36 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 37 #endif /* CONFIG_PCISLAVE */ 38 39 #ifndef CONFIG_SYS_CLK_FREQ 40 #ifdef CONFIG_PCI_66M 41 #define CONFIG_SYS_CLK_FREQ 66000000 42 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 43 #else 44 #define CONFIG_SYS_CLK_FREQ 33000000 45 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 46 #endif 47 #endif 48 49 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 50 51 #define CONFIG_SYS_IMMR 0xE0000000 52 53 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 54 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 55 #define CONFIG_SYS_MEMTEST_END 0x00100000 56 57 /* 58 * DDR Setup 59 */ 60 #define CONFIG_DDR_ECC /* support DDR ECC function */ 61 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 62 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 63 64 /* 65 * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver 66 * undefine it to use old spd_sdram.c 67 */ 68 #define CONFIG_SYS_FSL_DDR2 69 #ifdef CONFIG_SYS_FSL_DDR2 70 #define CONFIG_SYS_FSL_DDRC_GEN2 71 #define CONFIG_SYS_SPD_BUS_NUM 0 72 #define SPD_EEPROM_ADDRESS1 0x52 73 #define SPD_EEPROM_ADDRESS2 0x51 74 #define CONFIG_NUM_DDR_CONTROLLERS 1 75 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 76 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 78 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 79 #endif 80 81 /* 82 * 32-bit data path mode. 83 * 84 * Please note that using this mode for devices with the real density of 64-bit 85 * effectively reduces the amount of available memory due to the effect of 86 * wrapping around while translating address to row/columns, for example in the 87 * 256MB module the upper 128MB get aliased with contents of the lower 88 * 128MB); normally this define should be used for devices with real 32-bit 89 * data path. 90 */ 91 #undef CONFIG_DDR_32BIT 92 93 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 95 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 96 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 97 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 98 #undef CONFIG_DDR_2T_TIMING 99 100 /* 101 * DDRCDR - DDR Control Driver Register 102 */ 103 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 110 #else 111 /* 112 * Manually set up DDR parameters 113 */ 114 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 115 #if defined(CONFIG_DDR_II) 116 #define CONFIG_SYS_DDRCDR 0x80080001 117 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 118 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 119 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 120 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 121 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 123 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 124 #define CONFIG_SYS_DDR_MODE 0x47d00432 125 #define CONFIG_SYS_DDR_MODE2 0x8000c000 126 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 127 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 128 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 129 #else 130 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 131 | CSCONFIG_ROW_BIT_13 \ 132 | CSCONFIG_COL_BIT_10) 133 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 134 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 135 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 136 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 137 138 #if defined(CONFIG_DDR_32BIT) 139 /* set burst length to 8 for 32-bit data path */ 140 /* DLL,normal,seq,4/2.5, 8 burst len */ 141 #define CONFIG_SYS_DDR_MODE 0x00000023 142 #else 143 /* the default burst length is 4 - for 64-bit data path */ 144 /* DLL,normal,seq,4/2.5, 4 burst len */ 145 #define CONFIG_SYS_DDR_MODE 0x00000022 146 #endif 147 #endif 148 #endif 149 150 /* 151 * SDRAM on the Local Bus 152 */ 153 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 154 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 155 156 /* 157 * FLASH on the Local Bus 158 */ 159 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 160 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 161 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 162 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 163 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 164 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 165 166 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 167 | BR_PS_16 /* 16 bit port */ \ 168 | BR_MS_GPCM /* MSEL = GPCM */ \ 169 | BR_V) /* valid */ 170 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 171 | OR_UPM_XAM \ 172 | OR_GPCM_CSNT \ 173 | OR_GPCM_ACS_DIV2 \ 174 | OR_GPCM_XACS \ 175 | OR_GPCM_SCY_15 \ 176 | OR_GPCM_TRLX_SET \ 177 | OR_GPCM_EHTR_SET \ 178 | OR_GPCM_EAD) 179 180 /* window base at flash base */ 181 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 182 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 186 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 192 193 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 194 #define CONFIG_SYS_RAMBOOT 195 #else 196 #undef CONFIG_SYS_RAMBOOT 197 #endif 198 199 /* 200 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 201 */ 202 #define CONFIG_SYS_BCSR 0xE2400000 203 /* Access window base at BCSR base */ 204 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 205 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 206 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 207 | BR_PS_8 \ 208 | BR_MS_GPCM \ 209 | BR_V) 210 /* 0x00000801 */ 211 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 212 | OR_GPCM_XAM \ 213 | OR_GPCM_CSNT \ 214 | OR_GPCM_SCY_15 \ 215 | OR_GPCM_TRLX_CLEAR \ 216 | OR_GPCM_EHTR_CLEAR) 217 /* 0xFFFFE8F0 */ 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 222 223 #define CONFIG_SYS_GBL_DATA_OFFSET \ 224 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 226 227 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 228 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 229 230 /* 231 * Local Bus LCRR and LBCR regs 232 * LCRR: DLL bypass, Clock divider is 4 233 * External Local Bus rate is 234 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 235 */ 236 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 237 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 238 #define CONFIG_SYS_LBC_LBCR 0x00000000 239 240 /* 241 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 242 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 243 */ 244 #undef CONFIG_SYS_LB_SDRAM 245 246 #ifdef CONFIG_SYS_LB_SDRAM 247 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 248 /* 249 * Base Register 2 and Option Register 2 configure SDRAM. 250 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 251 * 252 * For BR2, need: 253 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 254 * port-size = 32-bits = BR2[19:20] = 11 255 * no parity checking = BR2[21:22] = 00 256 * SDRAM for MSEL = BR2[24:26] = 011 257 * Valid = BR[31] = 1 258 * 259 * 0 4 8 12 16 20 24 28 260 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 261 */ 262 263 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 264 | BR_PS_32 /* 32-bit port */ \ 265 | BR_MS_SDRAM /* MSEL = SDRAM */ \ 266 | BR_V) /* Valid */ 267 /* 0xF0001861 */ 268 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 269 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 270 271 /* 272 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 273 * 274 * For OR2, need: 275 * 64MB mask for AM, OR2[0:7] = 1111 1100 276 * XAM, OR2[17:18] = 11 277 * 9 columns OR2[19-21] = 010 278 * 13 rows OR2[23-25] = 100 279 * EAD set for extra time OR[31] = 1 280 * 281 * 0 4 8 12 16 20 24 28 282 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 283 */ 284 285 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ 286 | OR_SDRAM_XAM \ 287 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 288 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 289 | OR_SDRAM_EAD) 290 /* 0xFC006901 */ 291 292 /* LB sdram refresh timer, about 6us */ 293 #define CONFIG_SYS_LBC_LSRT 0x32000000 294 /* LB refresh timer prescal, 266MHz/32 */ 295 #define CONFIG_SYS_LBC_MRTPR 0x20000000 296 297 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 298 | LSDMR_BSMA1516 \ 299 | LSDMR_RFCR8 \ 300 | LSDMR_PRETOACT6 \ 301 | LSDMR_ACTTORW3 \ 302 | LSDMR_BL8 \ 303 | LSDMR_WRC3 \ 304 | LSDMR_CL3) 305 306 /* 307 * SDRAM Controller configuration sequence. 308 */ 309 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 310 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 311 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 312 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 313 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 314 #endif 315 316 /* 317 * Serial Port 318 */ 319 #define CONFIG_CONS_INDEX 1 320 #define CONFIG_SYS_NS16550 321 #define CONFIG_SYS_NS16550_SERIAL 322 #define CONFIG_SYS_NS16550_REG_SIZE 1 323 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 324 325 #define CONFIG_SYS_BAUDRATE_TABLE \ 326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 327 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 330 331 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 332 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 333 /* Use the HUSH parser */ 334 #define CONFIG_SYS_HUSH_PARSER 335 336 /* pass open firmware flat tree */ 337 #define CONFIG_OF_LIBFDT 1 338 #define CONFIG_OF_BOARD_SETUP 1 339 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 340 341 /* I2C */ 342 #define CONFIG_SYS_I2C 343 #define CONFIG_SYS_I2C_FSL 344 #define CONFIG_SYS_FSL_I2C_SPEED 400000 345 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 346 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 347 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 348 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 349 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 350 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 351 352 /* SPI */ 353 #define CONFIG_MPC8XXX_SPI 354 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 355 356 /* GPIOs. Used as SPI chip selects */ 357 #define CONFIG_SYS_GPIO1_PRELIM 358 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 359 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 360 361 /* TSEC */ 362 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 363 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 364 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 365 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 366 367 /* USB */ 368 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 369 370 /* 371 * General PCI 372 * Addresses are mapped 1-1. 373 */ 374 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 375 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 376 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 377 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 378 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 379 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 380 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 381 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 382 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 383 384 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 385 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 386 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 387 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 388 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 389 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 390 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 391 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 392 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 393 394 #if defined(CONFIG_PCI) 395 396 #define PCI_ONE_PCI1 397 #if defined(PCI_64BIT) 398 #undef PCI_ALL_PCI1 399 #undef PCI_TWO_PCI1 400 #undef PCI_ONE_PCI1 401 #endif 402 403 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 404 #define CONFIG_83XX_PCI_STREAMING 405 406 #undef CONFIG_EEPRO100 407 #undef CONFIG_TULIP 408 409 #if !defined(CONFIG_PCI_PNP) 410 #define PCI_ENET0_IOADDR 0xFIXME 411 #define PCI_ENET0_MEMADDR 0xFIXME 412 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 413 #endif 414 415 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 416 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 417 418 #endif /* CONFIG_PCI */ 419 420 /* 421 * TSEC configuration 422 */ 423 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 424 425 #if defined(CONFIG_TSEC_ENET) 426 427 #define CONFIG_GMII 1 /* MII PHY management */ 428 #define CONFIG_TSEC1 1 429 #define CONFIG_TSEC1_NAME "TSEC0" 430 #define CONFIG_TSEC2 1 431 #define CONFIG_TSEC2_NAME "TSEC1" 432 #define TSEC1_PHY_ADDR 0 433 #define TSEC2_PHY_ADDR 1 434 #define TSEC1_PHYIDX 0 435 #define TSEC2_PHYIDX 0 436 #define TSEC1_FLAGS TSEC_GIGABIT 437 #define TSEC2_FLAGS TSEC_GIGABIT 438 439 /* Options are: TSEC[0-1] */ 440 #define CONFIG_ETHPRIME "TSEC0" 441 442 #endif /* CONFIG_TSEC_ENET */ 443 444 /* 445 * Configure on-board RTC 446 */ 447 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 448 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 449 450 /* 451 * Environment 452 */ 453 #ifndef CONFIG_SYS_RAMBOOT 454 #define CONFIG_ENV_IS_IN_FLASH 1 455 #define CONFIG_ENV_ADDR \ 456 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 457 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 458 #define CONFIG_ENV_SIZE 0x2000 459 460 /* Address and size of Redundant Environment Sector */ 461 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 462 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 463 464 #else 465 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 466 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 467 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 468 #define CONFIG_ENV_SIZE 0x2000 469 #endif 470 471 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 472 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 473 474 475 /* 476 * BOOTP options 477 */ 478 #define CONFIG_BOOTP_BOOTFILESIZE 479 #define CONFIG_BOOTP_BOOTPATH 480 #define CONFIG_BOOTP_GATEWAY 481 #define CONFIG_BOOTP_HOSTNAME 482 483 484 /* 485 * Command line configuration. 486 */ 487 #include <config_cmd_default.h> 488 489 #define CONFIG_CMD_PING 490 #define CONFIG_CMD_I2C 491 #define CONFIG_CMD_DATE 492 #define CONFIG_CMD_MII 493 494 #if defined(CONFIG_PCI) 495 #define CONFIG_CMD_PCI 496 #endif 497 498 #if defined(CONFIG_SYS_RAMBOOT) 499 #undef CONFIG_CMD_SAVEENV 500 #undef CONFIG_CMD_LOADS 501 #endif 502 503 504 #undef CONFIG_WATCHDOG /* watchdog disabled */ 505 506 /* 507 * Miscellaneous configurable options 508 */ 509 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 510 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 511 512 #if defined(CONFIG_CMD_KGDB) 513 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 514 #else 515 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 516 #endif 517 518 /* Print Buffer Size */ 519 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 520 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 521 /* Boot Argument Buffer Size */ 522 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 523 524 /* 525 * For booting Linux, the board info and command line data 526 * have to be in the first 256 MB of memory, since this is 527 * the maximum mapped by the Linux kernel during initialization. 528 */ 529 /* Initial Memory map for Linux*/ 530 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 531 532 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 533 534 #if 1 /*528/264*/ 535 #define CONFIG_SYS_HRCW_LOW (\ 536 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 537 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 538 HRCWL_CSB_TO_CLKIN |\ 539 HRCWL_VCO_1X2 |\ 540 HRCWL_CORE_TO_CSB_2X1) 541 #elif 0 /*396/132*/ 542 #define CONFIG_SYS_HRCW_LOW (\ 543 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 544 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 545 HRCWL_CSB_TO_CLKIN |\ 546 HRCWL_VCO_1X4 |\ 547 HRCWL_CORE_TO_CSB_3X1) 548 #elif 0 /*264/132*/ 549 #define CONFIG_SYS_HRCW_LOW (\ 550 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 551 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 552 HRCWL_CSB_TO_CLKIN |\ 553 HRCWL_VCO_1X4 |\ 554 HRCWL_CORE_TO_CSB_2X1) 555 #elif 0 /*132/132*/ 556 #define CONFIG_SYS_HRCW_LOW (\ 557 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 558 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 559 HRCWL_CSB_TO_CLKIN |\ 560 HRCWL_VCO_1X4 |\ 561 HRCWL_CORE_TO_CSB_1X1) 562 #elif 0 /*264/264 */ 563 #define CONFIG_SYS_HRCW_LOW (\ 564 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 565 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 566 HRCWL_CSB_TO_CLKIN |\ 567 HRCWL_VCO_1X4 |\ 568 HRCWL_CORE_TO_CSB_1X1) 569 #endif 570 571 #ifdef CONFIG_PCISLAVE 572 #define CONFIG_SYS_HRCW_HIGH (\ 573 HRCWH_PCI_AGENT |\ 574 HRCWH_64_BIT_PCI |\ 575 HRCWH_PCI1_ARBITER_DISABLE |\ 576 HRCWH_PCI2_ARBITER_DISABLE |\ 577 HRCWH_CORE_ENABLE |\ 578 HRCWH_FROM_0X00000100 |\ 579 HRCWH_BOOTSEQ_DISABLE |\ 580 HRCWH_SW_WATCHDOG_DISABLE |\ 581 HRCWH_ROM_LOC_LOCAL_16BIT |\ 582 HRCWH_TSEC1M_IN_GMII |\ 583 HRCWH_TSEC2M_IN_GMII) 584 #else 585 #if defined(PCI_64BIT) 586 #define CONFIG_SYS_HRCW_HIGH (\ 587 HRCWH_PCI_HOST |\ 588 HRCWH_64_BIT_PCI |\ 589 HRCWH_PCI1_ARBITER_ENABLE |\ 590 HRCWH_PCI2_ARBITER_DISABLE |\ 591 HRCWH_CORE_ENABLE |\ 592 HRCWH_FROM_0X00000100 |\ 593 HRCWH_BOOTSEQ_DISABLE |\ 594 HRCWH_SW_WATCHDOG_DISABLE |\ 595 HRCWH_ROM_LOC_LOCAL_16BIT |\ 596 HRCWH_TSEC1M_IN_GMII |\ 597 HRCWH_TSEC2M_IN_GMII) 598 #else 599 #define CONFIG_SYS_HRCW_HIGH (\ 600 HRCWH_PCI_HOST |\ 601 HRCWH_32_BIT_PCI |\ 602 HRCWH_PCI1_ARBITER_ENABLE |\ 603 HRCWH_PCI2_ARBITER_ENABLE |\ 604 HRCWH_CORE_ENABLE |\ 605 HRCWH_FROM_0X00000100 |\ 606 HRCWH_BOOTSEQ_DISABLE |\ 607 HRCWH_SW_WATCHDOG_DISABLE |\ 608 HRCWH_ROM_LOC_LOCAL_16BIT |\ 609 HRCWH_TSEC1M_IN_GMII |\ 610 HRCWH_TSEC2M_IN_GMII) 611 #endif /* PCI_64BIT */ 612 #endif /* CONFIG_PCISLAVE */ 613 614 /* 615 * System performance 616 */ 617 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 618 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 619 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 620 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 621 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 622 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 623 624 /* System IO Config */ 625 #define CONFIG_SYS_SICRH 0 626 #define CONFIG_SYS_SICRL SICRL_LDP_A 627 628 #define CONFIG_SYS_HID0_INIT 0x000000000 629 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 630 | HID0_ENABLE_INSTRUCTION_CACHE) 631 632 /* #define CONFIG_SYS_HID0_FINAL (\ 633 HID0_ENABLE_INSTRUCTION_CACHE |\ 634 HID0_ENABLE_M_BIT |\ 635 HID0_ENABLE_ADDRESS_BROADCAST) */ 636 637 638 #define CONFIG_SYS_HID2 HID2_HBE 639 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 640 641 /* DDR @ 0x00000000 */ 642 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 643 | BATL_PP_RW \ 644 | BATL_MEMCOHERENCE) 645 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 646 | BATU_BL_256M \ 647 | BATU_VS \ 648 | BATU_VP) 649 650 /* PCI @ 0x80000000 */ 651 #ifdef CONFIG_PCI 652 #define CONFIG_PCI_INDIRECT_BRIDGE 653 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 654 | BATL_PP_RW \ 655 | BATL_MEMCOHERENCE) 656 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 657 | BATU_BL_256M \ 658 | BATU_VS \ 659 | BATU_VP) 660 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 661 | BATL_PP_RW \ 662 | BATL_CACHEINHIBIT \ 663 | BATL_GUARDEDSTORAGE) 664 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 665 | BATU_BL_256M \ 666 | BATU_VS \ 667 | BATU_VP) 668 #else 669 #define CONFIG_SYS_IBAT1L (0) 670 #define CONFIG_SYS_IBAT1U (0) 671 #define CONFIG_SYS_IBAT2L (0) 672 #define CONFIG_SYS_IBAT2U (0) 673 #endif 674 675 #ifdef CONFIG_MPC83XX_PCI2 676 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 677 | BATL_PP_RW \ 678 | BATL_MEMCOHERENCE) 679 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 680 | BATU_BL_256M \ 681 | BATU_VS \ 682 | BATU_VP) 683 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 684 | BATL_PP_RW \ 685 | BATL_CACHEINHIBIT \ 686 | BATL_GUARDEDSTORAGE) 687 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 688 | BATU_BL_256M \ 689 | BATU_VS \ 690 | BATU_VP) 691 #else 692 #define CONFIG_SYS_IBAT3L (0) 693 #define CONFIG_SYS_IBAT3U (0) 694 #define CONFIG_SYS_IBAT4L (0) 695 #define CONFIG_SYS_IBAT4U (0) 696 #endif 697 698 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 699 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 700 | BATL_PP_RW \ 701 | BATL_CACHEINHIBIT \ 702 | BATL_GUARDEDSTORAGE) 703 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 704 | BATU_BL_256M \ 705 | BATU_VS \ 706 | BATU_VP) 707 708 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 709 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 710 | BATL_PP_RW \ 711 | BATL_MEMCOHERENCE \ 712 | BATL_GUARDEDSTORAGE) 713 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 714 | BATU_BL_256M \ 715 | BATU_VS \ 716 | BATU_VP) 717 718 #define CONFIG_SYS_IBAT7L (0) 719 #define CONFIG_SYS_IBAT7U (0) 720 721 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 722 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 723 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 724 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 725 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 726 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 727 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 728 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 729 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 730 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 731 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 732 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 733 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 734 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 735 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 736 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 737 738 #if defined(CONFIG_CMD_KGDB) 739 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 740 #endif 741 742 /* 743 * Environment Configuration 744 */ 745 #define CONFIG_ENV_OVERWRITE 746 747 #if defined(CONFIG_TSEC_ENET) 748 #define CONFIG_HAS_ETH1 749 #define CONFIG_HAS_ETH0 750 #endif 751 752 #define CONFIG_HOSTNAME mpc8349emds 753 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 754 #define CONFIG_BOOTFILE "uImage" 755 756 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 757 758 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 759 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 760 761 #define CONFIG_BAUDRATE 115200 762 763 #define CONFIG_PREBOOT "echo;" \ 764 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 765 "echo" 766 767 #define CONFIG_EXTRA_ENV_SETTINGS \ 768 "netdev=eth0\0" \ 769 "hostname=mpc8349emds\0" \ 770 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 771 "nfsroot=${serverip}:${rootpath}\0" \ 772 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 773 "addip=setenv bootargs ${bootargs} " \ 774 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 775 ":${hostname}:${netdev}:off panic=1\0" \ 776 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 777 "flash_nfs=run nfsargs addip addtty;" \ 778 "bootm ${kernel_addr}\0" \ 779 "flash_self=run ramargs addip addtty;" \ 780 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 781 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 782 "bootm\0" \ 783 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 784 "update=protect off fe000000 fe03ffff; " \ 785 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 786 "upd=run load update\0" \ 787 "fdtaddr=780000\0" \ 788 "fdtfile=mpc834x_mds.dtb\0" \ 789 "" 790 791 #define CONFIG_NFSBOOTCOMMAND \ 792 "setenv bootargs root=/dev/nfs rw " \ 793 "nfsroot=$serverip:$rootpath " \ 794 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 795 "$netdev:off " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr - $fdtaddr" 800 801 #define CONFIG_RAMBOOTCOMMAND \ 802 "setenv bootargs root=/dev/ram rw " \ 803 "console=$consoledev,$baudrate $othbootargs;" \ 804 "tftp $ramdiskaddr $ramdiskfile;" \ 805 "tftp $loadaddr $bootfile;" \ 806 "tftp $fdtaddr $fdtfile;" \ 807 "bootm $loadaddr $ramdiskaddr $fdtaddr" 808 809 #define CONFIG_BOOTCOMMAND "run flash_self" 810 811 #endif /* __CONFIG_H */ 812