1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 /* E300 Family */ 36 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 37 #define CONFIG_MPC834x 1 /* MPC834x family */ 38 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 39 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 40 41 #define PCI_66M 42 #ifdef PCI_66M 43 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 44 #else 45 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 46 #endif 47 48 #ifdef CONFIG_PCISLAVE 49 #define CONFIG_PCI 50 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 51 #endif /* CONFIG_PCISLAVE */ 52 53 #ifndef CONFIG_SYS_CLK_FREQ 54 #ifdef PCI_66M 55 #define CONFIG_SYS_CLK_FREQ 66000000 56 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 57 #else 58 #define CONFIG_SYS_CLK_FREQ 33000000 59 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 60 #endif 61 #endif 62 63 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 64 65 #define CONFIG_SYS_IMMR 0xE0000000 66 67 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 68 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 69 #define CONFIG_SYS_MEMTEST_END 0x00100000 70 71 /* 72 * DDR Setup 73 */ 74 #define CONFIG_DDR_ECC /* support DDR ECC function */ 75 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 76 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 77 78 /* 79 * 32-bit data path mode. 80 * 81 * Please note that using this mode for devices with the real density of 64-bit 82 * effectively reduces the amount of available memory due to the effect of 83 * wrapping around while translating address to row/columns, for example in the 84 * 256MB module the upper 128MB get aliased with contents of the lower 85 * 128MB); normally this define should be used for devices with real 32-bit 86 * data path. 87 */ 88 #undef CONFIG_DDR_32BIT 89 90 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 92 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 93 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 94 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 95 #undef CONFIG_DDR_2T_TIMING 96 97 /* 98 * DDRCDR - DDR Control Driver Register 99 */ 100 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 101 102 #if defined(CONFIG_SPD_EEPROM) 103 /* 104 * Determine DDR configuration from I2C interface. 105 */ 106 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 107 #else 108 /* 109 * Manually set up DDR parameters 110 */ 111 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 112 #if defined(CONFIG_DDR_II) 113 #define CONFIG_SYS_DDRCDR 0x80080001 114 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 115 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 116 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 117 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 118 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 121 #define CONFIG_SYS_DDR_MODE 0x47d00432 122 #define CONFIG_SYS_DDR_MODE2 0x8000c000 123 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 124 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 125 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 126 #else 127 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 128 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 129 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 130 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 131 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 132 133 #if defined(CONFIG_DDR_32BIT) 134 /* set burst length to 8 for 32-bit data path */ 135 #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 136 #else 137 /* the default burst length is 4 - for 64-bit data path */ 138 #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 139 #endif 140 #endif 141 #endif 142 143 /* 144 * SDRAM on the Local Bus 145 */ 146 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 147 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 148 149 /* 150 * FLASH on the Local Bus 151 */ 152 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 153 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 154 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 155 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 156 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 157 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 158 159 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 160 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 161 BR_V) /* valid */ 162 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 163 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 164 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 165 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 166 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ 167 168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 170 171 #undef CONFIG_SYS_FLASH_CHECKSUM 172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 176 177 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 178 #define CONFIG_SYS_RAMBOOT 179 #else 180 #undef CONFIG_SYS_RAMBOOT 181 #endif 182 183 /* 184 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 185 */ 186 #define CONFIG_SYS_BCSR 0xE2400000 187 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ 188 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 189 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 190 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 191 192 #define CONFIG_SYS_INIT_RAM_LOCK 1 193 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 194 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 195 196 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 201 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 202 203 /* 204 * Local Bus LCRR and LBCR regs 205 * LCRR: DLL bypass, Clock divider is 4 206 * External Local Bus rate is 207 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 208 */ 209 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 210 #define CONFIG_SYS_LBC_LBCR 0x00000000 211 212 /* 213 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 214 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 215 */ 216 #undef CONFIG_SYS_LB_SDRAM 217 218 #ifdef CONFIG_SYS_LB_SDRAM 219 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 220 /* 221 * Base Register 2 and Option Register 2 configure SDRAM. 222 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 223 * 224 * For BR2, need: 225 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 226 * port-size = 32-bits = BR2[19:20] = 11 227 * no parity checking = BR2[21:22] = 00 228 * SDRAM for MSEL = BR2[24:26] = 011 229 * Valid = BR[31] = 1 230 * 231 * 0 4 8 12 16 20 24 28 232 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 233 * 234 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 235 * FIXME: the top 17 bits of BR2. 236 */ 237 238 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 239 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 240 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 241 242 /* 243 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 244 * 245 * For OR2, need: 246 * 64MB mask for AM, OR2[0:7] = 1111 1100 247 * XAM, OR2[17:18] = 11 248 * 9 columns OR2[19-21] = 010 249 * 13 rows OR2[23-25] = 100 250 * EAD set for extra time OR[31] = 1 251 * 252 * 0 4 8 12 16 20 24 28 253 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 254 */ 255 256 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 257 258 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 259 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 260 261 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ 262 | LSDMR_BSMA1516 \ 263 | LSDMR_RFCR8 \ 264 | LSDMR_PRETOACT6 \ 265 | LSDMR_ACTTORW3 \ 266 | LSDMR_BL8 \ 267 | LSDMR_WRC3 \ 268 | LSDMR_CL3 \ 269 ) 270 271 /* 272 * SDRAM Controller configuration sequence. 273 */ 274 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 275 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 276 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 277 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 278 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 279 #endif 280 281 /* 282 * Serial Port 283 */ 284 #define CONFIG_CONS_INDEX 1 285 #undef CONFIG_SERIAL_SOFTWARE_FIFO 286 #define CONFIG_SYS_NS16550 287 #define CONFIG_SYS_NS16550_SERIAL 288 #define CONFIG_SYS_NS16550_REG_SIZE 1 289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 290 291 #define CONFIG_SYS_BAUDRATE_TABLE \ 292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 293 294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 296 297 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 298 /* Use the HUSH parser */ 299 #define CONFIG_SYS_HUSH_PARSER 300 #ifdef CONFIG_SYS_HUSH_PARSER 301 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 302 #endif 303 304 /* pass open firmware flat tree */ 305 #define CONFIG_OF_LIBFDT 1 306 #define CONFIG_OF_BOARD_SETUP 1 307 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 308 309 /* I2C */ 310 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 311 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 312 #define CONFIG_FSL_I2C 313 #define CONFIG_I2C_MULTI_BUS 314 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 315 #define CONFIG_SYS_I2C_SLAVE 0x7F 316 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 317 #define CONFIG_SYS_I2C_OFFSET 0x3000 318 #define CONFIG_SYS_I2C2_OFFSET 0x3100 319 320 /* SPI */ 321 #define CONFIG_MPC8XXX_SPI 322 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 323 324 /* GPIOs. Used as SPI chip selects */ 325 #define CONFIG_SYS_GPIO1_PRELIM 326 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 327 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 328 329 /* TSEC */ 330 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 331 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 332 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 333 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 334 335 /* USB */ 336 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 337 338 /* 339 * General PCI 340 * Addresses are mapped 1-1. 341 */ 342 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 343 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 344 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 345 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 346 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 347 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 348 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 349 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 350 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 351 352 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 353 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 354 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 355 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 356 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 357 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 358 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 359 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 360 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 361 362 #if defined(CONFIG_PCI) 363 364 #define PCI_ONE_PCI1 365 #if defined(PCI_64BIT) 366 #undef PCI_ALL_PCI1 367 #undef PCI_TWO_PCI1 368 #undef PCI_ONE_PCI1 369 #endif 370 371 #define CONFIG_NET_MULTI 372 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 373 #define CONFIG_83XX_PCI_STREAMING 374 375 #undef CONFIG_EEPRO100 376 #undef CONFIG_TULIP 377 378 #if !defined(CONFIG_PCI_PNP) 379 #define PCI_ENET0_IOADDR 0xFIXME 380 #define PCI_ENET0_MEMADDR 0xFIXME 381 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 382 #endif 383 384 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 385 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 386 387 #endif /* CONFIG_PCI */ 388 389 /* 390 * TSEC configuration 391 */ 392 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 393 394 #if defined(CONFIG_TSEC_ENET) 395 #ifndef CONFIG_NET_MULTI 396 #define CONFIG_NET_MULTI 1 397 #endif 398 399 #define CONFIG_GMII 1 /* MII PHY management */ 400 #define CONFIG_TSEC1 1 401 #define CONFIG_TSEC1_NAME "TSEC0" 402 #define CONFIG_TSEC2 1 403 #define CONFIG_TSEC2_NAME "TSEC1" 404 #define TSEC1_PHY_ADDR 0 405 #define TSEC2_PHY_ADDR 1 406 #define TSEC1_PHYIDX 0 407 #define TSEC2_PHYIDX 0 408 #define TSEC1_FLAGS TSEC_GIGABIT 409 #define TSEC2_FLAGS TSEC_GIGABIT 410 411 /* Options are: TSEC[0-1] */ 412 #define CONFIG_ETHPRIME "TSEC0" 413 414 #endif /* CONFIG_TSEC_ENET */ 415 416 /* 417 * Configure on-board RTC 418 */ 419 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 420 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 421 422 /* 423 * Environment 424 */ 425 #ifndef CONFIG_SYS_RAMBOOT 426 #define CONFIG_ENV_IS_IN_FLASH 1 427 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 428 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 429 #define CONFIG_ENV_SIZE 0x2000 430 431 /* Address and size of Redundant Environment Sector */ 432 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 433 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 434 435 #else 436 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 437 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 439 #define CONFIG_ENV_SIZE 0x2000 440 #endif 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 446 /* 447 * BOOTP options 448 */ 449 #define CONFIG_BOOTP_BOOTFILESIZE 450 #define CONFIG_BOOTP_BOOTPATH 451 #define CONFIG_BOOTP_GATEWAY 452 #define CONFIG_BOOTP_HOSTNAME 453 454 455 /* 456 * Command line configuration. 457 */ 458 #include <config_cmd_default.h> 459 460 #define CONFIG_CMD_PING 461 #define CONFIG_CMD_I2C 462 #define CONFIG_CMD_DATE 463 #define CONFIG_CMD_MII 464 465 #if defined(CONFIG_PCI) 466 #define CONFIG_CMD_PCI 467 #endif 468 469 #if defined(CONFIG_SYS_RAMBOOT) 470 #undef CONFIG_CMD_SAVEENV 471 #undef CONFIG_CMD_LOADS 472 #endif 473 474 475 #undef CONFIG_WATCHDOG /* watchdog disabled */ 476 477 /* 478 * Miscellaneous configurable options 479 */ 480 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 481 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 482 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 483 484 #if defined(CONFIG_CMD_KGDB) 485 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 486 #else 487 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 488 #endif 489 490 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 491 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 492 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 493 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 494 495 /* 496 * For booting Linux, the board info and command line data 497 * have to be in the first 8 MB of memory, since this is 498 * the maximum mapped by the Linux kernel during initialization. 499 */ 500 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 501 502 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 503 504 #if 1 /*528/264*/ 505 #define CONFIG_SYS_HRCW_LOW (\ 506 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 507 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 508 HRCWL_CSB_TO_CLKIN |\ 509 HRCWL_VCO_1X2 |\ 510 HRCWL_CORE_TO_CSB_2X1) 511 #elif 0 /*396/132*/ 512 #define CONFIG_SYS_HRCW_LOW (\ 513 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 514 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 515 HRCWL_CSB_TO_CLKIN |\ 516 HRCWL_VCO_1X4 |\ 517 HRCWL_CORE_TO_CSB_3X1) 518 #elif 0 /*264/132*/ 519 #define CONFIG_SYS_HRCW_LOW (\ 520 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 521 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 522 HRCWL_CSB_TO_CLKIN |\ 523 HRCWL_VCO_1X4 |\ 524 HRCWL_CORE_TO_CSB_2X1) 525 #elif 0 /*132/132*/ 526 #define CONFIG_SYS_HRCW_LOW (\ 527 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 528 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 529 HRCWL_CSB_TO_CLKIN |\ 530 HRCWL_VCO_1X4 |\ 531 HRCWL_CORE_TO_CSB_1X1) 532 #elif 0 /*264/264 */ 533 #define CONFIG_SYS_HRCW_LOW (\ 534 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 535 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 536 HRCWL_CSB_TO_CLKIN |\ 537 HRCWL_VCO_1X4 |\ 538 HRCWL_CORE_TO_CSB_1X1) 539 #endif 540 541 #ifdef CONFIG_PCISLAVE 542 #define CONFIG_SYS_HRCW_HIGH (\ 543 HRCWH_PCI_AGENT |\ 544 HRCWH_64_BIT_PCI |\ 545 HRCWH_PCI1_ARBITER_DISABLE |\ 546 HRCWH_PCI2_ARBITER_DISABLE |\ 547 HRCWH_CORE_ENABLE |\ 548 HRCWH_FROM_0X00000100 |\ 549 HRCWH_BOOTSEQ_DISABLE |\ 550 HRCWH_SW_WATCHDOG_DISABLE |\ 551 HRCWH_ROM_LOC_LOCAL_16BIT |\ 552 HRCWH_TSEC1M_IN_GMII |\ 553 HRCWH_TSEC2M_IN_GMII ) 554 #else 555 #if defined(PCI_64BIT) 556 #define CONFIG_SYS_HRCW_HIGH (\ 557 HRCWH_PCI_HOST |\ 558 HRCWH_64_BIT_PCI |\ 559 HRCWH_PCI1_ARBITER_ENABLE |\ 560 HRCWH_PCI2_ARBITER_DISABLE |\ 561 HRCWH_CORE_ENABLE |\ 562 HRCWH_FROM_0X00000100 |\ 563 HRCWH_BOOTSEQ_DISABLE |\ 564 HRCWH_SW_WATCHDOG_DISABLE |\ 565 HRCWH_ROM_LOC_LOCAL_16BIT |\ 566 HRCWH_TSEC1M_IN_GMII |\ 567 HRCWH_TSEC2M_IN_GMII ) 568 #else 569 #define CONFIG_SYS_HRCW_HIGH (\ 570 HRCWH_PCI_HOST |\ 571 HRCWH_32_BIT_PCI |\ 572 HRCWH_PCI1_ARBITER_ENABLE |\ 573 HRCWH_PCI2_ARBITER_ENABLE |\ 574 HRCWH_CORE_ENABLE |\ 575 HRCWH_FROM_0X00000100 |\ 576 HRCWH_BOOTSEQ_DISABLE |\ 577 HRCWH_SW_WATCHDOG_DISABLE |\ 578 HRCWH_ROM_LOC_LOCAL_16BIT |\ 579 HRCWH_TSEC1M_IN_GMII |\ 580 HRCWH_TSEC2M_IN_GMII ) 581 #endif /* PCI_64BIT */ 582 #endif /* CONFIG_PCISLAVE */ 583 584 /* 585 * System performance 586 */ 587 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 588 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 589 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 590 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 591 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 592 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 593 594 /* System IO Config */ 595 #define CONFIG_SYS_SICRH 0 596 #define CONFIG_SYS_SICRL SICRL_LDP_A 597 598 #define CONFIG_SYS_HID0_INIT 0x000000000 599 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 600 601 /* #define CONFIG_SYS_HID0_FINAL (\ 602 HID0_ENABLE_INSTRUCTION_CACHE |\ 603 HID0_ENABLE_M_BIT |\ 604 HID0_ENABLE_ADDRESS_BROADCAST ) */ 605 606 607 #define CONFIG_SYS_HID2 HID2_HBE 608 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 609 610 /* DDR @ 0x00000000 */ 611 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 612 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 613 614 /* PCI @ 0x80000000 */ 615 #ifdef CONFIG_PCI 616 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 617 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 618 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 619 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 620 #else 621 #define CONFIG_SYS_IBAT1L (0) 622 #define CONFIG_SYS_IBAT1U (0) 623 #define CONFIG_SYS_IBAT2L (0) 624 #define CONFIG_SYS_IBAT2U (0) 625 #endif 626 627 #ifdef CONFIG_MPC83XX_PCI2 628 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 629 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 630 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 631 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 632 #else 633 #define CONFIG_SYS_IBAT3L (0) 634 #define CONFIG_SYS_IBAT3U (0) 635 #define CONFIG_SYS_IBAT4L (0) 636 #define CONFIG_SYS_IBAT4U (0) 637 #endif 638 639 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 640 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 641 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 642 643 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 644 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 645 BATL_GUARDEDSTORAGE) 646 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 647 648 #define CONFIG_SYS_IBAT7L (0) 649 #define CONFIG_SYS_IBAT7U (0) 650 651 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 652 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 653 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 654 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 655 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 656 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 657 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 658 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 659 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 660 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 661 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 662 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 663 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 664 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 665 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 666 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 667 668 /* 669 * Internal Definitions 670 * 671 * Boot Flags 672 */ 673 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 674 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 675 676 #if defined(CONFIG_CMD_KGDB) 677 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 678 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 679 #endif 680 681 /* 682 * Environment Configuration 683 */ 684 #define CONFIG_ENV_OVERWRITE 685 686 #if defined(CONFIG_TSEC_ENET) 687 #define CONFIG_ETHADDR 00:04:9f:ef:23:33 688 #define CONFIG_HAS_ETH1 689 #define CONFIG_HAS_ETH0 690 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 691 #endif 692 693 #define CONFIG_IPADDR 192.168.1.253 694 695 #define CONFIG_HOSTNAME mpc8349emds 696 #define CONFIG_ROOTPATH /nfsroot/rootfs 697 #define CONFIG_BOOTFILE uImage 698 699 #define CONFIG_SERVERIP 192.168.1.1 700 #define CONFIG_GATEWAYIP 192.168.1.1 701 #define CONFIG_NETMASK 255.255.255.0 702 703 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 704 705 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 706 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 707 708 #define CONFIG_BAUDRATE 115200 709 710 #define CONFIG_PREBOOT "echo;" \ 711 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 712 "echo" 713 714 #define CONFIG_EXTRA_ENV_SETTINGS \ 715 "netdev=eth0\0" \ 716 "hostname=mpc8349emds\0" \ 717 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 718 "nfsroot=${serverip}:${rootpath}\0" \ 719 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 720 "addip=setenv bootargs ${bootargs} " \ 721 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 722 ":${hostname}:${netdev}:off panic=1\0" \ 723 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 724 "flash_nfs=run nfsargs addip addtty;" \ 725 "bootm ${kernel_addr}\0" \ 726 "flash_self=run ramargs addip addtty;" \ 727 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 728 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 729 "bootm\0" \ 730 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 731 "update=protect off fe000000 fe03ffff; " \ 732 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 733 "upd=run load update\0" \ 734 "fdtaddr=780000\0" \ 735 "fdtfile=mpc8349emds.dtb\0" \ 736 "" 737 738 #define CONFIG_NFSBOOTCOMMAND \ 739 "setenv bootargs root=/dev/nfs rw " \ 740 "nfsroot=$serverip:$rootpath " \ 741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr - $fdtaddr" 746 747 #define CONFIG_RAMBOOTCOMMAND \ 748 "setenv bootargs root=/dev/ram rw " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "tftp $ramdiskaddr $ramdiskfile;" \ 751 "tftp $loadaddr $bootfile;" \ 752 "tftp $fdtaddr $fdtfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_BOOTCOMMAND "run flash_self" 756 757 #endif /* __CONFIG_H */ 758