1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 /* E300 Family */ 36 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 37 #define CONFIG_MPC834X 1 /* MPC834X family */ 38 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 39 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 40 41 #undef CONFIG_PCI 42 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 43 44 #define PCI_66M 45 #ifdef PCI_66M 46 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 47 #else 48 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 49 #endif 50 51 #ifndef CONFIG_SYS_CLK_FREQ 52 #ifdef PCI_66M 53 #define CONFIG_SYS_CLK_FREQ 66000000 54 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 55 #else 56 #define CONFIG_SYS_CLK_FREQ 33000000 57 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 58 #endif 59 #endif 60 61 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 62 63 #define CFG_IMMR 0xE0000000 64 65 #undef CFG_DRAM_TEST /* memory test, takes time */ 66 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 67 #define CFG_MEMTEST_END 0x00100000 68 69 /* 70 * DDR Setup 71 */ 72 #define CONFIG_DDR_ECC /* support DDR ECC function */ 73 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 74 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 75 76 /* 77 * 32-bit data path mode. 78 * 79 * Please note that using this mode for devices with the real density of 64-bit 80 * effectively reduces the amount of available memory due to the effect of 81 * wrapping around while translating address to row/columns, for example in the 82 * 256MB module the upper 128MB get aliased with contents of the lower 83 * 128MB); normally this define should be used for devices with real 32-bit 84 * data path. 85 */ 86 #undef CONFIG_DDR_32BIT 87 88 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 89 #define CFG_SDRAM_BASE CFG_DDR_BASE 90 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 91 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 92 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 93 #undef CONFIG_DDR_2T_TIMING 94 95 /* 96 * DDRCDR - DDR Control Driver Register 97 */ 98 #define CFG_DDRCDR_VALUE 0x80080001 99 100 #if defined(CONFIG_SPD_EEPROM) 101 /* 102 * Determine DDR configuration from I2C interface. 103 */ 104 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 105 #else 106 /* 107 * Manually set up DDR parameters 108 */ 109 #define CFG_DDR_SIZE 256 /* MB */ 110 #if defined(CONFIG_DDR_II) 111 #define CFG_DDRCDR 0x80080001 112 #define CFG_DDR_CS2_BNDS 0x0000000f 113 #define CFG_DDR_CS2_CONFIG 0x80330102 114 #define CFG_DDR_TIMING_0 0x00220802 115 #define CFG_DDR_TIMING_1 0x38357322 116 #define CFG_DDR_TIMING_2 0x2f9048c8 117 #define CFG_DDR_TIMING_3 0x00000000 118 #define CFG_DDR_CLK_CNTL 0x02000000 119 #define CFG_DDR_MODE 0x47d00432 120 #define CFG_DDR_MODE2 0x8000c000 121 #define CFG_DDR_INTERVAL 0x03cf0080 122 #define CFG_DDR_SDRAM_CFG 0x43000000 123 #define CFG_DDR_SDRAM_CFG2 0x00401000 124 #else 125 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 126 #define CFG_DDR_TIMING_1 0x36332321 127 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 128 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 129 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 130 131 #if defined(CONFIG_DDR_32BIT) 132 /* set burst length to 8 for 32-bit data path */ 133 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 134 #else 135 /* the default burst length is 4 - for 64-bit data path */ 136 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 137 #endif 138 #endif 139 #endif 140 141 /* 142 * SDRAM on the Local Bus 143 */ 144 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 145 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 146 147 /* 148 * FLASH on the Local Bus 149 */ 150 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 151 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 152 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 153 #define CFG_FLASH_SIZE 32 /* max flash size in MB */ 154 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 155 156 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 157 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 158 BR_V) /* valid */ 159 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 160 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 161 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 162 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 163 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ 164 165 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 166 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ 167 168 #undef CFG_FLASH_CHECKSUM 169 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 170 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 171 172 #define CFG_MID_FLASH_JUMP 0x7F000000 173 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 174 175 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 176 #define CFG_RAMBOOT 177 #else 178 #undef CFG_RAMBOOT 179 #endif 180 181 /* 182 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 183 */ 184 #define CFG_BCSR 0xE2400000 185 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 186 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 187 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 188 #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 189 190 #define CONFIG_L1_INIT_RAM 191 #define CFG_INIT_RAM_LOCK 1 192 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 193 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 194 195 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 196 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 197 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 198 199 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 200 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 201 202 /* 203 * Local Bus LCRR and LBCR regs 204 * LCRR: DLL bypass, Clock divider is 4 205 * External Local Bus rate is 206 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 207 */ 208 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 209 #define CFG_LBC_LBCR 0x00000000 210 211 /* 212 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 213 * if board has SRDAM on local bus, you can define CFG_LB_SDRAM 214 */ 215 #undef CFG_LB_SDRAM 216 217 #ifdef CFG_LB_SDRAM 218 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 219 /* 220 * Base Register 2 and Option Register 2 configure SDRAM. 221 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 222 * 223 * For BR2, need: 224 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 225 * port-size = 32-bits = BR2[19:20] = 11 226 * no parity checking = BR2[21:22] = 00 227 * SDRAM for MSEL = BR2[24:26] = 011 228 * Valid = BR[31] = 1 229 * 230 * 0 4 8 12 16 20 24 28 231 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 232 * 233 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 234 * FIXME: the top 17 bits of BR2. 235 */ 236 237 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 238 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 239 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 240 241 /* 242 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 243 * 244 * For OR2, need: 245 * 64MB mask for AM, OR2[0:7] = 1111 1100 246 * XAM, OR2[17:18] = 11 247 * 9 columns OR2[19-21] = 010 248 * 13 rows OR2[23-25] = 100 249 * EAD set for extra time OR[31] = 1 250 * 251 * 0 4 8 12 16 20 24 28 252 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 253 */ 254 255 #define CFG_OR2_PRELIM 0xFC006901 256 257 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 258 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 259 260 /* 261 * LSDMR masks 262 */ 263 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 264 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 265 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 266 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 267 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 268 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 269 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 270 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 271 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 272 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 273 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 274 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 275 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 276 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 277 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 278 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 279 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 280 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 281 282 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 283 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 284 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 285 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 286 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 287 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 288 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 289 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 290 291 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 292 | CFG_LBC_LSDMR_BSMA1516 \ 293 | CFG_LBC_LSDMR_RFCR8 \ 294 | CFG_LBC_LSDMR_PRETOACT6 \ 295 | CFG_LBC_LSDMR_ACTTORW3 \ 296 | CFG_LBC_LSDMR_BL8 \ 297 | CFG_LBC_LSDMR_WRC3 \ 298 | CFG_LBC_LSDMR_CL3 \ 299 ) 300 301 /* 302 * SDRAM Controller configuration sequence. 303 */ 304 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 305 | CFG_LBC_LSDMR_OP_PCHALL) 306 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 307 | CFG_LBC_LSDMR_OP_ARFRSH) 308 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 309 | CFG_LBC_LSDMR_OP_ARFRSH) 310 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 311 | CFG_LBC_LSDMR_OP_MRW) 312 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 313 | CFG_LBC_LSDMR_OP_NORMAL) 314 #endif 315 316 /* 317 * Serial Port 318 */ 319 #define CONFIG_CONS_INDEX 1 320 #undef CONFIG_SERIAL_SOFTWARE_FIFO 321 #define CFG_NS16550 322 #define CFG_NS16550_SERIAL 323 #define CFG_NS16550_REG_SIZE 1 324 #define CFG_NS16550_CLK get_bus_freq(0) 325 326 #define CFG_BAUDRATE_TABLE \ 327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 328 329 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 330 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 331 332 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 333 /* Use the HUSH parser */ 334 #define CFG_HUSH_PARSER 335 #ifdef CFG_HUSH_PARSER 336 #define CFG_PROMPT_HUSH_PS2 "> " 337 #endif 338 339 /* pass open firmware flat tree */ 340 #define CONFIG_OF_LIBFDT 1 341 #define CONFIG_OF_BOARD_SETUP 1 342 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 343 344 /* I2C */ 345 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 346 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 347 #define CONFIG_FSL_I2C 348 #define CONFIG_I2C_MULTI_BUS 349 #define CONFIG_I2C_CMD_TREE 350 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 351 #define CFG_I2C_SLAVE 0x7F 352 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 353 #define CFG_I2C_OFFSET 0x3000 354 #define CFG_I2C2_OFFSET 0x3100 355 356 /* SPI */ 357 #define CONFIG_MPC8XXX_SPI 358 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 359 360 /* GPIOs. Used as SPI chip selects */ 361 #define CFG_GPIO1_PRELIM 362 #define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 363 #define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 364 365 /* TSEC */ 366 #define CFG_TSEC1_OFFSET 0x24000 367 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 368 #define CFG_TSEC2_OFFSET 0x25000 369 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 370 371 /* USB */ 372 #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 373 374 /* 375 * General PCI 376 * Addresses are mapped 1-1. 377 */ 378 #define CFG_PCI1_MEM_BASE 0x80000000 379 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 380 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 381 #define CFG_PCI1_MMIO_BASE 0x90000000 382 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 383 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 384 #define CFG_PCI1_IO_BASE 0x00000000 385 #define CFG_PCI1_IO_PHYS 0xE2000000 386 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 387 388 #define CFG_PCI2_MEM_BASE 0xA0000000 389 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 390 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 391 #define CFG_PCI2_MMIO_BASE 0xB0000000 392 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 393 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 394 #define CFG_PCI2_IO_BASE 0x00000000 395 #define CFG_PCI2_IO_PHYS 0xE2100000 396 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 397 398 #if defined(CONFIG_PCI) 399 400 #define PCI_ONE_PCI1 401 #if defined(PCI_64BIT) 402 #undef PCI_ALL_PCI1 403 #undef PCI_TWO_PCI1 404 #undef PCI_ONE_PCI1 405 #endif 406 407 #define CONFIG_NET_MULTI 408 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 409 410 #undef CONFIG_EEPRO100 411 #undef CONFIG_TULIP 412 413 #if !defined(CONFIG_PCI_PNP) 414 #define PCI_ENET0_IOADDR 0xFIXME 415 #define PCI_ENET0_MEMADDR 0xFIXME 416 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 417 #endif 418 419 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 420 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 421 422 #endif /* CONFIG_PCI */ 423 424 /* 425 * TSEC configuration 426 */ 427 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 428 429 #if defined(CONFIG_TSEC_ENET) 430 #ifndef CONFIG_NET_MULTI 431 #define CONFIG_NET_MULTI 1 432 #endif 433 434 #define CONFIG_GMII 1 /* MII PHY management */ 435 #define CONFIG_TSEC1 1 436 #define CONFIG_TSEC1_NAME "TSEC0" 437 #define CONFIG_TSEC2 1 438 #define CONFIG_TSEC2_NAME "TSEC1" 439 #define TSEC1_PHY_ADDR 0 440 #define TSEC2_PHY_ADDR 1 441 #define TSEC1_PHYIDX 0 442 #define TSEC2_PHYIDX 0 443 #define TSEC1_FLAGS TSEC_GIGABIT 444 #define TSEC2_FLAGS TSEC_GIGABIT 445 446 /* Options are: TSEC[0-1] */ 447 #define CONFIG_ETHPRIME "TSEC0" 448 449 #endif /* CONFIG_TSEC_ENET */ 450 451 /* 452 * Configure on-board RTC 453 */ 454 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 455 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 456 457 /* 458 * Environment 459 */ 460 #ifndef CFG_RAMBOOT 461 #define CFG_ENV_IS_IN_FLASH 1 462 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 463 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 464 #define CFG_ENV_SIZE 0x2000 465 466 /* Address and size of Redundant Environment Sector */ 467 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 468 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 469 470 #else 471 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 472 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 473 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 474 #define CFG_ENV_SIZE 0x2000 475 #endif 476 477 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 478 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 479 480 481 /* 482 * BOOTP options 483 */ 484 #define CONFIG_BOOTP_BOOTFILESIZE 485 #define CONFIG_BOOTP_BOOTPATH 486 #define CONFIG_BOOTP_GATEWAY 487 #define CONFIG_BOOTP_HOSTNAME 488 489 490 /* 491 * Command line configuration. 492 */ 493 #include <config_cmd_default.h> 494 495 #define CONFIG_CMD_PING 496 #define CONFIG_CMD_I2C 497 #define CONFIG_CMD_DATE 498 #define CONFIG_CMD_MII 499 500 #if defined(CONFIG_PCI) 501 #define CONFIG_CMD_PCI 502 #endif 503 504 #if defined(CFG_RAMBOOT) 505 #undef CONFIG_CMD_ENV 506 #undef CONFIG_CMD_LOADS 507 #endif 508 509 510 #undef CONFIG_WATCHDOG /* watchdog disabled */ 511 512 /* 513 * Miscellaneous configurable options 514 */ 515 #define CFG_LONGHELP /* undef to save memory */ 516 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 517 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 518 519 #if defined(CONFIG_CMD_KGDB) 520 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 521 #else 522 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 523 #endif 524 525 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 526 #define CFG_MAXARGS 16 /* max number of command args */ 527 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 528 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 529 530 /* 531 * For booting Linux, the board info and command line data 532 * have to be in the first 8 MB of memory, since this is 533 * the maximum mapped by the Linux kernel during initialization. 534 */ 535 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 536 537 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 538 539 #if 1 /*528/264*/ 540 #define CFG_HRCW_LOW (\ 541 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 542 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 543 HRCWL_CSB_TO_CLKIN |\ 544 HRCWL_VCO_1X2 |\ 545 HRCWL_CORE_TO_CSB_2X1) 546 #elif 0 /*396/132*/ 547 #define CFG_HRCW_LOW (\ 548 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 549 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 550 HRCWL_CSB_TO_CLKIN |\ 551 HRCWL_VCO_1X4 |\ 552 HRCWL_CORE_TO_CSB_3X1) 553 #elif 0 /*264/132*/ 554 #define CFG_HRCW_LOW (\ 555 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 556 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 557 HRCWL_CSB_TO_CLKIN |\ 558 HRCWL_VCO_1X4 |\ 559 HRCWL_CORE_TO_CSB_2X1) 560 #elif 0 /*132/132*/ 561 #define CFG_HRCW_LOW (\ 562 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 563 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 564 HRCWL_CSB_TO_CLKIN |\ 565 HRCWL_VCO_1X4 |\ 566 HRCWL_CORE_TO_CSB_1X1) 567 #elif 0 /*264/264 */ 568 #define CFG_HRCW_LOW (\ 569 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 570 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 571 HRCWL_CSB_TO_CLKIN |\ 572 HRCWL_VCO_1X4 |\ 573 HRCWL_CORE_TO_CSB_1X1) 574 #endif 575 576 #if defined(PCI_64BIT) 577 #define CFG_HRCW_HIGH (\ 578 HRCWH_PCI_HOST |\ 579 HRCWH_64_BIT_PCI |\ 580 HRCWH_PCI1_ARBITER_ENABLE |\ 581 HRCWH_PCI2_ARBITER_DISABLE |\ 582 HRCWH_CORE_ENABLE |\ 583 HRCWH_FROM_0X00000100 |\ 584 HRCWH_BOOTSEQ_DISABLE |\ 585 HRCWH_SW_WATCHDOG_DISABLE |\ 586 HRCWH_ROM_LOC_LOCAL_16BIT |\ 587 HRCWH_TSEC1M_IN_GMII |\ 588 HRCWH_TSEC2M_IN_GMII ) 589 #else 590 #define CFG_HRCW_HIGH (\ 591 HRCWH_PCI_HOST |\ 592 HRCWH_32_BIT_PCI |\ 593 HRCWH_PCI1_ARBITER_ENABLE |\ 594 HRCWH_PCI2_ARBITER_ENABLE |\ 595 HRCWH_CORE_ENABLE |\ 596 HRCWH_FROM_0X00000100 |\ 597 HRCWH_BOOTSEQ_DISABLE |\ 598 HRCWH_SW_WATCHDOG_DISABLE |\ 599 HRCWH_ROM_LOC_LOCAL_16BIT |\ 600 HRCWH_TSEC1M_IN_GMII |\ 601 HRCWH_TSEC2M_IN_GMII ) 602 #endif 603 604 /* 605 * System performance 606 */ 607 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 608 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 609 #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 610 #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 611 #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 612 #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 613 614 /* System IO Config */ 615 #define CFG_SICRH SICRH_TSOBI1 616 #define CFG_SICRL SICRL_LDP_A 617 618 #define CFG_HID0_INIT 0x000000000 619 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 620 621 /* #define CFG_HID0_FINAL (\ 622 HID0_ENABLE_INSTRUCTION_CACHE |\ 623 HID0_ENABLE_M_BIT |\ 624 HID0_ENABLE_ADDRESS_BROADCAST ) */ 625 626 627 #define CFG_HID2 HID2_HBE 628 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 629 630 /* DDR @ 0x00000000 */ 631 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 632 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 633 634 /* PCI @ 0x80000000 */ 635 #ifdef CONFIG_PCI 636 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 637 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 638 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 639 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 640 #else 641 #define CFG_IBAT1L (0) 642 #define CFG_IBAT1U (0) 643 #define CFG_IBAT2L (0) 644 #define CFG_IBAT2U (0) 645 #endif 646 647 #ifdef CONFIG_MPC83XX_PCI2 648 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 649 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 650 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 651 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 652 #else 653 #define CFG_IBAT3L (0) 654 #define CFG_IBAT3U (0) 655 #define CFG_IBAT4L (0) 656 #define CFG_IBAT4U (0) 657 #endif 658 659 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 660 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 661 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 662 663 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 664 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 665 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 666 667 #define CFG_IBAT7L (0) 668 #define CFG_IBAT7U (0) 669 670 #define CFG_DBAT0L CFG_IBAT0L 671 #define CFG_DBAT0U CFG_IBAT0U 672 #define CFG_DBAT1L CFG_IBAT1L 673 #define CFG_DBAT1U CFG_IBAT1U 674 #define CFG_DBAT2L CFG_IBAT2L 675 #define CFG_DBAT2U CFG_IBAT2U 676 #define CFG_DBAT3L CFG_IBAT3L 677 #define CFG_DBAT3U CFG_IBAT3U 678 #define CFG_DBAT4L CFG_IBAT4L 679 #define CFG_DBAT4U CFG_IBAT4U 680 #define CFG_DBAT5L CFG_IBAT5L 681 #define CFG_DBAT5U CFG_IBAT5U 682 #define CFG_DBAT6L CFG_IBAT6L 683 #define CFG_DBAT6U CFG_IBAT6U 684 #define CFG_DBAT7L CFG_IBAT7L 685 #define CFG_DBAT7U CFG_IBAT7U 686 687 /* 688 * Internal Definitions 689 * 690 * Boot Flags 691 */ 692 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 693 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 694 695 #if defined(CONFIG_CMD_KGDB) 696 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 697 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 698 #endif 699 700 /* 701 * Environment Configuration 702 */ 703 #define CONFIG_ENV_OVERWRITE 704 705 #if defined(CONFIG_TSEC_ENET) 706 #define CONFIG_ETHADDR 00:04:9f:ef:23:33 707 #define CONFIG_HAS_ETH1 708 #define CONFIG_HAS_ETH0 709 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 710 #endif 711 712 #define CONFIG_IPADDR 192.168.1.253 713 714 #define CONFIG_HOSTNAME mpc8349emds 715 #define CONFIG_ROOTPATH /nfsroot/rootfs 716 #define CONFIG_BOOTFILE uImage 717 718 #define CONFIG_SERVERIP 192.168.1.1 719 #define CONFIG_GATEWAYIP 192.168.1.1 720 #define CONFIG_NETMASK 255.255.255.0 721 722 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 723 724 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 725 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 726 727 #define CONFIG_BAUDRATE 115200 728 729 #define CONFIG_PREBOOT "echo;" \ 730 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 731 "echo" 732 733 #define CONFIG_EXTRA_ENV_SETTINGS \ 734 "netdev=eth0\0" \ 735 "hostname=mpc8349emds\0" \ 736 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 737 "nfsroot=${serverip}:${rootpath}\0" \ 738 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 739 "addip=setenv bootargs ${bootargs} " \ 740 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 741 ":${hostname}:${netdev}:off panic=1\0" \ 742 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 743 "flash_nfs=run nfsargs addip addtty;" \ 744 "bootm ${kernel_addr}\0" \ 745 "flash_self=run ramargs addip addtty;" \ 746 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 747 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 748 "bootm\0" \ 749 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 750 "update=protect off fe000000 fe03ffff; " \ 751 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 752 "upd=run load update\0" \ 753 "fdtaddr=400000\0" \ 754 "fdtfile=mpc8349emds.dtb\0" \ 755 "" 756 757 #define CONFIG_NFSBOOTCOMMAND \ 758 "setenv bootargs root=/dev/nfs rw " \ 759 "nfsroot=$serverip:$rootpath " \ 760 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 761 "console=$consoledev,$baudrate $othbootargs;" \ 762 "tftp $loadaddr $bootfile;" \ 763 "tftp $fdtaddr $fdtfile;" \ 764 "bootm $loadaddr - $fdtaddr" 765 766 #define CONFIG_RAMBOOTCOMMAND \ 767 "setenv bootargs root=/dev/ram rw " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "tftp $ramdiskaddr $ramdiskfile;" \ 770 "tftp $loadaddr $bootfile;" \ 771 "tftp $fdtaddr $fdtfile;" \ 772 "bootm $loadaddr $ramdiskaddr $fdtaddr" 773 774 #define CONFIG_BOOTCOMMAND "run flash_self" 775 776 #endif /* __CONFIG_H */ 777