1 /*
2  * (C) Copyright 2006
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 /*
25  * mpc8349emds board configuration file
26  *
27  */
28 
29 #ifndef __CONFIG_H
30 #define __CONFIG_H
31 
32 #undef DEBUG
33 
34 /*
35  * High Level Configuration Options
36  */
37 #define CONFIG_E300		1	/* E300 Family */
38 #define CONFIG_MPC83XX		1	/* MPC83XX family */
39 #define CONFIG_MPC834X		1	/* MPC834X family */
40 #define CONFIG_MPC8349		1	/* MPC8349 specific */
41 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
42 
43 #undef CONFIG_PCI
44 #undef CONFIG_MPC83XX_PCI2 		/* support for 2nd PCI controller */
45 
46 #define PCI_66M
47 #ifdef PCI_66M
48 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
49 #else
50 #define CONFIG_83XX_CLKIN	33000000	/* in Hz */
51 #endif
52 
53 #ifndef CONFIG_SYS_CLK_FREQ
54 #ifdef PCI_66M
55 #define CONFIG_SYS_CLK_FREQ	66000000
56 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
57 #else
58 #define CONFIG_SYS_CLK_FREQ	33000000
59 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
60 #endif
61 #endif
62 
63 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
64 
65 #define CFG_IMMR		0xE0000000
66 
67 #undef CFG_DRAM_TEST				/* memory test, takes time */
68 #define CFG_MEMTEST_START	0x00000000      /* memtest region */
69 #define CFG_MEMTEST_END		0x00100000
70 
71 /*
72  * DDR Setup
73  */
74 #define CONFIG_DDR_ECC			/* support DDR ECC function */
75 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
76 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
77 
78 /*
79  * 32-bit data path mode.
80  *
81  * Please note that using this mode for devices with the real density of 64-bit
82  * effectively reduces the amount of available memory due to the effect of
83  * wrapping around while translating address to row/columns, for example in the
84  * 256MB module the upper 128MB get aliased with contents of the lower
85  * 128MB); normally this define should be used for devices with real 32-bit
86  * data path.
87  */
88 #undef CONFIG_DDR_32BIT
89 
90 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
91 #define CFG_SDRAM_BASE		CFG_DDR_BASE
92 #define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
93 #define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
94 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
95 #undef  CONFIG_DDR_2T_TIMING
96 
97 /*
98  * DDRCDR - DDR Control Driver Register
99  */
100 #define CFG_DDRCDR_VALUE	0x80080001
101 
102 #if defined(CONFIG_SPD_EEPROM)
103 /*
104  * Determine DDR configuration from I2C interface.
105  */
106 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
107 #else
108 /*
109  * Manually set up DDR parameters
110  */
111 #define CFG_DDR_SIZE		256		/* MB */
112 #if defined(CONFIG_DDR_II)
113 #define CFG_DDRCDR		0x80080001
114 #define CFG_DDR_CS2_BNDS	0x0000000f
115 #define CFG_DDR_CS2_CONFIG	0x80330102
116 #define CFG_DDR_TIMING_0	0x00220802
117 #define CFG_DDR_TIMING_1	0x38357322
118 #define CFG_DDR_TIMING_2	0x2f9048c8
119 #define CFG_DDR_TIMING_3	0x00000000
120 #define CFG_DDR_CLK_CNTL	0x02000000
121 #define CFG_DDR_MODE		0x47d00432
122 #define CFG_DDR_MODE2		0x8000c000
123 #define CFG_DDR_INTERVAL	0x03cf0080
124 #define CFG_DDR_SDRAM_CFG	0x43000000
125 #define CFG_DDR_SDRAM_CFG2	0x00401000
126 #else
127 #define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
128 #define CFG_DDR_TIMING_1	0x36332321
129 #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
130 #define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
131 #define CFG_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
132 
133 #if defined(CONFIG_DDR_32BIT)
134 /* set burst length to 8 for 32-bit data path */
135 #define CFG_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
136 #else
137 /* the default burst length is 4 - for 64-bit data path */
138 #define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
139 #endif
140 #endif
141 #endif
142 
143 /*
144  * SDRAM on the Local Bus
145  */
146 #define CFG_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
147 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
148 
149 /*
150  * FLASH on the Local Bus
151  */
152 #define CFG_FLASH_CFI				/* use the Common Flash Interface */
153 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
154 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
155 #define CFG_FLASH_SIZE		32		/* max flash size in MB */
156 /* #define CFG_FLASH_USE_BUFFER_WRITE */
157 
158 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
159 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
160 				BR_V)			/* valid */
161 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
162 				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
163 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
164 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
165 #define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
166 
167 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
168 #define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
169 
170 #undef CFG_FLASH_CHECKSUM
171 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
172 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
173 
174 #define CFG_MID_FLASH_JUMP	0x7F000000
175 #define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
176 
177 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
178 #define CFG_RAMBOOT
179 #else
180 #undef  CFG_RAMBOOT
181 #endif
182 
183 /*
184  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
185  */
186 #define CFG_BCSR		0xE2400000
187 #define CFG_LBLAWBAR1_PRELIM	CFG_BCSR		/* Access window base at BCSR base */
188 #define CFG_LBLAWAR1_PRELIM	0x8000000E		/* Access window size 32K */
189 #define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
190 #define CFG_OR1_PRELIM		0xFFFFE8F0		/* length 32K */
191 
192 #define CONFIG_L1_INIT_RAM
193 #define CFG_INIT_RAM_LOCK	1
194 #define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
195 #define CFG_INIT_RAM_END	0x1000			/* End of used area in RAM*/
196 
197 #define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
198 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
199 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
200 
201 #define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
202 #define CFG_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
203 
204 /*
205  * Local Bus LCRR and LBCR regs
206  *    LCRR:  DLL bypass, Clock divider is 4
207  * External Local Bus rate is
208  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
209  */
210 #define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
211 #define CFG_LBC_LBCR	0x00000000
212 
213 /*
214  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
215  * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
216  */
217 #undef CFG_LB_SDRAM
218 
219 #ifdef CFG_LB_SDRAM
220 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
221 /*
222  * Base Register 2 and Option Register 2 configure SDRAM.
223  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
224  *
225  * For BR2, need:
226  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
227  *    port-size = 32-bits = BR2[19:20] = 11
228  *    no parity checking = BR2[21:22] = 00
229  *    SDRAM for MSEL = BR2[24:26] = 011
230  *    Valid = BR[31] = 1
231  *
232  * 0    4    8    12   16   20   24   28
233  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
234  *
235  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
236  * FIXME: the top 17 bits of BR2.
237  */
238 
239 #define CFG_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
240 #define CFG_LBLAWBAR2_PRELIM	0xF0000000
241 #define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
242 
243 /*
244  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
245  *
246  * For OR2, need:
247  *    64MB mask for AM, OR2[0:7] = 1111 1100
248  *                 XAM, OR2[17:18] = 11
249  *    9 columns OR2[19-21] = 010
250  *    13 rows   OR2[23-25] = 100
251  *    EAD set for extra time OR[31] = 1
252  *
253  * 0    4    8    12   16   20   24   28
254  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
255  */
256 
257 #define CFG_OR2_PRELIM	0xFC006901
258 
259 #define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
260 #define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
261 
262 /*
263  * LSDMR masks
264  */
265 #define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
266 #define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
267 #define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
268 #define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
269 #define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
270 #define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
271 #define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
272 #define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
273 #define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
274 #define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
275 #define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
276 #define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
277 #define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
278 #define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
279 #define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
280 #define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
281 #define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
282 #define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
283 
284 #define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
285 #define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
286 #define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
287 #define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
288 #define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
289 #define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
290 #define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
291 #define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
292 
293 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
294 				| CFG_LBC_LSDMR_BSMA1516	\
295 				| CFG_LBC_LSDMR_RFCR8		\
296 				| CFG_LBC_LSDMR_PRETOACT6	\
297 				| CFG_LBC_LSDMR_ACTTORW3	\
298 				| CFG_LBC_LSDMR_BL8		\
299 				| CFG_LBC_LSDMR_WRC3		\
300 				| CFG_LBC_LSDMR_CL3		\
301 				)
302 
303 /*
304  * SDRAM Controller configuration sequence.
305  */
306 #define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
307 				| CFG_LBC_LSDMR_OP_PCHALL)
308 #define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
309 				| CFG_LBC_LSDMR_OP_ARFRSH)
310 #define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
311 				| CFG_LBC_LSDMR_OP_ARFRSH)
312 #define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
313 				| CFG_LBC_LSDMR_OP_MRW)
314 #define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
315 				| CFG_LBC_LSDMR_OP_NORMAL)
316 #endif
317 
318 /*
319  * Serial Port
320  */
321 #define CONFIG_CONS_INDEX     1
322 #undef CONFIG_SERIAL_SOFTWARE_FIFO
323 #define CFG_NS16550
324 #define CFG_NS16550_SERIAL
325 #define CFG_NS16550_REG_SIZE    1
326 #define CFG_NS16550_CLK		get_bus_freq(0)
327 
328 #define CFG_BAUDRATE_TABLE  \
329 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
330 
331 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
332 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
333 
334 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
335 /* Use the HUSH parser */
336 #define CFG_HUSH_PARSER
337 #ifdef  CFG_HUSH_PARSER
338 #define CFG_PROMPT_HUSH_PS2 "> "
339 #endif
340 
341 /* pass open firmware flat tree */
342 #define CONFIG_OF_LIBFDT	1
343 #define CONFIG_OF_BOARD_SETUP	1
344 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
345 
346 /* I2C */
347 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
348 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
349 #define CONFIG_FSL_I2C
350 #define CONFIG_I2C_MULTI_BUS
351 #define CONFIG_I2C_CMD_TREE
352 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
353 #define CFG_I2C_SLAVE		0x7F
354 #define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
355 #define CFG_I2C_OFFSET		0x3000
356 #define CFG_I2C2_OFFSET		0x3100
357 
358 /* TSEC */
359 #define CFG_TSEC1_OFFSET 0x24000
360 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
361 #define CFG_TSEC2_OFFSET 0x25000
362 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
363 
364 /* USB */
365 #define CFG_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
366 
367 /*
368  * General PCI
369  * Addresses are mapped 1-1.
370  */
371 #define CFG_PCI1_MEM_BASE	0x80000000
372 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
373 #define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
374 #define CFG_PCI1_MMIO_BASE	0x90000000
375 #define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
376 #define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
377 #define CFG_PCI1_IO_BASE	0x00000000
378 #define CFG_PCI1_IO_PHYS	0xE2000000
379 #define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
380 
381 #define CFG_PCI2_MEM_BASE	0xA0000000
382 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
383 #define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
384 #define CFG_PCI2_MMIO_BASE	0xB0000000
385 #define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
386 #define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
387 #define CFG_PCI2_IO_BASE	0x00000000
388 #define CFG_PCI2_IO_PHYS	0xE2100000
389 #define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
390 
391 #if defined(CONFIG_PCI)
392 
393 #define PCI_ONE_PCI1
394 #if defined(PCI_64BIT)
395 #undef PCI_ALL_PCI1
396 #undef PCI_TWO_PCI1
397 #undef PCI_ONE_PCI1
398 #endif
399 
400 #define CONFIG_NET_MULTI
401 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
402 
403 #undef CONFIG_EEPRO100
404 #undef CONFIG_TULIP
405 
406 #if !defined(CONFIG_PCI_PNP)
407 	#define PCI_ENET0_IOADDR	0xFIXME
408 	#define PCI_ENET0_MEMADDR	0xFIXME
409 	#define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
410 #endif
411 
412 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
413 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
414 
415 #endif	/* CONFIG_PCI */
416 
417 /*
418  * TSEC configuration
419  */
420 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
421 
422 #if defined(CONFIG_TSEC_ENET)
423 #ifndef CONFIG_NET_MULTI
424 #define CONFIG_NET_MULTI	1
425 #endif
426 
427 #define CONFIG_GMII		1	/* MII PHY management */
428 #define CONFIG_TSEC1	1
429 #define CONFIG_TSEC1_NAME	"TSEC0"
430 #define CONFIG_TSEC2	1
431 #define CONFIG_TSEC2_NAME	"TSEC1"
432 #define TSEC1_PHY_ADDR		0
433 #define TSEC2_PHY_ADDR		1
434 #define TSEC1_PHYIDX		0
435 #define TSEC2_PHYIDX		0
436 #define TSEC1_FLAGS		TSEC_GIGABIT
437 #define TSEC2_FLAGS		TSEC_GIGABIT
438 
439 /* Options are: TSEC[0-1] */
440 #define CONFIG_ETHPRIME		"TSEC0"
441 
442 #endif	/* CONFIG_TSEC_ENET */
443 
444 /*
445  * Configure on-board RTC
446  */
447 #define CONFIG_RTC_DS1374			/* use ds1374 rtc via i2c	*/
448 #define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
449 
450 /*
451  * Environment
452  */
453 #ifndef CFG_RAMBOOT
454 	#define CFG_ENV_IS_IN_FLASH	1
455 	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
456 	#define CFG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
457 	#define CFG_ENV_SIZE		0x2000
458 
459 /* Address and size of Redundant Environment Sector	*/
460 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
461 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
462 
463 #else
464 	#define CFG_NO_FLASH		1	/* Flash is not usable now */
465 	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
466 	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
467 	#define CFG_ENV_SIZE		0x2000
468 #endif
469 
470 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
471 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
472 
473 
474 /*
475  * BOOTP options
476  */
477 #define CONFIG_BOOTP_BOOTFILESIZE
478 #define CONFIG_BOOTP_BOOTPATH
479 #define CONFIG_BOOTP_GATEWAY
480 #define CONFIG_BOOTP_HOSTNAME
481 
482 
483 /*
484  * Command line configuration.
485  */
486 #include <config_cmd_default.h>
487 
488 #define CONFIG_CMD_PING
489 #define CONFIG_CMD_I2C
490 #define CONFIG_CMD_DATE
491 #define CONFIG_CMD_MII
492 
493 #if defined(CONFIG_PCI)
494     #define CONFIG_CMD_PCI
495 #endif
496 
497 #if defined(CFG_RAMBOOT)
498     #undef CONFIG_CMD_ENV
499     #undef CONFIG_CMD_LOADS
500 #endif
501 
502 
503 #undef CONFIG_WATCHDOG			/* watchdog disabled */
504 
505 /*
506  * Miscellaneous configurable options
507  */
508 #define CFG_LONGHELP			/* undef to save memory */
509 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
510 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
511 
512 #if defined(CONFIG_CMD_KGDB)
513 	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
514 #else
515 	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
516 #endif
517 
518 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
519 #define CFG_MAXARGS	16		/* max number of command args */
520 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
521 #define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
522 
523 /*
524  * For booting Linux, the board info and command line data
525  * have to be in the first 8 MB of memory, since this is
526  * the maximum mapped by the Linux kernel during initialization.
527  */
528 #define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
529 
530 /* Cache Configuration */
531 #define CFG_DCACHE_SIZE		32768
532 #define CFG_CACHELINE_SIZE	32
533 #if defined(CONFIG_CMD_KGDB)
534 #define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
535 #endif
536 
537 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
538 
539 #if 1 /*528/264*/
540 #define CFG_HRCW_LOW (\
541 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
542 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
543 	HRCWL_CSB_TO_CLKIN |\
544 	HRCWL_VCO_1X2 |\
545 	HRCWL_CORE_TO_CSB_2X1)
546 #elif 0 /*396/132*/
547 #define CFG_HRCW_LOW (\
548 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
549 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
550 	HRCWL_CSB_TO_CLKIN |\
551 	HRCWL_VCO_1X4 |\
552 	HRCWL_CORE_TO_CSB_3X1)
553 #elif 0 /*264/132*/
554 #define CFG_HRCW_LOW (\
555 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
556 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
557 	HRCWL_CSB_TO_CLKIN |\
558 	HRCWL_VCO_1X4 |\
559 	HRCWL_CORE_TO_CSB_2X1)
560 #elif 0 /*132/132*/
561 #define CFG_HRCW_LOW (\
562 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
563 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
564 	HRCWL_CSB_TO_CLKIN |\
565 	HRCWL_VCO_1X4 |\
566 	HRCWL_CORE_TO_CSB_1X1)
567 #elif 0 /*264/264 */
568 #define CFG_HRCW_LOW (\
569 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
570 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
571 	HRCWL_CSB_TO_CLKIN |\
572 	HRCWL_VCO_1X4 |\
573 	HRCWL_CORE_TO_CSB_1X1)
574 #endif
575 
576 #if defined(PCI_64BIT)
577 #define CFG_HRCW_HIGH (\
578 	HRCWH_PCI_HOST |\
579 	HRCWH_64_BIT_PCI |\
580 	HRCWH_PCI1_ARBITER_ENABLE |\
581 	HRCWH_PCI2_ARBITER_DISABLE |\
582 	HRCWH_CORE_ENABLE |\
583 	HRCWH_FROM_0X00000100 |\
584 	HRCWH_BOOTSEQ_DISABLE |\
585 	HRCWH_SW_WATCHDOG_DISABLE |\
586 	HRCWH_ROM_LOC_LOCAL_16BIT |\
587 	HRCWH_TSEC1M_IN_GMII |\
588 	HRCWH_TSEC2M_IN_GMII )
589 #else
590 #define CFG_HRCW_HIGH (\
591 	HRCWH_PCI_HOST |\
592 	HRCWH_32_BIT_PCI |\
593 	HRCWH_PCI1_ARBITER_ENABLE |\
594 	HRCWH_PCI2_ARBITER_ENABLE |\
595 	HRCWH_CORE_ENABLE |\
596 	HRCWH_FROM_0X00000100 |\
597 	HRCWH_BOOTSEQ_DISABLE |\
598 	HRCWH_SW_WATCHDOG_DISABLE |\
599 	HRCWH_ROM_LOC_LOCAL_16BIT |\
600 	HRCWH_TSEC1M_IN_GMII |\
601 	HRCWH_TSEC2M_IN_GMII )
602 #endif
603 
604 /* System IO Config */
605 #define CFG_SICRH SICRH_TSOBI1
606 #define CFG_SICRL SICRL_LDP_A
607 
608 #define CFG_HID0_INIT	0x000000000
609 #define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
610 
611 /* #define CFG_HID0_FINAL		(\
612 	HID0_ENABLE_INSTRUCTION_CACHE |\
613 	HID0_ENABLE_M_BIT |\
614 	HID0_ENABLE_ADDRESS_BROADCAST ) */
615 
616 
617 #define CFG_HID2 HID2_HBE
618 
619 /* DDR @ 0x00000000 */
620 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
621 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
622 
623 /* PCI @ 0x80000000 */
624 #ifdef CONFIG_PCI
625 #define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
626 #define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
627 #define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
628 #define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
629 #else
630 #define CFG_IBAT1L	(0)
631 #define CFG_IBAT1U	(0)
632 #define CFG_IBAT2L	(0)
633 #define CFG_IBAT2U	(0)
634 #endif
635 
636 #ifdef CONFIG_MPC83XX_PCI2
637 #define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
638 #define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
639 #define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
640 #define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
641 #else
642 #define CFG_IBAT3L	(0)
643 #define CFG_IBAT3U	(0)
644 #define CFG_IBAT4L	(0)
645 #define CFG_IBAT4U	(0)
646 #endif
647 
648 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
649 #define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
650 #define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
651 
652 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
653 #define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
654 #define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
655 
656 #define CFG_IBAT7L	(0)
657 #define CFG_IBAT7U	(0)
658 
659 #define CFG_DBAT0L	CFG_IBAT0L
660 #define CFG_DBAT0U	CFG_IBAT0U
661 #define CFG_DBAT1L	CFG_IBAT1L
662 #define CFG_DBAT1U	CFG_IBAT1U
663 #define CFG_DBAT2L	CFG_IBAT2L
664 #define CFG_DBAT2U	CFG_IBAT2U
665 #define CFG_DBAT3L	CFG_IBAT3L
666 #define CFG_DBAT3U	CFG_IBAT3U
667 #define CFG_DBAT4L	CFG_IBAT4L
668 #define CFG_DBAT4U	CFG_IBAT4U
669 #define CFG_DBAT5L	CFG_IBAT5L
670 #define CFG_DBAT5U	CFG_IBAT5U
671 #define CFG_DBAT6L	CFG_IBAT6L
672 #define CFG_DBAT6U	CFG_IBAT6U
673 #define CFG_DBAT7L	CFG_IBAT7L
674 #define CFG_DBAT7U	CFG_IBAT7U
675 
676 /*
677  * Internal Definitions
678  *
679  * Boot Flags
680  */
681 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
682 #define BOOTFLAG_WARM	0x02	/* Software reboot */
683 
684 #if defined(CONFIG_CMD_KGDB)
685 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
686 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
687 #endif
688 
689 /*
690  * Environment Configuration
691  */
692 #define CONFIG_ENV_OVERWRITE
693 
694 #if defined(CONFIG_TSEC_ENET)
695 #define CONFIG_ETHADDR		00:04:9f:ef:23:33
696 #define CONFIG_HAS_ETH1
697 #define CONFIG_HAS_ETH0
698 #define CONFIG_ETH1ADDR		00:E0:0C:00:7E:21
699 #endif
700 
701 #define CONFIG_IPADDR		192.168.1.253
702 
703 #define CONFIG_HOSTNAME		mpc8349emds
704 #define CONFIG_ROOTPATH		/nfsroot/rootfs
705 #define CONFIG_BOOTFILE		uImage
706 
707 #define CONFIG_SERVERIP		192.168.1.1
708 #define CONFIG_GATEWAYIP	192.168.1.1
709 #define CONFIG_NETMASK		255.255.255.0
710 
711 #define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
712 
713 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
714 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
715 
716 #define CONFIG_BAUDRATE	 115200
717 
718 #define CONFIG_PREBOOT	"echo;"	\
719 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
720 	"echo"
721 
722 #define	CONFIG_EXTRA_ENV_SETTINGS					\
723 	"netdev=eth0\0"							\
724 	"hostname=mpc8349emds\0"					\
725 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
726 		"nfsroot=${serverip}:${rootpath}\0"			\
727 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
728 	"addip=setenv bootargs ${bootargs} "				\
729 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
730 		":${hostname}:${netdev}:off panic=1\0"			\
731 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
732 	"flash_nfs=run nfsargs addip addtty;"				\
733 		"bootm ${kernel_addr}\0"				\
734 	"flash_self=run ramargs addip addtty;"				\
735 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
736 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
737 		"bootm\0"						\
738 	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
739 	"update=protect off fe000000 fe03ffff; "			\
740 		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"	\
741 	"upd=run load;run update\0"					\
742 	"fdtaddr=400000\0"						\
743 	"fdtfile=mpc8349emds.dtb\0"					\
744 	""
745 
746 #define CONFIG_NFSBOOTCOMMAND	                                        \
747    "setenv bootargs root=/dev/nfs rw "                                  \
748       "nfsroot=$serverip:$rootpath "                                    \
749       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
750       "console=$consoledev,$baudrate $othbootargs;"                     \
751    "tftp $loadaddr $bootfile;"                                          \
752    "tftp $fdtaddr $fdtfile;"						\
753    "bootm $loadaddr - $fdtaddr"
754 
755 #define CONFIG_RAMBOOTCOMMAND						\
756    "setenv bootargs root=/dev/ram rw "                                  \
757       "console=$consoledev,$baudrate $othbootargs;"                     \
758    "tftp $ramdiskaddr $ramdiskfile;"                                    \
759    "tftp $loadaddr $bootfile;"                                          \
760    "tftp $fdtaddr $fdtfile;"						\
761    "bootm $loadaddr $ramdiskaddr $fdtaddr"
762 
763 #define CONFIG_BOOTCOMMAND	"run flash_self"
764 
765 #endif	/* __CONFIG_H */
766