1 /* 2 * (C) Copyright 2006-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * mpc8349emds board configuration file 10 * 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 /* E300 Family */ 20 #define CONFIG_MPC834x 1 /* MPC834x family */ 21 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 22 23 #define CONFIG_SYS_TEXT_BASE 0xFE000000 24 25 #define CONFIG_PCI_66M 26 #ifdef CONFIG_PCI_66M 27 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 28 #else 29 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 30 #endif 31 32 #ifdef CONFIG_PCISLAVE 33 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 34 #endif /* CONFIG_PCISLAVE */ 35 36 #ifndef CONFIG_SYS_CLK_FREQ 37 #ifdef CONFIG_PCI_66M 38 #define CONFIG_SYS_CLK_FREQ 66000000 39 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 40 #else 41 #define CONFIG_SYS_CLK_FREQ 33000000 42 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 43 #endif 44 #endif 45 46 #define CONFIG_SYS_IMMR 0xE0000000 47 48 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 49 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 50 #define CONFIG_SYS_MEMTEST_END 0x00100000 51 52 /* 53 * DDR Setup 54 */ 55 #define CONFIG_DDR_ECC /* support DDR ECC function */ 56 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 57 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 58 59 /* 60 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver 61 * unselect it to use old spd_sdram.c 62 */ 63 #define CONFIG_SYS_SPD_BUS_NUM 0 64 #define SPD_EEPROM_ADDRESS1 0x52 65 #define SPD_EEPROM_ADDRESS2 0x51 66 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 67 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 69 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 70 71 /* 72 * 32-bit data path mode. 73 * 74 * Please note that using this mode for devices with the real density of 64-bit 75 * effectively reduces the amount of available memory due to the effect of 76 * wrapping around while translating address to row/columns, for example in the 77 * 256MB module the upper 128MB get aliased with contents of the lower 78 * 128MB); normally this define should be used for devices with real 32-bit 79 * data path. 80 */ 81 #undef CONFIG_DDR_32BIT 82 83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 85 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 86 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 87 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 88 #undef CONFIG_DDR_2T_TIMING 89 90 /* 91 * DDRCDR - DDR Control Driver Register 92 */ 93 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 94 95 #if defined(CONFIG_SPD_EEPROM) 96 /* 97 * Determine DDR configuration from I2C interface. 98 */ 99 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 100 #else 101 /* 102 * Manually set up DDR parameters 103 */ 104 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 105 #if defined(CONFIG_DDR_II) 106 #define CONFIG_SYS_DDRCDR 0x80080001 107 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 108 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 109 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 110 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 111 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 112 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 113 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 114 #define CONFIG_SYS_DDR_MODE 0x47d00432 115 #define CONFIG_SYS_DDR_MODE2 0x8000c000 116 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 117 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 118 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 119 #else 120 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 121 | CSCONFIG_ROW_BIT_13 \ 122 | CSCONFIG_COL_BIT_10) 123 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 124 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 125 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 126 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 127 128 #if defined(CONFIG_DDR_32BIT) 129 /* set burst length to 8 for 32-bit data path */ 130 /* DLL,normal,seq,4/2.5, 8 burst len */ 131 #define CONFIG_SYS_DDR_MODE 0x00000023 132 #else 133 /* the default burst length is 4 - for 64-bit data path */ 134 /* DLL,normal,seq,4/2.5, 4 burst len */ 135 #define CONFIG_SYS_DDR_MODE 0x00000022 136 #endif 137 #endif 138 #endif 139 140 /* 141 * SDRAM on the Local Bus 142 */ 143 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 144 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 145 146 /* 147 * FLASH on the Local Bus 148 */ 149 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 150 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 151 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 152 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 153 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 154 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 155 156 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 157 | BR_PS_16 /* 16 bit port */ \ 158 | BR_MS_GPCM /* MSEL = GPCM */ \ 159 | BR_V) /* valid */ 160 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 161 | OR_UPM_XAM \ 162 | OR_GPCM_CSNT \ 163 | OR_GPCM_ACS_DIV2 \ 164 | OR_GPCM_XACS \ 165 | OR_GPCM_SCY_15 \ 166 | OR_GPCM_TRLX_SET \ 167 | OR_GPCM_EHTR_SET \ 168 | OR_GPCM_EAD) 169 170 /* window base at flash base */ 171 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 172 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 173 174 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 175 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 176 177 #undef CONFIG_SYS_FLASH_CHECKSUM 178 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 179 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 180 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 182 183 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 184 #define CONFIG_SYS_RAMBOOT 185 #else 186 #undef CONFIG_SYS_RAMBOOT 187 #endif 188 189 /* 190 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 191 */ 192 #define CONFIG_SYS_BCSR 0xE2400000 193 /* Access window base at BCSR base */ 194 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 195 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 196 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 197 | BR_PS_8 \ 198 | BR_MS_GPCM \ 199 | BR_V) 200 /* 0x00000801 */ 201 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 202 | OR_GPCM_XAM \ 203 | OR_GPCM_CSNT \ 204 | OR_GPCM_SCY_15 \ 205 | OR_GPCM_TRLX_CLEAR \ 206 | OR_GPCM_EHTR_CLEAR) 207 /* 0xFFFFE8F0 */ 208 209 #define CONFIG_SYS_INIT_RAM_LOCK 1 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 211 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 212 213 #define CONFIG_SYS_GBL_DATA_OFFSET \ 214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 216 217 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 218 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 219 220 /* 221 * Local Bus LCRR and LBCR regs 222 * LCRR: DLL bypass, Clock divider is 4 223 * External Local Bus rate is 224 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 225 */ 226 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 227 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 228 #define CONFIG_SYS_LBC_LBCR 0x00000000 229 230 /* 231 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 232 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 233 */ 234 #undef CONFIG_SYS_LB_SDRAM 235 236 #ifdef CONFIG_SYS_LB_SDRAM 237 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 238 /* 239 * Base Register 2 and Option Register 2 configure SDRAM. 240 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 241 * 242 * For BR2, need: 243 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 244 * port-size = 32-bits = BR2[19:20] = 11 245 * no parity checking = BR2[21:22] = 00 246 * SDRAM for MSEL = BR2[24:26] = 011 247 * Valid = BR[31] = 1 248 * 249 * 0 4 8 12 16 20 24 28 250 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 251 */ 252 253 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 254 | BR_PS_32 /* 32-bit port */ \ 255 | BR_MS_SDRAM /* MSEL = SDRAM */ \ 256 | BR_V) /* Valid */ 257 /* 0xF0001861 */ 258 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 259 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 260 261 /* 262 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 263 * 264 * For OR2, need: 265 * 64MB mask for AM, OR2[0:7] = 1111 1100 266 * XAM, OR2[17:18] = 11 267 * 9 columns OR2[19-21] = 010 268 * 13 rows OR2[23-25] = 100 269 * EAD set for extra time OR[31] = 1 270 * 271 * 0 4 8 12 16 20 24 28 272 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 273 */ 274 275 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ 276 | OR_SDRAM_XAM \ 277 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 278 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 279 | OR_SDRAM_EAD) 280 /* 0xFC006901 */ 281 282 /* LB sdram refresh timer, about 6us */ 283 #define CONFIG_SYS_LBC_LSRT 0x32000000 284 /* LB refresh timer prescal, 266MHz/32 */ 285 #define CONFIG_SYS_LBC_MRTPR 0x20000000 286 287 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 288 | LSDMR_BSMA1516 \ 289 | LSDMR_RFCR8 \ 290 | LSDMR_PRETOACT6 \ 291 | LSDMR_ACTTORW3 \ 292 | LSDMR_BL8 \ 293 | LSDMR_WRC3 \ 294 | LSDMR_CL3) 295 296 /* 297 * SDRAM Controller configuration sequence. 298 */ 299 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 300 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 301 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 302 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 303 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 304 #endif 305 306 /* 307 * Serial Port 308 */ 309 #define CONFIG_CONS_INDEX 1 310 #define CONFIG_SYS_NS16550_SERIAL 311 #define CONFIG_SYS_NS16550_REG_SIZE 1 312 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 313 314 #define CONFIG_SYS_BAUDRATE_TABLE \ 315 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 316 317 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 318 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 319 320 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 321 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 322 323 /* I2C */ 324 #define CONFIG_SYS_I2C 325 #define CONFIG_SYS_I2C_FSL 326 #define CONFIG_SYS_FSL_I2C_SPEED 400000 327 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 328 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 329 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 330 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 331 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 332 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 333 334 /* SPI */ 335 #define CONFIG_MPC8XXX_SPI 336 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 337 338 /* GPIOs. Used as SPI chip selects */ 339 #define CONFIG_SYS_GPIO1_PRELIM 340 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 341 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 342 343 /* TSEC */ 344 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 345 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 346 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 347 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 348 349 /* USB */ 350 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 351 352 /* 353 * General PCI 354 * Addresses are mapped 1-1. 355 */ 356 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 357 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 358 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 359 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 360 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 361 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 362 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 363 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 364 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 365 366 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 367 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 368 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 369 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 370 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 371 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 372 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 373 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 374 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 375 376 #if defined(CONFIG_PCI) 377 378 #define PCI_ONE_PCI1 379 #if defined(PCI_64BIT) 380 #undef PCI_ALL_PCI1 381 #undef PCI_TWO_PCI1 382 #undef PCI_ONE_PCI1 383 #endif 384 385 #define CONFIG_83XX_PCI_STREAMING 386 387 #undef CONFIG_EEPRO100 388 #undef CONFIG_TULIP 389 390 #if !defined(CONFIG_PCI_PNP) 391 #define PCI_ENET0_IOADDR 0xFIXME 392 #define PCI_ENET0_MEMADDR 0xFIXME 393 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 394 #endif 395 396 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 397 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 398 399 #endif /* CONFIG_PCI */ 400 401 /* 402 * TSEC configuration 403 */ 404 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 405 406 #if defined(CONFIG_TSEC_ENET) 407 408 #define CONFIG_GMII 1 /* MII PHY management */ 409 #define CONFIG_TSEC1 1 410 #define CONFIG_TSEC1_NAME "TSEC0" 411 #define CONFIG_TSEC2 1 412 #define CONFIG_TSEC2_NAME "TSEC1" 413 #define TSEC1_PHY_ADDR 0 414 #define TSEC2_PHY_ADDR 1 415 #define TSEC1_PHYIDX 0 416 #define TSEC2_PHYIDX 0 417 #define TSEC1_FLAGS TSEC_GIGABIT 418 #define TSEC2_FLAGS TSEC_GIGABIT 419 420 /* Options are: TSEC[0-1] */ 421 #define CONFIG_ETHPRIME "TSEC0" 422 423 #endif /* CONFIG_TSEC_ENET */ 424 425 /* 426 * Configure on-board RTC 427 */ 428 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 429 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 430 431 /* 432 * Environment 433 */ 434 #ifndef CONFIG_SYS_RAMBOOT 435 #define CONFIG_ENV_ADDR \ 436 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 437 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 438 #define CONFIG_ENV_SIZE 0x2000 439 440 /* Address and size of Redundant Environment Sector */ 441 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 442 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 443 444 #else 445 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 446 #define CONFIG_ENV_SIZE 0x2000 447 #endif 448 449 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 450 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 451 452 /* 453 * BOOTP options 454 */ 455 #define CONFIG_BOOTP_BOOTFILESIZE 456 #define CONFIG_BOOTP_BOOTPATH 457 #define CONFIG_BOOTP_GATEWAY 458 #define CONFIG_BOOTP_HOSTNAME 459 460 /* 461 * Command line configuration. 462 */ 463 464 #undef CONFIG_WATCHDOG /* watchdog disabled */ 465 466 /* 467 * Miscellaneous configurable options 468 */ 469 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 470 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 471 472 /* 473 * For booting Linux, the board info and command line data 474 * have to be in the first 256 MB of memory, since this is 475 * the maximum mapped by the Linux kernel during initialization. 476 */ 477 /* Initial Memory map for Linux*/ 478 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 479 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 480 481 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 482 483 #if 1 /*528/264*/ 484 #define CONFIG_SYS_HRCW_LOW (\ 485 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 486 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 487 HRCWL_CSB_TO_CLKIN |\ 488 HRCWL_VCO_1X2 |\ 489 HRCWL_CORE_TO_CSB_2X1) 490 #elif 0 /*396/132*/ 491 #define CONFIG_SYS_HRCW_LOW (\ 492 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 493 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 494 HRCWL_CSB_TO_CLKIN |\ 495 HRCWL_VCO_1X4 |\ 496 HRCWL_CORE_TO_CSB_3X1) 497 #elif 0 /*264/132*/ 498 #define CONFIG_SYS_HRCW_LOW (\ 499 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 500 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 501 HRCWL_CSB_TO_CLKIN |\ 502 HRCWL_VCO_1X4 |\ 503 HRCWL_CORE_TO_CSB_2X1) 504 #elif 0 /*132/132*/ 505 #define CONFIG_SYS_HRCW_LOW (\ 506 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 507 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 508 HRCWL_CSB_TO_CLKIN |\ 509 HRCWL_VCO_1X4 |\ 510 HRCWL_CORE_TO_CSB_1X1) 511 #elif 0 /*264/264 */ 512 #define CONFIG_SYS_HRCW_LOW (\ 513 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 514 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 515 HRCWL_CSB_TO_CLKIN |\ 516 HRCWL_VCO_1X4 |\ 517 HRCWL_CORE_TO_CSB_1X1) 518 #endif 519 520 #ifdef CONFIG_PCISLAVE 521 #define CONFIG_SYS_HRCW_HIGH (\ 522 HRCWH_PCI_AGENT |\ 523 HRCWH_64_BIT_PCI |\ 524 HRCWH_PCI1_ARBITER_DISABLE |\ 525 HRCWH_PCI2_ARBITER_DISABLE |\ 526 HRCWH_CORE_ENABLE |\ 527 HRCWH_FROM_0X00000100 |\ 528 HRCWH_BOOTSEQ_DISABLE |\ 529 HRCWH_SW_WATCHDOG_DISABLE |\ 530 HRCWH_ROM_LOC_LOCAL_16BIT |\ 531 HRCWH_TSEC1M_IN_GMII |\ 532 HRCWH_TSEC2M_IN_GMII) 533 #else 534 #if defined(PCI_64BIT) 535 #define CONFIG_SYS_HRCW_HIGH (\ 536 HRCWH_PCI_HOST |\ 537 HRCWH_64_BIT_PCI |\ 538 HRCWH_PCI1_ARBITER_ENABLE |\ 539 HRCWH_PCI2_ARBITER_DISABLE |\ 540 HRCWH_CORE_ENABLE |\ 541 HRCWH_FROM_0X00000100 |\ 542 HRCWH_BOOTSEQ_DISABLE |\ 543 HRCWH_SW_WATCHDOG_DISABLE |\ 544 HRCWH_ROM_LOC_LOCAL_16BIT |\ 545 HRCWH_TSEC1M_IN_GMII |\ 546 HRCWH_TSEC2M_IN_GMII) 547 #else 548 #define CONFIG_SYS_HRCW_HIGH (\ 549 HRCWH_PCI_HOST |\ 550 HRCWH_32_BIT_PCI |\ 551 HRCWH_PCI1_ARBITER_ENABLE |\ 552 HRCWH_PCI2_ARBITER_ENABLE |\ 553 HRCWH_CORE_ENABLE |\ 554 HRCWH_FROM_0X00000100 |\ 555 HRCWH_BOOTSEQ_DISABLE |\ 556 HRCWH_SW_WATCHDOG_DISABLE |\ 557 HRCWH_ROM_LOC_LOCAL_16BIT |\ 558 HRCWH_TSEC1M_IN_GMII |\ 559 HRCWH_TSEC2M_IN_GMII) 560 #endif /* PCI_64BIT */ 561 #endif /* CONFIG_PCISLAVE */ 562 563 /* 564 * System performance 565 */ 566 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 567 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 568 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 569 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 570 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 571 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 572 573 /* System IO Config */ 574 #define CONFIG_SYS_SICRH 0 575 #define CONFIG_SYS_SICRL SICRL_LDP_A 576 577 #define CONFIG_SYS_HID0_INIT 0x000000000 578 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 579 | HID0_ENABLE_INSTRUCTION_CACHE) 580 581 /* #define CONFIG_SYS_HID0_FINAL (\ 582 HID0_ENABLE_INSTRUCTION_CACHE |\ 583 HID0_ENABLE_M_BIT |\ 584 HID0_ENABLE_ADDRESS_BROADCAST) */ 585 586 #define CONFIG_SYS_HID2 HID2_HBE 587 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 588 589 /* DDR @ 0x00000000 */ 590 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 591 | BATL_PP_RW \ 592 | BATL_MEMCOHERENCE) 593 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 594 | BATU_BL_256M \ 595 | BATU_VS \ 596 | BATU_VP) 597 598 /* PCI @ 0x80000000 */ 599 #ifdef CONFIG_PCI 600 #define CONFIG_PCI_INDIRECT_BRIDGE 601 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 602 | BATL_PP_RW \ 603 | BATL_MEMCOHERENCE) 604 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 605 | BATU_BL_256M \ 606 | BATU_VS \ 607 | BATU_VP) 608 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 609 | BATL_PP_RW \ 610 | BATL_CACHEINHIBIT \ 611 | BATL_GUARDEDSTORAGE) 612 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 613 | BATU_BL_256M \ 614 | BATU_VS \ 615 | BATU_VP) 616 #else 617 #define CONFIG_SYS_IBAT1L (0) 618 #define CONFIG_SYS_IBAT1U (0) 619 #define CONFIG_SYS_IBAT2L (0) 620 #define CONFIG_SYS_IBAT2U (0) 621 #endif 622 623 #ifdef CONFIG_MPC83XX_PCI2 624 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 625 | BATL_PP_RW \ 626 | BATL_MEMCOHERENCE) 627 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 628 | BATU_BL_256M \ 629 | BATU_VS \ 630 | BATU_VP) 631 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 632 | BATL_PP_RW \ 633 | BATL_CACHEINHIBIT \ 634 | BATL_GUARDEDSTORAGE) 635 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 636 | BATU_BL_256M \ 637 | BATU_VS \ 638 | BATU_VP) 639 #else 640 #define CONFIG_SYS_IBAT3L (0) 641 #define CONFIG_SYS_IBAT3U (0) 642 #define CONFIG_SYS_IBAT4L (0) 643 #define CONFIG_SYS_IBAT4U (0) 644 #endif 645 646 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 647 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 648 | BATL_PP_RW \ 649 | BATL_CACHEINHIBIT \ 650 | BATL_GUARDEDSTORAGE) 651 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 652 | BATU_BL_256M \ 653 | BATU_VS \ 654 | BATU_VP) 655 656 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 657 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 658 | BATL_PP_RW \ 659 | BATL_MEMCOHERENCE \ 660 | BATL_GUARDEDSTORAGE) 661 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 662 | BATU_BL_256M \ 663 | BATU_VS \ 664 | BATU_VP) 665 666 #define CONFIG_SYS_IBAT7L (0) 667 #define CONFIG_SYS_IBAT7U (0) 668 669 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 670 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 671 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 672 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 673 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 674 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 675 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 676 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 677 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 678 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 679 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 680 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 681 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 682 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 683 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 684 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 685 686 #if defined(CONFIG_CMD_KGDB) 687 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 688 #endif 689 690 /* 691 * Environment Configuration 692 */ 693 #define CONFIG_ENV_OVERWRITE 694 695 #if defined(CONFIG_TSEC_ENET) 696 #define CONFIG_HAS_ETH1 697 #define CONFIG_HAS_ETH0 698 #endif 699 700 #define CONFIG_HOSTNAME mpc8349emds 701 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 702 #define CONFIG_BOOTFILE "uImage" 703 704 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 705 706 #define CONFIG_PREBOOT "echo;" \ 707 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 708 "echo" 709 710 #define CONFIG_EXTRA_ENV_SETTINGS \ 711 "netdev=eth0\0" \ 712 "hostname=mpc8349emds\0" \ 713 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 714 "nfsroot=${serverip}:${rootpath}\0" \ 715 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 716 "addip=setenv bootargs ${bootargs} " \ 717 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 718 ":${hostname}:${netdev}:off panic=1\0" \ 719 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 720 "flash_nfs=run nfsargs addip addtty;" \ 721 "bootm ${kernel_addr}\0" \ 722 "flash_self=run ramargs addip addtty;" \ 723 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 724 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 725 "bootm\0" \ 726 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 727 "update=protect off fe000000 fe03ffff; " \ 728 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 729 "upd=run load update\0" \ 730 "fdtaddr=780000\0" \ 731 "fdtfile=mpc834x_mds.dtb\0" \ 732 "" 733 734 #define CONFIG_NFSBOOTCOMMAND \ 735 "setenv bootargs root=/dev/nfs rw " \ 736 "nfsroot=$serverip:$rootpath " \ 737 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 738 "$netdev:off " \ 739 "console=$consoledev,$baudrate $othbootargs;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr - $fdtaddr" 743 744 #define CONFIG_RAMBOOTCOMMAND \ 745 "setenv bootargs root=/dev/ram rw " \ 746 "console=$consoledev,$baudrate $othbootargs;" \ 747 "tftp $ramdiskaddr $ramdiskfile;" \ 748 "tftp $loadaddr $bootfile;" \ 749 "tftp $fdtaddr $fdtfile;" \ 750 "bootm $loadaddr $ramdiskaddr $fdtaddr" 751 752 #define CONFIG_BOOTCOMMAND "run flash_self" 753 754 #endif /* __CONFIG_H */ 755