1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  */
19 
20 #ifndef __CONFIG_H
21 #define __CONFIG_H
22 
23 /*
24  * High Level Configuration Options
25  */
26 #define CONFIG_E300		1	/* E300 family */
27 #define CONFIG_QE		1	/* Has QE */
28 #define CONFIG_MPC83XX		1	/* MPC83xx family */
29 #define CONFIG_MPC832X		1	/* MPC832x CPU specific */
30 #define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
31 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
32 #undef CONFIG_PQ_MDS_PIB_ATM	/* QOC3 ATM card */
33 
34 /*
35  * System Clock Setup
36  */
37 #ifdef CONFIG_PCISLAVE
38 #define CONFIG_83XX_PCICLK	66000000	/* in HZ */
39 #else
40 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
41 #endif
42 
43 #ifndef CONFIG_SYS_CLK_FREQ
44 #define CONFIG_SYS_CLK_FREQ	66000000
45 #endif
46 
47 /*
48  * Hardware Reset Configuration Word
49  */
50 #define CONFIG_SYS_HRCW_LOW (\
51 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
53 	HRCWL_VCO_1X2 |\
54 	HRCWL_CSB_TO_CLKIN_2X1 |\
55 	HRCWL_CORE_TO_CSB_2X1 |\
56 	HRCWL_CE_PLL_VCO_DIV_2 |\
57 	HRCWL_CE_PLL_DIV_1X1 |\
58 	HRCWL_CE_TO_PLL_1X3)
59 
60 #ifdef CONFIG_PCISLAVE
61 #define CONFIG_SYS_HRCW_HIGH (\
62 	HRCWH_PCI_AGENT |\
63 	HRCWH_PCI1_ARBITER_DISABLE |\
64 	HRCWH_CORE_ENABLE |\
65 	HRCWH_FROM_0XFFF00100 |\
66 	HRCWH_BOOTSEQ_DISABLE |\
67 	HRCWH_SW_WATCHDOG_DISABLE |\
68 	HRCWH_ROM_LOC_LOCAL_16BIT |\
69 	HRCWH_BIG_ENDIAN |\
70 	HRCWH_LALE_NORMAL)
71 #else
72 #define CONFIG_SYS_HRCW_HIGH (\
73 	HRCWH_PCI_HOST |\
74 	HRCWH_PCI1_ARBITER_ENABLE |\
75 	HRCWH_CORE_ENABLE |\
76 	HRCWH_FROM_0X00000100 |\
77 	HRCWH_BOOTSEQ_DISABLE |\
78 	HRCWH_SW_WATCHDOG_DISABLE |\
79 	HRCWH_ROM_LOC_LOCAL_16BIT |\
80 	HRCWH_BIG_ENDIAN |\
81 	HRCWH_LALE_NORMAL)
82 #endif
83 
84 /*
85  * System IO Config
86  */
87 #define CONFIG_SYS_SICRL		0x00000000
88 
89 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
90 #define CONFIG_BOARD_EARLY_INIT_R
91 
92 /*
93  * IMMR new address
94  */
95 #define CONFIG_SYS_IMMR		0xE0000000
96 
97 /*
98  * DDR Setup
99  */
100 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory */
101 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
102 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
104 
105 #undef CONFIG_SPD_EEPROM
106 #if defined(CONFIG_SPD_EEPROM)
107 /* Determine DDR configuration from I2C interface
108  */
109 #define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
110 #else
111 /* Manually set up DDR parameters
112  */
113 #define CONFIG_SYS_DDR_SIZE		128	/* MB */
114 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80840102
115 #define CONFIG_SYS_DDR_TIMING_0	0x00220802
116 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
117 #define CONFIG_SYS_DDR_TIMING_2	0x0f9048ca
118 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
119 #define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
120 #define CONFIG_SYS_DDR_MODE		0x44400232
121 #define CONFIG_SYS_DDR_MODE2		0x8000c000
122 #define CONFIG_SYS_DDR_INTERVAL	0x03200064
123 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
124 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43080000
125 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
126 #endif
127 
128 /*
129  * Memory test
130  */
131 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
132 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
133 #define CONFIG_SYS_MEMTEST_END		0x00100000
134 
135 /*
136  * The reserved memory
137  */
138 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
139 
140 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
141 #define CONFIG_SYS_RAMBOOT
142 #else
143 #undef  CONFIG_SYS_RAMBOOT
144 #endif
145 
146 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
147 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
148 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
149 
150 /*
151  * Initial RAM Base Address Setup
152  */
153 #define CONFIG_SYS_INIT_RAM_LOCK	1
154 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
155 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM */
156 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
157 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
158 
159 /*
160  * Local Bus Configuration & Clock Setup
161  */
162 #define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
163 #define CONFIG_SYS_LBC_LBCR		0x00000000
164 
165 /*
166  * FLASH on the Local Bus
167  */
168 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
169 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
170 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* FLASH base address */
171 #define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
172 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
173 
174 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
175 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
176 
177 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* Flash Base address */ \
178 			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
179 			BR_V)			/* valid */
180 #define CONFIG_SYS_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
181 
182 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
183 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
184 
185 #undef CONFIG_SYS_FLASH_CHECKSUM
186 
187 /*
188  * BCSR on the Local Bus
189  */
190 #define CONFIG_SYS_BCSR		0xF8000000
191 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR	/* Access window base at BCSR base */
192 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* Access window size 32K */
193 
194 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)	/* Port size=8bit, MSEL=GPCM */
195 #define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
196 
197 /*
198  * SDRAM on the Local Bus
199  */
200 #undef CONFIG_SYS_LB_SDRAM		/* The board has not SRDAM on local bus */
201 
202 #ifdef CONFIG_SYS_LB_SDRAM
203 #define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
204 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
205 
206 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
207 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
208 
209 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
210 /*
211  * Base Register 2 and Option Register 2 configure SDRAM.
212  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
213  *
214  * For BR2, need:
215  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
216  *    port size = 32-bits = BR2[19:20] = 11
217  *    no parity checking = BR2[21:22] = 00
218  *    SDRAM for MSEL = BR2[24:26] = 011
219  *    Valid = BR[31] = 1
220  *
221  * 0    4    8    12   16   20   24   28
222  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
223  *
224  * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
225  * the top 17 bits of BR2.
226  */
227 
228 #define CONFIG_SYS_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
229 
230 /*
231  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
232  *
233  * For OR2, need:
234  *    64MB mask for AM, OR2[0:7] = 1111 1100
235  *                 XAM, OR2[17:18] = 11
236  *    9 columns OR2[19-21] = 010
237  *    13 rows   OR2[23-25] = 100
238  *    EAD set for extra time OR[31] = 1
239  *
240  * 0    4    8    12   16   20   24   28
241  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
242  */
243 
244 #define CONFIG_SYS_OR2_PRELIM	0xfc006901
245 
246 #define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
247 #define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
248 
249 /*
250  * LSDMR masks
251  */
252 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
253 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
254 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
255 #define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
256 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
257 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
258 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
259 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
260 
261 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
262 
263 /*
264  * SDRAM Controller configuration sequence.
265  */
266 #define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
267 				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
268 #define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
269 				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
270 #define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
271 				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
272 #define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
273 				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
274 #define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
275 				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
276 
277 #endif
278 
279 /*
280  * Windows to access PIB via local bus
281  */
282 #define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
283 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
284 
285 /*
286  * CS2 on Local Bus, to PIB
287  */
288 #define CONFIG_SYS_BR2_PRELIM	0xf8008801	/* CS2 base address at 0xf8008000 */
289 #define CONFIG_SYS_OR2_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
290 
291 /*
292  * CS3 on Local Bus, to PIB
293  */
294 #define CONFIG_SYS_BR3_PRELIM	0xf8010801	/* CS3 base address at 0xf8010000 */
295 #define CONFIG_SYS_OR3_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
296 
297 /*
298  * Serial Port
299  */
300 #define CONFIG_CONS_INDEX	1
301 #undef CONFIG_SERIAL_SOFTWARE_FIFO
302 #define CONFIG_SYS_NS16550
303 #define CONFIG_SYS_NS16550_SERIAL
304 #define CONFIG_SYS_NS16550_REG_SIZE	1
305 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
306 
307 #define CONFIG_SYS_BAUDRATE_TABLE  \
308 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
309 
310 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
311 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
312 
313 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
314 /* Use the HUSH parser */
315 #define CONFIG_SYS_HUSH_PARSER
316 #ifdef CONFIG_SYS_HUSH_PARSER
317 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
318 #endif
319 
320 /* pass open firmware flat tree */
321 #define CONFIG_OF_LIBFDT	1
322 #define CONFIG_OF_BOARD_SETUP	1
323 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
324 
325 /* I2C */
326 #define CONFIG_HARD_I2C		/* I2C with hardware support */
327 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
328 #define CONFIG_FSL_I2C
329 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
330 #define CONFIG_SYS_I2C_SLAVE	0x7F
331 #define CONFIG_SYS_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
332 #define CONFIG_SYS_I2C_OFFSET	0x3000
333 
334 /*
335  * Config on-board RTC
336  */
337 #define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
338 #define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
339 
340 /*
341  * General PCI
342  * Addresses are mapped 1-1.
343  */
344 #define CONFIG_SYS_PCI_MEM_BASE	0x80000000
345 #define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
346 #define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
347 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
348 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
349 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
350 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
351 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
352 #define CONFIG_SYS_PCI_IO_SIZE		0x100000	/* 1M */
353 
354 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
355 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
356 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
357 
358 
359 #ifdef CONFIG_PCI
360 
361 #define CONFIG_NET_MULTI
362 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
363 
364 #undef CONFIG_EEPRO100
365 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
366 #define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
367 
368 #endif	/* CONFIG_PCI */
369 
370 
371 #ifndef CONFIG_NET_MULTI
372 #define CONFIG_NET_MULTI	1
373 #endif
374 
375 /*
376  * QE UEC ethernet configuration
377  */
378 #define CONFIG_UEC_ETH
379 #define CONFIG_ETHPRIME		"FSL UEC0"
380 
381 #define CONFIG_UEC_ETH1		/* ETH3 */
382 
383 #ifdef CONFIG_UEC_ETH1
384 #define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
385 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
386 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
387 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
388 #define CONFIG_SYS_UEC1_PHY_ADDR	3
389 #define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
390 #endif
391 
392 #define CONFIG_UEC_ETH2		/* ETH4 */
393 
394 #ifdef CONFIG_UEC_ETH2
395 #define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
396 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
397 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
398 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
399 #define CONFIG_SYS_UEC2_PHY_ADDR	4
400 #define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
401 #endif
402 
403 /*
404  * Environment
405  */
406 #ifndef CONFIG_SYS_RAMBOOT
407 	#define CONFIG_ENV_IS_IN_FLASH	1
408 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
409 	#define CONFIG_ENV_SECT_SIZE	0x20000
410 	#define CONFIG_ENV_SIZE		0x2000
411 #else
412 	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
413 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
414 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
415 	#define CONFIG_ENV_SIZE		0x2000
416 #endif
417 
418 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
419 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
420 
421 /*
422  * BOOTP options
423  */
424 #define CONFIG_BOOTP_BOOTFILESIZE
425 #define CONFIG_BOOTP_BOOTPATH
426 #define CONFIG_BOOTP_GATEWAY
427 #define CONFIG_BOOTP_HOSTNAME
428 
429 
430 /*
431  * Command line configuration.
432  */
433 #include <config_cmd_default.h>
434 
435 #define CONFIG_CMD_PING
436 #define CONFIG_CMD_I2C
437 #define CONFIG_CMD_ASKENV
438 
439 #if defined(CONFIG_PCI)
440     #define CONFIG_CMD_PCI
441 #endif
442 
443 #if defined(CONFIG_SYS_RAMBOOT)
444     #undef CONFIG_CMD_SAVEENV
445     #undef CONFIG_CMD_LOADS
446 #endif
447 
448 
449 #undef CONFIG_WATCHDOG		/* watchdog disabled */
450 
451 /*
452  * Miscellaneous configurable options
453  */
454 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
455 #define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
456 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
457 
458 #if defined(CONFIG_CMD_KGDB)
459 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
460 #else
461 	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
462 #endif
463 
464 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
465 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
466 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
467 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
468 
469 /*
470  * For booting Linux, the board info and command line data
471  * have to be in the first 8 MB of memory, since this is
472  * the maximum mapped by the Linux kernel during initialization.
473  */
474 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
475 
476 /*
477  * Core HID Setup
478  */
479 #define CONFIG_SYS_HID0_INIT		0x000000000
480 #define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
481 #define CONFIG_SYS_HID2		HID2_HBE
482 
483 /*
484  * MMU Setup
485  */
486 
487 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
488 
489 /* DDR: cache cacheable */
490 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
491 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
492 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
493 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
494 
495 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
496 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
497 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
498 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
499 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
500 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
501 
502 /* BCSR: cache-inhibit and guarded */
503 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
504 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
505 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
506 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
507 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
508 
509 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
510 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
511 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
512 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
513 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
514 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
515 
516 #define CONFIG_SYS_IBAT4L	(0)
517 #define CONFIG_SYS_IBAT4U	(0)
518 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
519 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
520 
521 /* Stack in dcache: cacheable, no memory coherence */
522 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
523 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
524 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
525 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
526 
527 #ifdef CONFIG_PCI
528 /* PCI MEM space: cacheable */
529 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
530 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
531 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
532 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
533 /* PCI MMIO space: cache-inhibit and guarded */
534 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
535 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
536 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
537 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
538 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
539 #else
540 #define CONFIG_SYS_IBAT6L	(0)
541 #define CONFIG_SYS_IBAT6U	(0)
542 #define CONFIG_SYS_IBAT7L	(0)
543 #define CONFIG_SYS_IBAT7U	(0)
544 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
545 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
546 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
547 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
548 #endif
549 
550 /*
551  * Internal Definitions
552  *
553  * Boot Flags
554  */
555 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
556 #define BOOTFLAG_WARM	0x02	/* Software reboot */
557 
558 #if defined(CONFIG_CMD_KGDB)
559 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
560 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
561 #endif
562 
563 /*
564  * Environment Configuration
565  */
566 
567 #define CONFIG_ENV_OVERWRITE
568 
569 #if defined(CONFIG_UEC_ETH)
570 #define CONFIG_HAS_ETH0
571 #define CONFIG_ETHADDR	00:04:9f:ef:03:01
572 #define CONFIG_HAS_ETH1
573 #define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
574 #endif
575 
576 #define CONFIG_BAUDRATE	115200
577 
578 #define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
579 
580 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
581 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
582 
583 #define CONFIG_EXTRA_ENV_SETTINGS					\
584    "netdev=eth0\0"							\
585    "consoledev=ttyS0\0"							\
586    "ramdiskaddr=1000000\0"						\
587    "ramdiskfile=ramfs.83xx\0"						\
588    "fdtaddr=400000\0"							\
589    "fdtfile=mpc832x_mds.dtb\0"						\
590    ""
591 
592 #define CONFIG_NFSBOOTCOMMAND						\
593    "setenv bootargs root=/dev/nfs rw "					\
594       "nfsroot=$serverip:$rootpath "					\
595       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
596       "console=$consoledev,$baudrate $othbootargs;"			\
597    "tftp $loadaddr $bootfile;"						\
598    "tftp $fdtaddr $fdtfile;"						\
599    "bootm $loadaddr - $fdtaddr"
600 
601 #define CONFIG_RAMBOOTCOMMAND						\
602    "setenv bootargs root=/dev/ram rw "					\
603       "console=$consoledev,$baudrate $othbootargs;"			\
604    "tftp $ramdiskaddr $ramdiskfile;"					\
605    "tftp $loadaddr $bootfile;"						\
606    "tftp $fdtaddr $fdtfile;"						\
607    "bootm $loadaddr $ramdiskaddr $fdtaddr"
608 
609 
610 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
611 
612 #endif	/* __CONFIG_H */
613