1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_DISPLAY_BOARDINFO 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 18 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 /* 23 * System Clock Setup 24 */ 25 #ifdef CONFIG_PCISLAVE 26 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 27 #else 28 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 29 #endif 30 31 #ifndef CONFIG_SYS_CLK_FREQ 32 #define CONFIG_SYS_CLK_FREQ 66000000 33 #endif 34 35 /* 36 * Hardware Reset Configuration Word 37 */ 38 #define CONFIG_SYS_HRCW_LOW (\ 39 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 40 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 41 HRCWL_VCO_1X2 |\ 42 HRCWL_CSB_TO_CLKIN_2X1 |\ 43 HRCWL_CORE_TO_CSB_2X1 |\ 44 HRCWL_CE_PLL_VCO_DIV_2 |\ 45 HRCWL_CE_PLL_DIV_1X1 |\ 46 HRCWL_CE_TO_PLL_1X3) 47 48 #ifdef CONFIG_PCISLAVE 49 #define CONFIG_SYS_HRCW_HIGH (\ 50 HRCWH_PCI_AGENT |\ 51 HRCWH_PCI1_ARBITER_DISABLE |\ 52 HRCWH_CORE_ENABLE |\ 53 HRCWH_FROM_0XFFF00100 |\ 54 HRCWH_BOOTSEQ_DISABLE |\ 55 HRCWH_SW_WATCHDOG_DISABLE |\ 56 HRCWH_ROM_LOC_LOCAL_16BIT |\ 57 HRCWH_BIG_ENDIAN |\ 58 HRCWH_LALE_NORMAL) 59 #else 60 #define CONFIG_SYS_HRCW_HIGH (\ 61 HRCWH_PCI_HOST |\ 62 HRCWH_PCI1_ARBITER_ENABLE |\ 63 HRCWH_CORE_ENABLE |\ 64 HRCWH_FROM_0X00000100 |\ 65 HRCWH_BOOTSEQ_DISABLE |\ 66 HRCWH_SW_WATCHDOG_DISABLE |\ 67 HRCWH_ROM_LOC_LOCAL_16BIT |\ 68 HRCWH_BIG_ENDIAN |\ 69 HRCWH_LALE_NORMAL) 70 #endif 71 72 /* 73 * System IO Config 74 */ 75 #define CONFIG_SYS_SICRL 0x00000000 76 77 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 78 #define CONFIG_BOARD_EARLY_INIT_R 79 80 /* 81 * IMMR new address 82 */ 83 #define CONFIG_SYS_IMMR 0xE0000000 84 85 /* 86 * DDR Setup 87 */ 88 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 90 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 91 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 92 93 #undef CONFIG_SPD_EEPROM 94 #if defined(CONFIG_SPD_EEPROM) 95 /* Determine DDR configuration from I2C interface 96 */ 97 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 98 #else 99 /* Manually set up DDR parameters 100 */ 101 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 102 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 103 | CSCONFIG_AP \ 104 | CSCONFIG_ODT_WR_CFG \ 105 | CSCONFIG_ROW_BIT_13 \ 106 | CSCONFIG_COL_BIT_10) 107 /* 0x80840102 */ 108 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 109 | (0 << TIMING_CFG0_WRT_SHIFT) \ 110 | (0 << TIMING_CFG0_RRT_SHIFT) \ 111 | (0 << TIMING_CFG0_WWT_SHIFT) \ 112 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 113 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 114 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 115 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 116 /* 0x00220802 */ 117 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 118 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 119 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 120 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 121 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 122 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 123 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 124 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 125 /* 0x3935D322 */ 126 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 127 | (31 << TIMING_CFG2_CPO_SHIFT) \ 128 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 129 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 130 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 131 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 132 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) 133 /* 0x0F9048CA */ 134 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 135 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 136 /* 0x02000000 */ 137 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 138 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 139 /* 0x44400232 */ 140 #define CONFIG_SYS_DDR_MODE2 0x8000c000 141 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 142 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 143 /* 0x03200064 */ 144 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 145 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 147 | SDRAM_CFG_32_BE) 148 /* 0x43080000 */ 149 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 150 #endif 151 152 /* 153 * Memory test 154 */ 155 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 156 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 157 #define CONFIG_SYS_MEMTEST_END 0x00100000 158 159 /* 160 * The reserved memory 161 */ 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 163 164 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 165 #define CONFIG_SYS_RAMBOOT 166 #else 167 #undef CONFIG_SYS_RAMBOOT 168 #endif 169 170 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 171 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 172 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 173 174 /* 175 * Initial RAM Base Address Setup 176 */ 177 #define CONFIG_SYS_INIT_RAM_LOCK 1 178 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 180 #define CONFIG_SYS_GBL_DATA_OFFSET \ 181 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 182 183 /* 184 * Local Bus Configuration & Clock Setup 185 */ 186 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 187 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 188 #define CONFIG_SYS_LBC_LBCR 0x00000000 189 190 /* 191 * FLASH on the Local Bus 192 */ 193 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 194 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 195 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 196 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 197 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 198 199 /* Window base at flash base */ 200 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 201 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 202 203 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 204 | BR_PS_16 /* 16 bit port */ \ 205 | BR_MS_GPCM /* MSEL = GPCM */ \ 206 | BR_V) /* valid */ 207 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 208 | OR_GPCM_XAM \ 209 | OR_GPCM_CSNT \ 210 | OR_GPCM_ACS_DIV2 \ 211 | OR_GPCM_XACS \ 212 | OR_GPCM_SCY_15 \ 213 | OR_GPCM_TRLX_SET \ 214 | OR_GPCM_EHTR_SET \ 215 | OR_GPCM_EAD) 216 /* 0xfe006ff7 */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 220 221 #undef CONFIG_SYS_FLASH_CHECKSUM 222 223 /* 224 * BCSR on the Local Bus 225 */ 226 #define CONFIG_SYS_BCSR 0xF8000000 227 /* Access window base at BCSR base */ 228 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 229 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 230 231 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 232 | BR_PS_8 \ 233 | BR_MS_GPCM \ 234 | BR_V) 235 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 236 | OR_GPCM_XAM \ 237 | OR_GPCM_CSNT \ 238 | OR_GPCM_XACS \ 239 | OR_GPCM_SCY_15 \ 240 | OR_GPCM_TRLX_SET \ 241 | OR_GPCM_EHTR_SET \ 242 | OR_GPCM_EAD) 243 /* 0xFFFFE9F7 */ 244 245 /* 246 * Windows to access PIB via local bus 247 */ 248 /* PIB window base 0xF8008000 */ 249 #define CONFIG_SYS_PIB_BASE 0xF8008000 250 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) 251 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE 252 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 253 254 /* 255 * CS2 on Local Bus, to PIB 256 */ 257 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ 258 | BR_PS_8 \ 259 | BR_MS_GPCM \ 260 | BR_V) 261 /* 0xF8008801 */ 262 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 263 | OR_GPCM_XAM \ 264 | OR_GPCM_CSNT \ 265 | OR_GPCM_XACS \ 266 | OR_GPCM_SCY_15 \ 267 | OR_GPCM_TRLX_SET \ 268 | OR_GPCM_EHTR_SET \ 269 | OR_GPCM_EAD) 270 /* 0xffffe9f7 */ 271 272 /* 273 * CS3 on Local Bus, to PIB 274 */ 275 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ 276 CONFIG_SYS_PIB_WINDOW_SIZE) \ 277 | BR_PS_8 \ 278 | BR_MS_GPCM \ 279 | BR_V) 280 /* 0xF8010801 */ 281 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 282 | OR_GPCM_XAM \ 283 | OR_GPCM_CSNT \ 284 | OR_GPCM_XACS \ 285 | OR_GPCM_SCY_15 \ 286 | OR_GPCM_TRLX_SET \ 287 | OR_GPCM_EHTR_SET \ 288 | OR_GPCM_EAD) 289 /* 0xffffe9f7 */ 290 291 /* 292 * Serial Port 293 */ 294 #define CONFIG_CONS_INDEX 1 295 #define CONFIG_SYS_NS16550_SERIAL 296 #define CONFIG_SYS_NS16550_REG_SIZE 1 297 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 298 299 #define CONFIG_SYS_BAUDRATE_TABLE \ 300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 301 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 304 305 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 306 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 307 308 /* I2C */ 309 #define CONFIG_SYS_I2C 310 #define CONFIG_SYS_I2C_FSL 311 #define CONFIG_SYS_FSL_I2C_SPEED 400000 312 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 313 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 314 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 315 316 /* 317 * Config on-board RTC 318 */ 319 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 320 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 321 322 /* 323 * General PCI 324 * Addresses are mapped 1-1. 325 */ 326 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 327 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 328 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 329 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 330 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 331 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 332 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 333 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 334 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 335 336 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 337 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 338 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 339 340 #ifdef CONFIG_PCI 341 #define CONFIG_PCI_INDIRECT_BRIDGE 342 343 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 344 #define CONFIG_83XX_PCI_STREAMING 345 346 #undef CONFIG_EEPRO100 347 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 348 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 349 350 #endif /* CONFIG_PCI */ 351 352 /* 353 * QE UEC ethernet configuration 354 */ 355 #define CONFIG_UEC_ETH 356 #define CONFIG_ETHPRIME "UEC0" 357 358 #define CONFIG_UEC_ETH1 /* ETH3 */ 359 360 #ifdef CONFIG_UEC_ETH1 361 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 362 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 363 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 364 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 365 #define CONFIG_SYS_UEC1_PHY_ADDR 3 366 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 367 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 368 #endif 369 370 #define CONFIG_UEC_ETH2 /* ETH4 */ 371 372 #ifdef CONFIG_UEC_ETH2 373 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ 374 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 375 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 376 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 377 #define CONFIG_SYS_UEC2_PHY_ADDR 4 378 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 379 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 380 #endif 381 382 /* 383 * Environment 384 */ 385 #ifndef CONFIG_SYS_RAMBOOT 386 #define CONFIG_ENV_IS_IN_FLASH 1 387 #define CONFIG_ENV_ADDR \ 388 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 389 #define CONFIG_ENV_SECT_SIZE 0x20000 390 #define CONFIG_ENV_SIZE 0x2000 391 #else 392 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 393 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 394 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 395 #define CONFIG_ENV_SIZE 0x2000 396 #endif 397 398 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 399 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 400 401 /* 402 * BOOTP options 403 */ 404 #define CONFIG_BOOTP_BOOTFILESIZE 405 #define CONFIG_BOOTP_BOOTPATH 406 #define CONFIG_BOOTP_GATEWAY 407 #define CONFIG_BOOTP_HOSTNAME 408 409 /* 410 * Command line configuration. 411 */ 412 413 #if defined(CONFIG_PCI) 414 #define CONFIG_CMD_PCI 415 #endif 416 417 #undef CONFIG_WATCHDOG /* watchdog disabled */ 418 419 /* 420 * Miscellaneous configurable options 421 */ 422 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 423 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 424 425 #if defined(CONFIG_CMD_KGDB) 426 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 427 #else 428 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 429 #endif 430 431 /* Print Buffer Size */ 432 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 433 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 434 /* Boot Argument Buffer Size */ 435 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 436 437 /* 438 * For booting Linux, the board info and command line data 439 * have to be in the first 256 MB of memory, since this is 440 * the maximum mapped by the Linux kernel during initialization. 441 */ 442 /* Initial Memory map for Linux */ 443 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 444 445 /* 446 * Core HID Setup 447 */ 448 #define CONFIG_SYS_HID0_INIT 0x000000000 449 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 450 HID0_ENABLE_INSTRUCTION_CACHE) 451 #define CONFIG_SYS_HID2 HID2_HBE 452 453 /* 454 * MMU Setup 455 */ 456 457 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 458 459 /* DDR: cache cacheable */ 460 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 461 | BATL_PP_RW \ 462 | BATL_MEMCOHERENCE) 463 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 464 | BATU_BL_256M \ 465 | BATU_VS \ 466 | BATU_VP) 467 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 468 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 469 470 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 471 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 472 | BATL_PP_RW \ 473 | BATL_CACHEINHIBIT \ 474 | BATL_GUARDEDSTORAGE) 475 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 476 | BATU_BL_4M \ 477 | BATU_VS \ 478 | BATU_VP) 479 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 480 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 481 482 /* BCSR: cache-inhibit and guarded */ 483 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ 484 | BATL_PP_RW \ 485 | BATL_CACHEINHIBIT \ 486 | BATL_GUARDEDSTORAGE) 487 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ 488 | BATU_BL_128K \ 489 | BATU_VS \ 490 | BATU_VP) 491 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 492 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 493 494 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 495 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ 496 | BATL_PP_RW \ 497 | BATL_MEMCOHERENCE) 498 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ 499 | BATU_BL_32M \ 500 | BATU_VS \ 501 | BATU_VP) 502 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ 503 | BATL_PP_RW \ 504 | BATL_CACHEINHIBIT \ 505 | BATL_GUARDEDSTORAGE) 506 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 507 508 #define CONFIG_SYS_IBAT4L (0) 509 #define CONFIG_SYS_IBAT4U (0) 510 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 511 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 512 513 /* Stack in dcache: cacheable, no memory coherence */ 514 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 515 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 516 | BATU_BL_128K \ 517 | BATU_VS \ 518 | BATU_VP) 519 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 520 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 521 522 #ifdef CONFIG_PCI 523 /* PCI MEM space: cacheable */ 524 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ 525 | BATL_PP_RW \ 526 | BATL_MEMCOHERENCE) 527 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ 528 | BATU_BL_256M \ 529 | BATU_VS \ 530 | BATU_VP) 531 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 532 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 533 /* PCI MMIO space: cache-inhibit and guarded */ 534 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ 535 | BATL_PP_RW \ 536 | BATL_CACHEINHIBIT \ 537 | BATL_GUARDEDSTORAGE) 538 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ 539 | BATU_BL_256M \ 540 | BATU_VS \ 541 | BATU_VP) 542 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 543 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 544 #else 545 #define CONFIG_SYS_IBAT6L (0) 546 #define CONFIG_SYS_IBAT6U (0) 547 #define CONFIG_SYS_IBAT7L (0) 548 #define CONFIG_SYS_IBAT7U (0) 549 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 550 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 551 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 552 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 553 #endif 554 555 #if defined(CONFIG_CMD_KGDB) 556 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 557 #endif 558 559 /* 560 * Environment Configuration 561 */ #define CONFIG_ENV_OVERWRITE 562 563 #if defined(CONFIG_UEC_ETH) 564 #define CONFIG_HAS_ETH0 565 #define CONFIG_HAS_ETH1 566 #endif 567 568 #define CONFIG_BAUDRATE 115200 569 570 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 571 572 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 573 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 574 575 #define CONFIG_EXTRA_ENV_SETTINGS \ 576 "netdev=eth0\0" \ 577 "consoledev=ttyS0\0" \ 578 "ramdiskaddr=1000000\0" \ 579 "ramdiskfile=ramfs.83xx\0" \ 580 "fdtaddr=780000\0" \ 581 "fdtfile=mpc832x_mds.dtb\0" \ 582 "" 583 584 #define CONFIG_NFSBOOTCOMMAND \ 585 "setenv bootargs root=/dev/nfs rw " \ 586 "nfsroot=$serverip:$rootpath " \ 587 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 588 "$netdev:off " \ 589 "console=$consoledev,$baudrate $othbootargs;" \ 590 "tftp $loadaddr $bootfile;" \ 591 "tftp $fdtaddr $fdtfile;" \ 592 "bootm $loadaddr - $fdtaddr" 593 594 #define CONFIG_RAMBOOTCOMMAND \ 595 "setenv bootargs root=/dev/ram rw " \ 596 "console=$consoledev,$baudrate $othbootargs;" \ 597 "tftp $ramdiskaddr $ramdiskfile;" \ 598 "tftp $loadaddr $bootfile;" \ 599 "tftp $fdtaddr $fdtfile;" \ 600 "bootm $loadaddr $ramdiskaddr $fdtaddr" 601 602 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 603 604 #endif /* __CONFIG_H */ 605