1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_SYS_GENERIC_BOARD 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 /* E300 family */ 17 #define CONFIG_QE 1 /* Has QE */ 18 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 19 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 /* 24 * System Clock Setup 25 */ 26 #ifdef CONFIG_PCISLAVE 27 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 28 #else 29 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 30 #endif 31 32 #ifndef CONFIG_SYS_CLK_FREQ 33 #define CONFIG_SYS_CLK_FREQ 66000000 34 #endif 35 36 /* 37 * Hardware Reset Configuration Word 38 */ 39 #define CONFIG_SYS_HRCW_LOW (\ 40 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 41 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 42 HRCWL_VCO_1X2 |\ 43 HRCWL_CSB_TO_CLKIN_2X1 |\ 44 HRCWL_CORE_TO_CSB_2X1 |\ 45 HRCWL_CE_PLL_VCO_DIV_2 |\ 46 HRCWL_CE_PLL_DIV_1X1 |\ 47 HRCWL_CE_TO_PLL_1X3) 48 49 #ifdef CONFIG_PCISLAVE 50 #define CONFIG_SYS_HRCW_HIGH (\ 51 HRCWH_PCI_AGENT |\ 52 HRCWH_PCI1_ARBITER_DISABLE |\ 53 HRCWH_CORE_ENABLE |\ 54 HRCWH_FROM_0XFFF00100 |\ 55 HRCWH_BOOTSEQ_DISABLE |\ 56 HRCWH_SW_WATCHDOG_DISABLE |\ 57 HRCWH_ROM_LOC_LOCAL_16BIT |\ 58 HRCWH_BIG_ENDIAN |\ 59 HRCWH_LALE_NORMAL) 60 #else 61 #define CONFIG_SYS_HRCW_HIGH (\ 62 HRCWH_PCI_HOST |\ 63 HRCWH_PCI1_ARBITER_ENABLE |\ 64 HRCWH_CORE_ENABLE |\ 65 HRCWH_FROM_0X00000100 |\ 66 HRCWH_BOOTSEQ_DISABLE |\ 67 HRCWH_SW_WATCHDOG_DISABLE |\ 68 HRCWH_ROM_LOC_LOCAL_16BIT |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LALE_NORMAL) 71 #endif 72 73 /* 74 * System IO Config 75 */ 76 #define CONFIG_SYS_SICRL 0x00000000 77 78 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 79 #define CONFIG_BOARD_EARLY_INIT_R 80 81 /* 82 * IMMR new address 83 */ 84 #define CONFIG_SYS_IMMR 0xE0000000 85 86 /* 87 * DDR Setup 88 */ 89 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 91 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 92 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 93 94 #undef CONFIG_SPD_EEPROM 95 #if defined(CONFIG_SPD_EEPROM) 96 /* Determine DDR configuration from I2C interface 97 */ 98 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 99 #else 100 /* Manually set up DDR parameters 101 */ 102 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 103 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 104 | CSCONFIG_AP \ 105 | CSCONFIG_ODT_WR_CFG \ 106 | CSCONFIG_ROW_BIT_13 \ 107 | CSCONFIG_COL_BIT_10) 108 /* 0x80840102 */ 109 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 110 | (0 << TIMING_CFG0_WRT_SHIFT) \ 111 | (0 << TIMING_CFG0_RRT_SHIFT) \ 112 | (0 << TIMING_CFG0_WWT_SHIFT) \ 113 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 114 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 115 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 116 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 117 /* 0x00220802 */ 118 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 119 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 120 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 121 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 122 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 123 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 124 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 125 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 126 /* 0x3935D322 */ 127 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 128 | (31 << TIMING_CFG2_CPO_SHIFT) \ 129 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 130 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 131 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 132 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 133 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) 134 /* 0x0F9048CA */ 135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 136 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 137 /* 0x02000000 */ 138 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 139 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 140 /* 0x44400232 */ 141 #define CONFIG_SYS_DDR_MODE2 0x8000c000 142 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 143 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 144 /* 0x03200064 */ 145 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 146 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 147 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 148 | SDRAM_CFG_32_BE) 149 /* 0x43080000 */ 150 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 151 #endif 152 153 /* 154 * Memory test 155 */ 156 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 157 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 158 #define CONFIG_SYS_MEMTEST_END 0x00100000 159 160 /* 161 * The reserved memory 162 */ 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 164 165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 166 #define CONFIG_SYS_RAMBOOT 167 #else 168 #undef CONFIG_SYS_RAMBOOT 169 #endif 170 171 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 172 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 173 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 174 175 /* 176 * Initial RAM Base Address Setup 177 */ 178 #define CONFIG_SYS_INIT_RAM_LOCK 1 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ 180 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 181 #define CONFIG_SYS_GBL_DATA_OFFSET \ 182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 183 184 /* 185 * Local Bus Configuration & Clock Setup 186 */ 187 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 188 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 189 #define CONFIG_SYS_LBC_LBCR 0x00000000 190 191 /* 192 * FLASH on the Local Bus 193 */ 194 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 195 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 196 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 197 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 198 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 199 200 /* Window base at flash base */ 201 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 202 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 203 204 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 205 | BR_PS_16 /* 16 bit port */ \ 206 | BR_MS_GPCM /* MSEL = GPCM */ \ 207 | BR_V) /* valid */ 208 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 209 | OR_GPCM_XAM \ 210 | OR_GPCM_CSNT \ 211 | OR_GPCM_ACS_DIV2 \ 212 | OR_GPCM_XACS \ 213 | OR_GPCM_SCY_15 \ 214 | OR_GPCM_TRLX_SET \ 215 | OR_GPCM_EHTR_SET \ 216 | OR_GPCM_EAD) 217 /* 0xfe006ff7 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 221 222 #undef CONFIG_SYS_FLASH_CHECKSUM 223 224 /* 225 * BCSR on the Local Bus 226 */ 227 #define CONFIG_SYS_BCSR 0xF8000000 228 /* Access window base at BCSR base */ 229 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 230 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 231 232 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 233 | BR_PS_8 \ 234 | BR_MS_GPCM \ 235 | BR_V) 236 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 237 | OR_GPCM_XAM \ 238 | OR_GPCM_CSNT \ 239 | OR_GPCM_XACS \ 240 | OR_GPCM_SCY_15 \ 241 | OR_GPCM_TRLX_SET \ 242 | OR_GPCM_EHTR_SET \ 243 | OR_GPCM_EAD) 244 /* 0xFFFFE9F7 */ 245 246 /* 247 * Windows to access PIB via local bus 248 */ 249 /* PIB window base 0xF8008000 */ 250 #define CONFIG_SYS_PIB_BASE 0xF8008000 251 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) 252 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE 253 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 254 255 /* 256 * CS2 on Local Bus, to PIB 257 */ 258 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ 259 | BR_PS_8 \ 260 | BR_MS_GPCM \ 261 | BR_V) 262 /* 0xF8008801 */ 263 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 264 | OR_GPCM_XAM \ 265 | OR_GPCM_CSNT \ 266 | OR_GPCM_XACS \ 267 | OR_GPCM_SCY_15 \ 268 | OR_GPCM_TRLX_SET \ 269 | OR_GPCM_EHTR_SET \ 270 | OR_GPCM_EAD) 271 /* 0xffffe9f7 */ 272 273 /* 274 * CS3 on Local Bus, to PIB 275 */ 276 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ 277 CONFIG_SYS_PIB_WINDOW_SIZE) \ 278 | BR_PS_8 \ 279 | BR_MS_GPCM \ 280 | BR_V) 281 /* 0xF8010801 */ 282 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 283 | OR_GPCM_XAM \ 284 | OR_GPCM_CSNT \ 285 | OR_GPCM_XACS \ 286 | OR_GPCM_SCY_15 \ 287 | OR_GPCM_TRLX_SET \ 288 | OR_GPCM_EHTR_SET \ 289 | OR_GPCM_EAD) 290 /* 0xffffe9f7 */ 291 292 /* 293 * Serial Port 294 */ 295 #define CONFIG_CONS_INDEX 1 296 #define CONFIG_SYS_NS16550 297 #define CONFIG_SYS_NS16550_SERIAL 298 #define CONFIG_SYS_NS16550_REG_SIZE 1 299 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 300 301 #define CONFIG_SYS_BAUDRATE_TABLE \ 302 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 303 304 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 305 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 306 307 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 308 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 309 /* Use the HUSH parser */ 310 #define CONFIG_SYS_HUSH_PARSER 311 312 /* pass open firmware flat tree */ 313 #define CONFIG_OF_LIBFDT 1 314 #define CONFIG_OF_BOARD_SETUP 1 315 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 316 317 /* I2C */ 318 #define CONFIG_SYS_I2C 319 #define CONFIG_SYS_I2C_FSL 320 #define CONFIG_SYS_FSL_I2C_SPEED 400000 321 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 322 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 323 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 324 325 /* 326 * Config on-board RTC 327 */ 328 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 329 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 330 331 /* 332 * General PCI 333 * Addresses are mapped 1-1. 334 */ 335 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 336 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 337 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 338 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 339 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 340 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 341 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 342 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 343 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 344 345 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 346 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 347 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 348 349 350 #ifdef CONFIG_PCI 351 #define CONFIG_PCI_INDIRECT_BRIDGE 352 353 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 354 #define CONFIG_83XX_PCI_STREAMING 355 356 #undef CONFIG_EEPRO100 357 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 358 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 359 360 #endif /* CONFIG_PCI */ 361 362 /* 363 * QE UEC ethernet configuration 364 */ 365 #define CONFIG_UEC_ETH 366 #define CONFIG_ETHPRIME "UEC0" 367 368 #define CONFIG_UEC_ETH1 /* ETH3 */ 369 370 #ifdef CONFIG_UEC_ETH1 371 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 372 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 373 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 374 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 375 #define CONFIG_SYS_UEC1_PHY_ADDR 3 376 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 377 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 378 #endif 379 380 #define CONFIG_UEC_ETH2 /* ETH4 */ 381 382 #ifdef CONFIG_UEC_ETH2 383 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ 384 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 385 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 386 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 387 #define CONFIG_SYS_UEC2_PHY_ADDR 4 388 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 389 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 390 #endif 391 392 /* 393 * Environment 394 */ 395 #ifndef CONFIG_SYS_RAMBOOT 396 #define CONFIG_ENV_IS_IN_FLASH 1 397 #define CONFIG_ENV_ADDR \ 398 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 399 #define CONFIG_ENV_SECT_SIZE 0x20000 400 #define CONFIG_ENV_SIZE 0x2000 401 #else 402 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 403 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 404 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 405 #define CONFIG_ENV_SIZE 0x2000 406 #endif 407 408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 409 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 410 411 /* 412 * BOOTP options 413 */ 414 #define CONFIG_BOOTP_BOOTFILESIZE 415 #define CONFIG_BOOTP_BOOTPATH 416 #define CONFIG_BOOTP_GATEWAY 417 #define CONFIG_BOOTP_HOSTNAME 418 419 420 /* 421 * Command line configuration. 422 */ 423 #include <config_cmd_default.h> 424 425 #define CONFIG_CMD_PING 426 #define CONFIG_CMD_I2C 427 #define CONFIG_CMD_ASKENV 428 429 #if defined(CONFIG_PCI) 430 #define CONFIG_CMD_PCI 431 #endif 432 433 #if defined(CONFIG_SYS_RAMBOOT) 434 #undef CONFIG_CMD_SAVEENV 435 #undef CONFIG_CMD_LOADS 436 #endif 437 438 439 #undef CONFIG_WATCHDOG /* watchdog disabled */ 440 441 /* 442 * Miscellaneous configurable options 443 */ 444 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 445 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 446 447 #if defined(CONFIG_CMD_KGDB) 448 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 449 #else 450 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 451 #endif 452 453 /* Print Buffer Size */ 454 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 455 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 456 /* Boot Argument Buffer Size */ 457 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 458 459 /* 460 * For booting Linux, the board info and command line data 461 * have to be in the first 256 MB of memory, since this is 462 * the maximum mapped by the Linux kernel during initialization. 463 */ 464 /* Initial Memory map for Linux */ 465 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 466 467 /* 468 * Core HID Setup 469 */ 470 #define CONFIG_SYS_HID0_INIT 0x000000000 471 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 472 HID0_ENABLE_INSTRUCTION_CACHE) 473 #define CONFIG_SYS_HID2 HID2_HBE 474 475 /* 476 * MMU Setup 477 */ 478 479 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 480 481 /* DDR: cache cacheable */ 482 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 483 | BATL_PP_RW \ 484 | BATL_MEMCOHERENCE) 485 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 486 | BATU_BL_256M \ 487 | BATU_VS \ 488 | BATU_VP) 489 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 490 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 491 492 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 493 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 494 | BATL_PP_RW \ 495 | BATL_CACHEINHIBIT \ 496 | BATL_GUARDEDSTORAGE) 497 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 498 | BATU_BL_4M \ 499 | BATU_VS \ 500 | BATU_VP) 501 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 502 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 503 504 /* BCSR: cache-inhibit and guarded */ 505 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ 506 | BATL_PP_RW \ 507 | BATL_CACHEINHIBIT \ 508 | BATL_GUARDEDSTORAGE) 509 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ 510 | BATU_BL_128K \ 511 | BATU_VS \ 512 | BATU_VP) 513 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 514 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 515 516 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 517 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ 518 | BATL_PP_RW \ 519 | BATL_MEMCOHERENCE) 520 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ 521 | BATU_BL_32M \ 522 | BATU_VS \ 523 | BATU_VP) 524 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ 525 | BATL_PP_RW \ 526 | BATL_CACHEINHIBIT \ 527 | BATL_GUARDEDSTORAGE) 528 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 529 530 #define CONFIG_SYS_IBAT4L (0) 531 #define CONFIG_SYS_IBAT4U (0) 532 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 533 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 534 535 /* Stack in dcache: cacheable, no memory coherence */ 536 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 537 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 538 | BATU_BL_128K \ 539 | BATU_VS \ 540 | BATU_VP) 541 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 542 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 543 544 #ifdef CONFIG_PCI 545 /* PCI MEM space: cacheable */ 546 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ 547 | BATL_PP_RW \ 548 | BATL_MEMCOHERENCE) 549 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ 550 | BATU_BL_256M \ 551 | BATU_VS \ 552 | BATU_VP) 553 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 554 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 555 /* PCI MMIO space: cache-inhibit and guarded */ 556 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ 557 | BATL_PP_RW \ 558 | BATL_CACHEINHIBIT \ 559 | BATL_GUARDEDSTORAGE) 560 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ 561 | BATU_BL_256M \ 562 | BATU_VS \ 563 | BATU_VP) 564 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 565 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 566 #else 567 #define CONFIG_SYS_IBAT6L (0) 568 #define CONFIG_SYS_IBAT6U (0) 569 #define CONFIG_SYS_IBAT7L (0) 570 #define CONFIG_SYS_IBAT7U (0) 571 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 572 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 573 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 574 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 575 #endif 576 577 #if defined(CONFIG_CMD_KGDB) 578 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 579 #endif 580 581 /* 582 * Environment Configuration 583 */ #define CONFIG_ENV_OVERWRITE 584 585 #if defined(CONFIG_UEC_ETH) 586 #define CONFIG_HAS_ETH0 587 #define CONFIG_HAS_ETH1 588 #endif 589 590 #define CONFIG_BAUDRATE 115200 591 592 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 593 594 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 595 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 596 597 #define CONFIG_EXTRA_ENV_SETTINGS \ 598 "netdev=eth0\0" \ 599 "consoledev=ttyS0\0" \ 600 "ramdiskaddr=1000000\0" \ 601 "ramdiskfile=ramfs.83xx\0" \ 602 "fdtaddr=780000\0" \ 603 "fdtfile=mpc832x_mds.dtb\0" \ 604 "" 605 606 #define CONFIG_NFSBOOTCOMMAND \ 607 "setenv bootargs root=/dev/nfs rw " \ 608 "nfsroot=$serverip:$rootpath " \ 609 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 610 "$netdev:off " \ 611 "console=$consoledev,$baudrate $othbootargs;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "tftp $fdtaddr $fdtfile;" \ 614 "bootm $loadaddr - $fdtaddr" 615 616 #define CONFIG_RAMBOOTCOMMAND \ 617 "setenv bootargs root=/dev/ram rw " \ 618 "console=$consoledev,$baudrate $othbootargs;" \ 619 "tftp $ramdiskaddr $ramdiskfile;" \ 620 "tftp $loadaddr $bootfile;" \ 621 "tftp $fdtaddr $fdtfile;" \ 622 "bootm $loadaddr $ramdiskaddr $fdtaddr" 623 624 625 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 626 627 #endif /* __CONFIG_H */ 628