1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9 
10 /*
11  * High Level Configuration Options
12  */
13 #define CONFIG_E300		1	/* E300 family */
14 #define CONFIG_QE		1	/* Has QE */
15 #define CONFIG_MPC832x		1	/* MPC832x CPU specific */
16 #define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
17 
18 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
19 
20 /*
21  * System Clock Setup
22  */
23 #ifdef CONFIG_PCISLAVE
24 #define CONFIG_83XX_PCICLK	66000000	/* in HZ */
25 #else
26 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
27 #endif
28 
29 #ifndef CONFIG_SYS_CLK_FREQ
30 #define CONFIG_SYS_CLK_FREQ	66000000
31 #endif
32 
33 /*
34  * Hardware Reset Configuration Word
35  */
36 #define CONFIG_SYS_HRCW_LOW (\
37 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
38 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
39 	HRCWL_VCO_1X2 |\
40 	HRCWL_CSB_TO_CLKIN_2X1 |\
41 	HRCWL_CORE_TO_CSB_2X1 |\
42 	HRCWL_CE_PLL_VCO_DIV_2 |\
43 	HRCWL_CE_PLL_DIV_1X1 |\
44 	HRCWL_CE_TO_PLL_1X3)
45 
46 #ifdef CONFIG_PCISLAVE
47 #define CONFIG_SYS_HRCW_HIGH (\
48 	HRCWH_PCI_AGENT |\
49 	HRCWH_PCI1_ARBITER_DISABLE |\
50 	HRCWH_CORE_ENABLE |\
51 	HRCWH_FROM_0XFFF00100 |\
52 	HRCWH_BOOTSEQ_DISABLE |\
53 	HRCWH_SW_WATCHDOG_DISABLE |\
54 	HRCWH_ROM_LOC_LOCAL_16BIT |\
55 	HRCWH_BIG_ENDIAN |\
56 	HRCWH_LALE_NORMAL)
57 #else
58 #define CONFIG_SYS_HRCW_HIGH (\
59 	HRCWH_PCI_HOST |\
60 	HRCWH_PCI1_ARBITER_ENABLE |\
61 	HRCWH_CORE_ENABLE |\
62 	HRCWH_FROM_0X00000100 |\
63 	HRCWH_BOOTSEQ_DISABLE |\
64 	HRCWH_SW_WATCHDOG_DISABLE |\
65 	HRCWH_ROM_LOC_LOCAL_16BIT |\
66 	HRCWH_BIG_ENDIAN |\
67 	HRCWH_LALE_NORMAL)
68 #endif
69 
70 /*
71  * System IO Config
72  */
73 #define CONFIG_SYS_SICRL		0x00000000
74 
75 #define CONFIG_BOARD_EARLY_INIT_R
76 
77 /*
78  * IMMR new address
79  */
80 #define CONFIG_SYS_IMMR		0xE0000000
81 
82 /*
83  * DDR Setup
84  */
85 #define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
86 #define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
87 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
88 #define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */
89 
90 #undef CONFIG_SPD_EEPROM
91 #if defined(CONFIG_SPD_EEPROM)
92 /* Determine DDR configuration from I2C interface
93  */
94 #define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
95 #else
96 /* Manually set up DDR parameters
97  */
98 #define CONFIG_SYS_DDR_SIZE		128	/* MB */
99 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
100 					| CSCONFIG_AP \
101 					| CSCONFIG_ODT_WR_CFG \
102 					| CSCONFIG_ROW_BIT_13 \
103 					| CSCONFIG_COL_BIT_10)
104 					/* 0x80840102 */
105 #define CONFIG_SYS_DDR_TIMING_0		((0 << TIMING_CFG0_RWT_SHIFT) \
106 					| (0 << TIMING_CFG0_WRT_SHIFT) \
107 					| (0 << TIMING_CFG0_RRT_SHIFT) \
108 					| (0 << TIMING_CFG0_WWT_SHIFT) \
109 					| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
110 					| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
111 					| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
112 					| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
113 					/* 0x00220802 */
114 #define CONFIG_SYS_DDR_TIMING_1		((3 << TIMING_CFG1_PRETOACT_SHIFT) \
115 					| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
116 					| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
117 					| (5 << TIMING_CFG1_CASLAT_SHIFT) \
118 					| (13 << TIMING_CFG1_REFREC_SHIFT) \
119 					| (3 << TIMING_CFG1_WRREC_SHIFT) \
120 					| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
121 					| (2 << TIMING_CFG1_WRTORD_SHIFT))
122 					/* 0x3935D322 */
123 #define CONFIG_SYS_DDR_TIMING_2		((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
124 				| (31 << TIMING_CFG2_CPO_SHIFT) \
125 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
126 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
127 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
128 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
129 				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
130 				/* 0x0F9048CA */
131 #define CONFIG_SYS_DDR_TIMING_3		0x00000000
132 #define CONFIG_SYS_DDR_CLK_CNTL		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
133 					/* 0x02000000 */
134 #define CONFIG_SYS_DDR_MODE		((0x4440 << SDRAM_MODE_ESD_SHIFT) \
135 					| (0x0232 << SDRAM_MODE_SD_SHIFT))
136 					/* 0x44400232 */
137 #define CONFIG_SYS_DDR_MODE2		0x8000c000
138 #define CONFIG_SYS_DDR_INTERVAL		((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
139 					| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
140 					/* 0x03200064 */
141 #define CONFIG_SYS_DDR_CS0_BNDS		0x00000007
142 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
143 					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
144 					| SDRAM_CFG_32_BE)
145 					/* 0x43080000 */
146 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
147 #endif
148 
149 /*
150  * Memory test
151  */
152 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
153 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
154 #define CONFIG_SYS_MEMTEST_END		0x00100000
155 
156 /*
157  * The reserved memory
158  */
159 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
160 
161 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
162 #define CONFIG_SYS_RAMBOOT
163 #else
164 #undef  CONFIG_SYS_RAMBOOT
165 #endif
166 
167 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
168 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
169 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
170 
171 /*
172  * Initial RAM Base Address Setup
173  */
174 #define CONFIG_SYS_INIT_RAM_LOCK	1
175 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
176 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
177 #define CONFIG_SYS_GBL_DATA_OFFSET	\
178 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179 
180 /*
181  * Local Bus Configuration & Clock Setup
182  */
183 #define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
184 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
185 #define CONFIG_SYS_LBC_LBCR		0x00000000
186 
187 /*
188  * FLASH on the Local Bus
189  */
190 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
191 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
192 #define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
193 #define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */
194 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
195 
196 					/* Window base at flash base */
197 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
198 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
199 
200 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
201 				| BR_PS_16	/* 16 bit port */ \
202 				| BR_MS_GPCM	/* MSEL = GPCM */ \
203 				| BR_V)		/* valid */
204 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
205 				| OR_GPCM_XAM \
206 				| OR_GPCM_CSNT \
207 				| OR_GPCM_ACS_DIV2 \
208 				| OR_GPCM_XACS \
209 				| OR_GPCM_SCY_15 \
210 				| OR_GPCM_TRLX_SET \
211 				| OR_GPCM_EHTR_SET \
212 				| OR_GPCM_EAD)
213 				/* 0xfe006ff7 */
214 
215 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
217 
218 #undef CONFIG_SYS_FLASH_CHECKSUM
219 
220 /*
221  * BCSR on the Local Bus
222  */
223 #define CONFIG_SYS_BCSR			0xF8000000
224 					/* Access window base at BCSR base */
225 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
226 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
227 
228 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
229 					| BR_PS_8 \
230 					| BR_MS_GPCM \
231 					| BR_V)
232 #define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
233 					| OR_GPCM_XAM \
234 					| OR_GPCM_CSNT \
235 					| OR_GPCM_XACS \
236 					| OR_GPCM_SCY_15 \
237 					| OR_GPCM_TRLX_SET \
238 					| OR_GPCM_EHTR_SET \
239 					| OR_GPCM_EAD)
240 					/* 0xFFFFE9F7 */
241 
242 /*
243  * Windows to access PIB via local bus
244  */
245 					/* PIB window base 0xF8008000 */
246 #define CONFIG_SYS_PIB_BASE		0xF8008000
247 #define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
248 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PIB_BASE
249 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
250 
251 /*
252  * CS2 on Local Bus, to PIB
253  */
254 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_PIB_BASE \
255 				| BR_PS_8 \
256 				| BR_MS_GPCM \
257 				| BR_V)
258 				/* 0xF8008801 */
259 #define CONFIG_SYS_OR2_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
260 				| OR_GPCM_XAM \
261 				| OR_GPCM_CSNT \
262 				| OR_GPCM_XACS \
263 				| OR_GPCM_SCY_15 \
264 				| OR_GPCM_TRLX_SET \
265 				| OR_GPCM_EHTR_SET \
266 				| OR_GPCM_EAD)
267 				/* 0xffffe9f7 */
268 
269 /*
270  * CS3 on Local Bus, to PIB
271  */
272 #define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIB_BASE + \
273 					CONFIG_SYS_PIB_WINDOW_SIZE) \
274 				| BR_PS_8 \
275 				| BR_MS_GPCM \
276 				| BR_V)
277 				/* 0xF8010801 */
278 #define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
279 				| OR_GPCM_XAM \
280 				| OR_GPCM_CSNT \
281 				| OR_GPCM_XACS \
282 				| OR_GPCM_SCY_15 \
283 				| OR_GPCM_TRLX_SET \
284 				| OR_GPCM_EHTR_SET \
285 				| OR_GPCM_EAD)
286 				/* 0xffffe9f7 */
287 
288 /*
289  * Serial Port
290  */
291 #define CONFIG_CONS_INDEX	1
292 #define CONFIG_SYS_NS16550_SERIAL
293 #define CONFIG_SYS_NS16550_REG_SIZE	1
294 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
295 
296 #define CONFIG_SYS_BAUDRATE_TABLE  \
297 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
298 
299 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
300 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
301 
302 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
303 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
304 
305 /* I2C */
306 #define CONFIG_SYS_I2C
307 #define CONFIG_SYS_I2C_FSL
308 #define CONFIG_SYS_FSL_I2C_SPEED	400000
309 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
310 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
311 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
312 
313 /*
314  * Config on-board RTC
315  */
316 #define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
317 #define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
318 
319 /*
320  * General PCI
321  * Addresses are mapped 1-1.
322  */
323 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
324 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
325 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
326 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
327 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
328 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
329 #define CONFIG_SYS_PCI1_IO_BASE		0x00000000
330 #define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
331 #define CONFIG_SYS_PCI1_IO_SIZE		0x100000	/* 1M */
332 
333 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
334 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
335 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
336 
337 #ifdef CONFIG_PCI
338 #define CONFIG_PCI_INDIRECT_BRIDGE
339 
340 #define CONFIG_83XX_PCI_STREAMING
341 
342 #undef CONFIG_EEPRO100
343 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
344 #define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
345 
346 #endif	/* CONFIG_PCI */
347 
348 /*
349  * QE UEC ethernet configuration
350  */
351 #define CONFIG_UEC_ETH
352 #define CONFIG_ETHPRIME		"UEC0"
353 
354 #define CONFIG_UEC_ETH1		/* ETH3 */
355 
356 #ifdef CONFIG_UEC_ETH1
357 #define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
358 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
359 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
360 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
361 #define CONFIG_SYS_UEC1_PHY_ADDR	3
362 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
363 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
364 #endif
365 
366 #define CONFIG_UEC_ETH2		/* ETH4 */
367 
368 #ifdef CONFIG_UEC_ETH2
369 #define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
370 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
371 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
372 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
373 #define CONFIG_SYS_UEC2_PHY_ADDR	4
374 #define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
375 #define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
376 #endif
377 
378 /*
379  * Environment
380  */
381 #ifndef CONFIG_SYS_RAMBOOT
382 	#define CONFIG_ENV_IS_IN_FLASH	1
383 	#define CONFIG_ENV_ADDR		\
384 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
385 	#define CONFIG_ENV_SECT_SIZE	0x20000
386 	#define CONFIG_ENV_SIZE		0x2000
387 #else
388 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
389 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
390 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
391 	#define CONFIG_ENV_SIZE		0x2000
392 #endif
393 
394 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
395 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
396 
397 /*
398  * BOOTP options
399  */
400 #define CONFIG_BOOTP_BOOTFILESIZE
401 #define CONFIG_BOOTP_BOOTPATH
402 #define CONFIG_BOOTP_GATEWAY
403 #define CONFIG_BOOTP_HOSTNAME
404 
405 /*
406  * Command line configuration.
407  */
408 
409 #if defined(CONFIG_PCI)
410     #define CONFIG_CMD_PCI
411 #endif
412 
413 #undef CONFIG_WATCHDOG		/* watchdog disabled */
414 
415 /*
416  * Miscellaneous configurable options
417  */
418 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
419 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
420 
421 #if defined(CONFIG_CMD_KGDB)
422 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
423 #else
424 	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
425 #endif
426 
427 				/* Print Buffer Size */
428 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
429 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
430 				/* Boot Argument Buffer Size */
431 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
432 
433 /*
434  * For booting Linux, the board info and command line data
435  * have to be in the first 256 MB of memory, since this is
436  * the maximum mapped by the Linux kernel during initialization.
437  */
438 					/* Initial Memory map for Linux */
439 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
440 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
441 
442 /*
443  * Core HID Setup
444  */
445 #define CONFIG_SYS_HID0_INIT	0x000000000
446 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
447 				 HID0_ENABLE_INSTRUCTION_CACHE)
448 #define CONFIG_SYS_HID2		HID2_HBE
449 
450 /*
451  * MMU Setup
452  */
453 
454 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
455 
456 /* DDR: cache cacheable */
457 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
458 				| BATL_PP_RW \
459 				| BATL_MEMCOHERENCE)
460 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
461 				| BATU_BL_256M \
462 				| BATU_VS \
463 				| BATU_VP)
464 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
465 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
466 
467 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
468 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
469 				| BATL_PP_RW \
470 				| BATL_CACHEINHIBIT \
471 				| BATL_GUARDEDSTORAGE)
472 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
473 				| BATU_BL_4M \
474 				| BATU_VS \
475 				| BATU_VP)
476 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
477 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
478 
479 /* BCSR: cache-inhibit and guarded */
480 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR \
481 				| BATL_PP_RW \
482 				| BATL_CACHEINHIBIT \
483 				| BATL_GUARDEDSTORAGE)
484 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR \
485 				| BATU_BL_128K \
486 				| BATU_VS \
487 				| BATU_VP)
488 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
489 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
490 
491 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
492 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
493 				| BATL_PP_RW \
494 				| BATL_MEMCOHERENCE)
495 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
496 				| BATU_BL_32M \
497 				| BATU_VS \
498 				| BATU_VP)
499 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
500 				| BATL_PP_RW \
501 				| BATL_CACHEINHIBIT \
502 				| BATL_GUARDEDSTORAGE)
503 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
504 
505 #define CONFIG_SYS_IBAT4L	(0)
506 #define CONFIG_SYS_IBAT4U	(0)
507 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
508 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
509 
510 /* Stack in dcache: cacheable, no memory coherence */
511 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
512 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
513 				| BATU_BL_128K \
514 				| BATU_VS \
515 				| BATU_VP)
516 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
517 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
518 
519 #ifdef CONFIG_PCI
520 /* PCI MEM space: cacheable */
521 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
522 				| BATL_PP_RW \
523 				| BATL_MEMCOHERENCE)
524 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
525 				| BATU_BL_256M \
526 				| BATU_VS \
527 				| BATU_VP)
528 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
529 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
530 /* PCI MMIO space: cache-inhibit and guarded */
531 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
532 				| BATL_PP_RW \
533 				| BATL_CACHEINHIBIT \
534 				| BATL_GUARDEDSTORAGE)
535 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
536 				| BATU_BL_256M \
537 				| BATU_VS \
538 				| BATU_VP)
539 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
540 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
541 #else
542 #define CONFIG_SYS_IBAT6L	(0)
543 #define CONFIG_SYS_IBAT6U	(0)
544 #define CONFIG_SYS_IBAT7L	(0)
545 #define CONFIG_SYS_IBAT7U	(0)
546 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
547 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
548 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
549 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
550 #endif
551 
552 #if defined(CONFIG_CMD_KGDB)
553 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
554 #endif
555 
556 /*
557  * Environment Configuration
558  */ #define CONFIG_ENV_OVERWRITE
559 
560 #if defined(CONFIG_UEC_ETH)
561 #define CONFIG_HAS_ETH0
562 #define CONFIG_HAS_ETH1
563 #endif
564 
565 #define CONFIG_BAUDRATE	115200
566 
567 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
568 
569 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
570 
571 #define CONFIG_EXTRA_ENV_SETTINGS					\
572 	"netdev=eth0\0"							\
573 	"consoledev=ttyS0\0"						\
574 	"ramdiskaddr=1000000\0"						\
575 	"ramdiskfile=ramfs.83xx\0"					\
576 	"fdtaddr=780000\0"						\
577 	"fdtfile=mpc832x_mds.dtb\0"					\
578 	""
579 
580 #define CONFIG_NFSBOOTCOMMAND						\
581 	"setenv bootargs root=/dev/nfs rw "				\
582 		"nfsroot=$serverip:$rootpath "				\
583 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
584 							"$netdev:off "	\
585 		"console=$consoledev,$baudrate $othbootargs;"		\
586 	"tftp $loadaddr $bootfile;"					\
587 	"tftp $fdtaddr $fdtfile;"					\
588 	"bootm $loadaddr - $fdtaddr"
589 
590 #define CONFIG_RAMBOOTCOMMAND						\
591 	"setenv bootargs root=/dev/ram rw "				\
592 		"console=$consoledev,$baudrate $othbootargs;"		\
593 	"tftp $ramdiskaddr $ramdiskfile;"				\
594 	"tftp $loadaddr $bootfile;"					\
595 	"tftp $fdtaddr $fdtfile;"					\
596 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
597 
598 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
599 
600 #endif	/* __CONFIG_H */
601