1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * High Level Configuration Options 12 */ 13 #define CONFIG_E300 1 /* E300 family */ 14 #define CONFIG_QE 1 /* Has QE */ 15 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 16 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ 17 18 /* 19 * System Clock Setup 20 */ 21 #ifdef CONFIG_PCISLAVE 22 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 23 #else 24 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 25 #endif 26 27 #ifndef CONFIG_SYS_CLK_FREQ 28 #define CONFIG_SYS_CLK_FREQ 66000000 29 #endif 30 31 /* 32 * Hardware Reset Configuration Word 33 */ 34 #define CONFIG_SYS_HRCW_LOW (\ 35 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 36 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 37 HRCWL_VCO_1X2 |\ 38 HRCWL_CSB_TO_CLKIN_2X1 |\ 39 HRCWL_CORE_TO_CSB_2X1 |\ 40 HRCWL_CE_PLL_VCO_DIV_2 |\ 41 HRCWL_CE_PLL_DIV_1X1 |\ 42 HRCWL_CE_TO_PLL_1X3) 43 44 #ifdef CONFIG_PCISLAVE 45 #define CONFIG_SYS_HRCW_HIGH (\ 46 HRCWH_PCI_AGENT |\ 47 HRCWH_PCI1_ARBITER_DISABLE |\ 48 HRCWH_CORE_ENABLE |\ 49 HRCWH_FROM_0XFFF00100 |\ 50 HRCWH_BOOTSEQ_DISABLE |\ 51 HRCWH_SW_WATCHDOG_DISABLE |\ 52 HRCWH_ROM_LOC_LOCAL_16BIT |\ 53 HRCWH_BIG_ENDIAN |\ 54 HRCWH_LALE_NORMAL) 55 #else 56 #define CONFIG_SYS_HRCW_HIGH (\ 57 HRCWH_PCI_HOST |\ 58 HRCWH_PCI1_ARBITER_ENABLE |\ 59 HRCWH_CORE_ENABLE |\ 60 HRCWH_FROM_0X00000100 |\ 61 HRCWH_BOOTSEQ_DISABLE |\ 62 HRCWH_SW_WATCHDOG_DISABLE |\ 63 HRCWH_ROM_LOC_LOCAL_16BIT |\ 64 HRCWH_BIG_ENDIAN |\ 65 HRCWH_LALE_NORMAL) 66 #endif 67 68 /* 69 * System IO Config 70 */ 71 #define CONFIG_SYS_SICRL 0x00000000 72 73 /* 74 * IMMR new address 75 */ 76 #define CONFIG_SYS_IMMR 0xE0000000 77 78 /* 79 * DDR Setup 80 */ 81 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 82 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 83 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 84 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 85 86 #undef CONFIG_SPD_EEPROM 87 #if defined(CONFIG_SPD_EEPROM) 88 /* Determine DDR configuration from I2C interface 89 */ 90 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 91 #else 92 /* Manually set up DDR parameters 93 */ 94 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 95 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 96 | CSCONFIG_AP \ 97 | CSCONFIG_ODT_WR_CFG \ 98 | CSCONFIG_ROW_BIT_13 \ 99 | CSCONFIG_COL_BIT_10) 100 /* 0x80840102 */ 101 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 102 | (0 << TIMING_CFG0_WRT_SHIFT) \ 103 | (0 << TIMING_CFG0_RRT_SHIFT) \ 104 | (0 << TIMING_CFG0_WWT_SHIFT) \ 105 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 106 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 107 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 108 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 109 /* 0x00220802 */ 110 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 111 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 112 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 113 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 114 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 115 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 116 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 117 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 118 /* 0x3935D322 */ 119 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 120 | (31 << TIMING_CFG2_CPO_SHIFT) \ 121 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 122 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 123 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 124 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 125 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) 126 /* 0x0F9048CA */ 127 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 128 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 129 /* 0x02000000 */ 130 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 131 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 132 /* 0x44400232 */ 133 #define CONFIG_SYS_DDR_MODE2 0x8000c000 134 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 135 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 136 /* 0x03200064 */ 137 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 138 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 139 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 140 | SDRAM_CFG_32_BE) 141 /* 0x43080000 */ 142 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 143 #endif 144 145 /* 146 * Memory test 147 */ 148 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 149 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 150 #define CONFIG_SYS_MEMTEST_END 0x00100000 151 152 /* 153 * The reserved memory 154 */ 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 156 157 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 158 #define CONFIG_SYS_RAMBOOT 159 #else 160 #undef CONFIG_SYS_RAMBOOT 161 #endif 162 163 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 164 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 165 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 166 167 /* 168 * Initial RAM Base Address Setup 169 */ 170 #define CONFIG_SYS_INIT_RAM_LOCK 1 171 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ 172 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 173 #define CONFIG_SYS_GBL_DATA_OFFSET \ 174 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 175 176 /* 177 * Local Bus Configuration & Clock Setup 178 */ 179 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 180 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 181 #define CONFIG_SYS_LBC_LBCR 0x00000000 182 183 /* 184 * FLASH on the Local Bus 185 */ 186 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 187 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 188 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 189 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 190 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 191 192 /* Window base at flash base */ 193 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 194 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 195 196 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 197 | BR_PS_16 /* 16 bit port */ \ 198 | BR_MS_GPCM /* MSEL = GPCM */ \ 199 | BR_V) /* valid */ 200 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 201 | OR_GPCM_XAM \ 202 | OR_GPCM_CSNT \ 203 | OR_GPCM_ACS_DIV2 \ 204 | OR_GPCM_XACS \ 205 | OR_GPCM_SCY_15 \ 206 | OR_GPCM_TRLX_SET \ 207 | OR_GPCM_EHTR_SET \ 208 | OR_GPCM_EAD) 209 /* 0xfe006ff7 */ 210 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 213 214 #undef CONFIG_SYS_FLASH_CHECKSUM 215 216 /* 217 * BCSR on the Local Bus 218 */ 219 #define CONFIG_SYS_BCSR 0xF8000000 220 /* Access window base at BCSR base */ 221 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 222 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 223 224 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 225 | BR_PS_8 \ 226 | BR_MS_GPCM \ 227 | BR_V) 228 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 229 | OR_GPCM_XAM \ 230 | OR_GPCM_CSNT \ 231 | OR_GPCM_XACS \ 232 | OR_GPCM_SCY_15 \ 233 | OR_GPCM_TRLX_SET \ 234 | OR_GPCM_EHTR_SET \ 235 | OR_GPCM_EAD) 236 /* 0xFFFFE9F7 */ 237 238 /* 239 * Windows to access PIB via local bus 240 */ 241 /* PIB window base 0xF8008000 */ 242 #define CONFIG_SYS_PIB_BASE 0xF8008000 243 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) 244 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE 245 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 246 247 /* 248 * CS2 on Local Bus, to PIB 249 */ 250 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ 251 | BR_PS_8 \ 252 | BR_MS_GPCM \ 253 | BR_V) 254 /* 0xF8008801 */ 255 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 256 | OR_GPCM_XAM \ 257 | OR_GPCM_CSNT \ 258 | OR_GPCM_XACS \ 259 | OR_GPCM_SCY_15 \ 260 | OR_GPCM_TRLX_SET \ 261 | OR_GPCM_EHTR_SET \ 262 | OR_GPCM_EAD) 263 /* 0xffffe9f7 */ 264 265 /* 266 * CS3 on Local Bus, to PIB 267 */ 268 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ 269 CONFIG_SYS_PIB_WINDOW_SIZE) \ 270 | BR_PS_8 \ 271 | BR_MS_GPCM \ 272 | BR_V) 273 /* 0xF8010801 */ 274 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 275 | OR_GPCM_XAM \ 276 | OR_GPCM_CSNT \ 277 | OR_GPCM_XACS \ 278 | OR_GPCM_SCY_15 \ 279 | OR_GPCM_TRLX_SET \ 280 | OR_GPCM_EHTR_SET \ 281 | OR_GPCM_EAD) 282 /* 0xffffe9f7 */ 283 284 /* 285 * Serial Port 286 */ 287 #define CONFIG_SYS_NS16550_SERIAL 288 #define CONFIG_SYS_NS16550_REG_SIZE 1 289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 290 291 #define CONFIG_SYS_BAUDRATE_TABLE \ 292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 293 294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 296 297 /* I2C */ 298 #define CONFIG_SYS_I2C 299 #define CONFIG_SYS_I2C_FSL 300 #define CONFIG_SYS_FSL_I2C_SPEED 400000 301 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 302 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 303 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 304 305 /* 306 * Config on-board RTC 307 */ 308 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 309 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 310 311 /* 312 * General PCI 313 * Addresses are mapped 1-1. 314 */ 315 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 316 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 317 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 319 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 320 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 321 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 322 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 323 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 324 325 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 326 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 327 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 328 329 #ifdef CONFIG_PCI 330 #define CONFIG_PCI_INDIRECT_BRIDGE 331 332 #define CONFIG_83XX_PCI_STREAMING 333 334 #undef CONFIG_EEPRO100 335 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 336 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 337 338 #endif /* CONFIG_PCI */ 339 340 /* 341 * QE UEC ethernet configuration 342 */ 343 #define CONFIG_UEC_ETH 344 #define CONFIG_ETHPRIME "UEC0" 345 346 #define CONFIG_UEC_ETH1 /* ETH3 */ 347 348 #ifdef CONFIG_UEC_ETH1 349 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 350 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 351 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 352 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 353 #define CONFIG_SYS_UEC1_PHY_ADDR 3 354 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 355 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 356 #endif 357 358 #define CONFIG_UEC_ETH2 /* ETH4 */ 359 360 #ifdef CONFIG_UEC_ETH2 361 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ 362 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 363 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 364 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 365 #define CONFIG_SYS_UEC2_PHY_ADDR 4 366 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 367 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 368 #endif 369 370 /* 371 * Environment 372 */ 373 #ifndef CONFIG_SYS_RAMBOOT 374 #define CONFIG_ENV_ADDR \ 375 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 376 #define CONFIG_ENV_SECT_SIZE 0x20000 377 #define CONFIG_ENV_SIZE 0x2000 378 #else 379 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 380 #define CONFIG_ENV_SIZE 0x2000 381 #endif 382 383 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 385 386 /* 387 * BOOTP options 388 */ 389 #define CONFIG_BOOTP_BOOTFILESIZE 390 391 /* 392 * Command line configuration. 393 */ 394 395 #undef CONFIG_WATCHDOG /* watchdog disabled */ 396 397 /* 398 * Miscellaneous configurable options 399 */ 400 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 401 402 /* 403 * For booting Linux, the board info and command line data 404 * have to be in the first 256 MB of memory, since this is 405 * the maximum mapped by the Linux kernel during initialization. 406 */ 407 /* Initial Memory map for Linux */ 408 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 409 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 410 411 /* 412 * Core HID Setup 413 */ 414 #define CONFIG_SYS_HID0_INIT 0x000000000 415 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 416 HID0_ENABLE_INSTRUCTION_CACHE) 417 #define CONFIG_SYS_HID2 HID2_HBE 418 419 /* 420 * MMU Setup 421 */ 422 423 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 424 425 /* DDR: cache cacheable */ 426 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 427 | BATL_PP_RW \ 428 | BATL_MEMCOHERENCE) 429 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 430 | BATU_BL_256M \ 431 | BATU_VS \ 432 | BATU_VP) 433 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 434 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 435 436 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 437 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 438 | BATL_PP_RW \ 439 | BATL_CACHEINHIBIT \ 440 | BATL_GUARDEDSTORAGE) 441 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 442 | BATU_BL_4M \ 443 | BATU_VS \ 444 | BATU_VP) 445 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 446 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 447 448 /* BCSR: cache-inhibit and guarded */ 449 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ 450 | BATL_PP_RW \ 451 | BATL_CACHEINHIBIT \ 452 | BATL_GUARDEDSTORAGE) 453 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ 454 | BATU_BL_128K \ 455 | BATU_VS \ 456 | BATU_VP) 457 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 458 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 459 460 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 461 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ 462 | BATL_PP_RW \ 463 | BATL_MEMCOHERENCE) 464 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ 465 | BATU_BL_32M \ 466 | BATU_VS \ 467 | BATU_VP) 468 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ 469 | BATL_PP_RW \ 470 | BATL_CACHEINHIBIT \ 471 | BATL_GUARDEDSTORAGE) 472 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 473 474 #define CONFIG_SYS_IBAT4L (0) 475 #define CONFIG_SYS_IBAT4U (0) 476 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 477 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 478 479 /* Stack in dcache: cacheable, no memory coherence */ 480 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 481 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 482 | BATU_BL_128K \ 483 | BATU_VS \ 484 | BATU_VP) 485 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 486 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 487 488 #ifdef CONFIG_PCI 489 /* PCI MEM space: cacheable */ 490 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ 491 | BATL_PP_RW \ 492 | BATL_MEMCOHERENCE) 493 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ 494 | BATU_BL_256M \ 495 | BATU_VS \ 496 | BATU_VP) 497 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 498 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 499 /* PCI MMIO space: cache-inhibit and guarded */ 500 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ 501 | BATL_PP_RW \ 502 | BATL_CACHEINHIBIT \ 503 | BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ 505 | BATU_BL_256M \ 506 | BATU_VS \ 507 | BATU_VP) 508 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 509 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 510 #else 511 #define CONFIG_SYS_IBAT6L (0) 512 #define CONFIG_SYS_IBAT6U (0) 513 #define CONFIG_SYS_IBAT7L (0) 514 #define CONFIG_SYS_IBAT7U (0) 515 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 516 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 517 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 518 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 519 #endif 520 521 #if defined(CONFIG_CMD_KGDB) 522 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 523 #endif 524 525 /* 526 * Environment Configuration 527 */ #define CONFIG_ENV_OVERWRITE 528 529 #if defined(CONFIG_UEC_ETH) 530 #define CONFIG_HAS_ETH0 531 #define CONFIG_HAS_ETH1 532 #endif 533 534 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 535 536 #define CONFIG_EXTRA_ENV_SETTINGS \ 537 "netdev=eth0\0" \ 538 "consoledev=ttyS0\0" \ 539 "ramdiskaddr=1000000\0" \ 540 "ramdiskfile=ramfs.83xx\0" \ 541 "fdtaddr=780000\0" \ 542 "fdtfile=mpc832x_mds.dtb\0" \ 543 "" 544 545 #define CONFIG_NFSBOOTCOMMAND \ 546 "setenv bootargs root=/dev/nfs rw " \ 547 "nfsroot=$serverip:$rootpath " \ 548 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 549 "$netdev:off " \ 550 "console=$consoledev,$baudrate $othbootargs;" \ 551 "tftp $loadaddr $bootfile;" \ 552 "tftp $fdtaddr $fdtfile;" \ 553 "bootm $loadaddr - $fdtaddr" 554 555 #define CONFIG_RAMBOOTCOMMAND \ 556 "setenv bootargs root=/dev/ram rw " \ 557 "console=$consoledev,$baudrate $othbootargs;" \ 558 "tftp $ramdiskaddr $ramdiskfile;" \ 559 "tftp $loadaddr $bootfile;" \ 560 "tftp $fdtaddr $fdtfile;" \ 561 "bootm $loadaddr $ramdiskaddr $fdtaddr" 562 563 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 564 565 #endif /* __CONFIG_H */ 566