1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * High Level Configuration Options 12 */ 13 #define CONFIG_E300 1 /* E300 family */ 14 #define CONFIG_QE 1 /* Has QE */ 15 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 16 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ 17 18 #define CONFIG_SYS_TEXT_BASE 0xFE000000 19 20 /* 21 * System Clock Setup 22 */ 23 #ifdef CONFIG_PCISLAVE 24 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 25 #else 26 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 27 #endif 28 29 #ifndef CONFIG_SYS_CLK_FREQ 30 #define CONFIG_SYS_CLK_FREQ 66000000 31 #endif 32 33 /* 34 * Hardware Reset Configuration Word 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 39 HRCWL_VCO_1X2 |\ 40 HRCWL_CSB_TO_CLKIN_2X1 |\ 41 HRCWL_CORE_TO_CSB_2X1 |\ 42 HRCWL_CE_PLL_VCO_DIV_2 |\ 43 HRCWL_CE_PLL_DIV_1X1 |\ 44 HRCWL_CE_TO_PLL_1X3) 45 46 #ifdef CONFIG_PCISLAVE 47 #define CONFIG_SYS_HRCW_HIGH (\ 48 HRCWH_PCI_AGENT |\ 49 HRCWH_PCI1_ARBITER_DISABLE |\ 50 HRCWH_CORE_ENABLE |\ 51 HRCWH_FROM_0XFFF00100 |\ 52 HRCWH_BOOTSEQ_DISABLE |\ 53 HRCWH_SW_WATCHDOG_DISABLE |\ 54 HRCWH_ROM_LOC_LOCAL_16BIT |\ 55 HRCWH_BIG_ENDIAN |\ 56 HRCWH_LALE_NORMAL) 57 #else 58 #define CONFIG_SYS_HRCW_HIGH (\ 59 HRCWH_PCI_HOST |\ 60 HRCWH_PCI1_ARBITER_ENABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0X00000100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_BIG_ENDIAN |\ 67 HRCWH_LALE_NORMAL) 68 #endif 69 70 /* 71 * System IO Config 72 */ 73 #define CONFIG_SYS_SICRL 0x00000000 74 75 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 76 #define CONFIG_BOARD_EARLY_INIT_R 77 78 /* 79 * IMMR new address 80 */ 81 #define CONFIG_SYS_IMMR 0xE0000000 82 83 /* 84 * DDR Setup 85 */ 86 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 88 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 89 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 90 91 #undef CONFIG_SPD_EEPROM 92 #if defined(CONFIG_SPD_EEPROM) 93 /* Determine DDR configuration from I2C interface 94 */ 95 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 96 #else 97 /* Manually set up DDR parameters 98 */ 99 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 100 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 101 | CSCONFIG_AP \ 102 | CSCONFIG_ODT_WR_CFG \ 103 | CSCONFIG_ROW_BIT_13 \ 104 | CSCONFIG_COL_BIT_10) 105 /* 0x80840102 */ 106 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 107 | (0 << TIMING_CFG0_WRT_SHIFT) \ 108 | (0 << TIMING_CFG0_RRT_SHIFT) \ 109 | (0 << TIMING_CFG0_WWT_SHIFT) \ 110 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 111 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 112 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 113 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 114 /* 0x00220802 */ 115 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 116 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 117 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 118 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 119 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 120 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 121 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 122 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 123 /* 0x3935D322 */ 124 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 125 | (31 << TIMING_CFG2_CPO_SHIFT) \ 126 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 127 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 128 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 129 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 130 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) 131 /* 0x0F9048CA */ 132 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 133 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 134 /* 0x02000000 */ 135 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 136 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 137 /* 0x44400232 */ 138 #define CONFIG_SYS_DDR_MODE2 0x8000c000 139 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 140 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 141 /* 0x03200064 */ 142 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 143 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 144 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 145 | SDRAM_CFG_32_BE) 146 /* 0x43080000 */ 147 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 148 #endif 149 150 /* 151 * Memory test 152 */ 153 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 154 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 155 #define CONFIG_SYS_MEMTEST_END 0x00100000 156 157 /* 158 * The reserved memory 159 */ 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 161 162 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 163 #define CONFIG_SYS_RAMBOOT 164 #else 165 #undef CONFIG_SYS_RAMBOOT 166 #endif 167 168 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 169 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 170 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 171 172 /* 173 * Initial RAM Base Address Setup 174 */ 175 #define CONFIG_SYS_INIT_RAM_LOCK 1 176 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ 177 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 178 #define CONFIG_SYS_GBL_DATA_OFFSET \ 179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 180 181 /* 182 * Local Bus Configuration & Clock Setup 183 */ 184 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 185 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 186 #define CONFIG_SYS_LBC_LBCR 0x00000000 187 188 /* 189 * FLASH on the Local Bus 190 */ 191 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 192 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 193 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 194 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 195 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 196 197 /* Window base at flash base */ 198 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 199 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 200 201 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 202 | BR_PS_16 /* 16 bit port */ \ 203 | BR_MS_GPCM /* MSEL = GPCM */ \ 204 | BR_V) /* valid */ 205 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 206 | OR_GPCM_XAM \ 207 | OR_GPCM_CSNT \ 208 | OR_GPCM_ACS_DIV2 \ 209 | OR_GPCM_XACS \ 210 | OR_GPCM_SCY_15 \ 211 | OR_GPCM_TRLX_SET \ 212 | OR_GPCM_EHTR_SET \ 213 | OR_GPCM_EAD) 214 /* 0xfe006ff7 */ 215 216 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 218 219 #undef CONFIG_SYS_FLASH_CHECKSUM 220 221 /* 222 * BCSR on the Local Bus 223 */ 224 #define CONFIG_SYS_BCSR 0xF8000000 225 /* Access window base at BCSR base */ 226 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 227 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 228 229 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 230 | BR_PS_8 \ 231 | BR_MS_GPCM \ 232 | BR_V) 233 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 234 | OR_GPCM_XAM \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_XACS \ 237 | OR_GPCM_SCY_15 \ 238 | OR_GPCM_TRLX_SET \ 239 | OR_GPCM_EHTR_SET \ 240 | OR_GPCM_EAD) 241 /* 0xFFFFE9F7 */ 242 243 /* 244 * Windows to access PIB via local bus 245 */ 246 /* PIB window base 0xF8008000 */ 247 #define CONFIG_SYS_PIB_BASE 0xF8008000 248 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) 249 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE 250 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 251 252 /* 253 * CS2 on Local Bus, to PIB 254 */ 255 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ 256 | BR_PS_8 \ 257 | BR_MS_GPCM \ 258 | BR_V) 259 /* 0xF8008801 */ 260 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 261 | OR_GPCM_XAM \ 262 | OR_GPCM_CSNT \ 263 | OR_GPCM_XACS \ 264 | OR_GPCM_SCY_15 \ 265 | OR_GPCM_TRLX_SET \ 266 | OR_GPCM_EHTR_SET \ 267 | OR_GPCM_EAD) 268 /* 0xffffe9f7 */ 269 270 /* 271 * CS3 on Local Bus, to PIB 272 */ 273 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ 274 CONFIG_SYS_PIB_WINDOW_SIZE) \ 275 | BR_PS_8 \ 276 | BR_MS_GPCM \ 277 | BR_V) 278 /* 0xF8010801 */ 279 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ 280 | OR_GPCM_XAM \ 281 | OR_GPCM_CSNT \ 282 | OR_GPCM_XACS \ 283 | OR_GPCM_SCY_15 \ 284 | OR_GPCM_TRLX_SET \ 285 | OR_GPCM_EHTR_SET \ 286 | OR_GPCM_EAD) 287 /* 0xffffe9f7 */ 288 289 /* 290 * Serial Port 291 */ 292 #define CONFIG_CONS_INDEX 1 293 #define CONFIG_SYS_NS16550_SERIAL 294 #define CONFIG_SYS_NS16550_REG_SIZE 1 295 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 296 297 #define CONFIG_SYS_BAUDRATE_TABLE \ 298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 299 300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 302 303 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 304 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 305 306 /* I2C */ 307 #define CONFIG_SYS_I2C 308 #define CONFIG_SYS_I2C_FSL 309 #define CONFIG_SYS_FSL_I2C_SPEED 400000 310 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 311 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 312 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 313 314 /* 315 * Config on-board RTC 316 */ 317 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 318 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 319 320 /* 321 * General PCI 322 * Addresses are mapped 1-1. 323 */ 324 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 325 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 326 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 327 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 328 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 329 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 330 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 331 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 332 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 333 334 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 335 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 336 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 337 338 #ifdef CONFIG_PCI 339 #define CONFIG_PCI_INDIRECT_BRIDGE 340 341 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 342 #define CONFIG_83XX_PCI_STREAMING 343 344 #undef CONFIG_EEPRO100 345 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 346 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 347 348 #endif /* CONFIG_PCI */ 349 350 /* 351 * QE UEC ethernet configuration 352 */ 353 #define CONFIG_UEC_ETH 354 #define CONFIG_ETHPRIME "UEC0" 355 356 #define CONFIG_UEC_ETH1 /* ETH3 */ 357 358 #ifdef CONFIG_UEC_ETH1 359 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 360 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 361 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 362 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 363 #define CONFIG_SYS_UEC1_PHY_ADDR 3 364 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 365 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 366 #endif 367 368 #define CONFIG_UEC_ETH2 /* ETH4 */ 369 370 #ifdef CONFIG_UEC_ETH2 371 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ 372 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 373 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 374 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 375 #define CONFIG_SYS_UEC2_PHY_ADDR 4 376 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 377 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 378 #endif 379 380 /* 381 * Environment 382 */ 383 #ifndef CONFIG_SYS_RAMBOOT 384 #define CONFIG_ENV_IS_IN_FLASH 1 385 #define CONFIG_ENV_ADDR \ 386 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 387 #define CONFIG_ENV_SECT_SIZE 0x20000 388 #define CONFIG_ENV_SIZE 0x2000 389 #else 390 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 391 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 392 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 393 #define CONFIG_ENV_SIZE 0x2000 394 #endif 395 396 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 397 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 398 399 /* 400 * BOOTP options 401 */ 402 #define CONFIG_BOOTP_BOOTFILESIZE 403 #define CONFIG_BOOTP_BOOTPATH 404 #define CONFIG_BOOTP_GATEWAY 405 #define CONFIG_BOOTP_HOSTNAME 406 407 /* 408 * Command line configuration. 409 */ 410 411 #if defined(CONFIG_PCI) 412 #define CONFIG_CMD_PCI 413 #endif 414 415 #undef CONFIG_WATCHDOG /* watchdog disabled */ 416 417 /* 418 * Miscellaneous configurable options 419 */ 420 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 421 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 422 423 #if defined(CONFIG_CMD_KGDB) 424 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 425 #else 426 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 427 #endif 428 429 /* Print Buffer Size */ 430 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 431 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 432 /* Boot Argument Buffer Size */ 433 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 434 435 /* 436 * For booting Linux, the board info and command line data 437 * have to be in the first 256 MB of memory, since this is 438 * the maximum mapped by the Linux kernel during initialization. 439 */ 440 /* Initial Memory map for Linux */ 441 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 442 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 443 444 /* 445 * Core HID Setup 446 */ 447 #define CONFIG_SYS_HID0_INIT 0x000000000 448 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 449 HID0_ENABLE_INSTRUCTION_CACHE) 450 #define CONFIG_SYS_HID2 HID2_HBE 451 452 /* 453 * MMU Setup 454 */ 455 456 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 457 458 /* DDR: cache cacheable */ 459 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 460 | BATL_PP_RW \ 461 | BATL_MEMCOHERENCE) 462 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 463 | BATU_BL_256M \ 464 | BATU_VS \ 465 | BATU_VP) 466 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 467 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 468 469 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 470 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 471 | BATL_PP_RW \ 472 | BATL_CACHEINHIBIT \ 473 | BATL_GUARDEDSTORAGE) 474 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 475 | BATU_BL_4M \ 476 | BATU_VS \ 477 | BATU_VP) 478 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 479 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 480 481 /* BCSR: cache-inhibit and guarded */ 482 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ 483 | BATL_PP_RW \ 484 | BATL_CACHEINHIBIT \ 485 | BATL_GUARDEDSTORAGE) 486 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ 487 | BATU_BL_128K \ 488 | BATU_VS \ 489 | BATU_VP) 490 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 491 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 492 493 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 494 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ 495 | BATL_PP_RW \ 496 | BATL_MEMCOHERENCE) 497 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ 498 | BATU_BL_32M \ 499 | BATU_VS \ 500 | BATU_VP) 501 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ 502 | BATL_PP_RW \ 503 | BATL_CACHEINHIBIT \ 504 | BATL_GUARDEDSTORAGE) 505 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 506 507 #define CONFIG_SYS_IBAT4L (0) 508 #define CONFIG_SYS_IBAT4U (0) 509 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 510 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 511 512 /* Stack in dcache: cacheable, no memory coherence */ 513 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 514 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 515 | BATU_BL_128K \ 516 | BATU_VS \ 517 | BATU_VP) 518 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 519 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 520 521 #ifdef CONFIG_PCI 522 /* PCI MEM space: cacheable */ 523 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ 524 | BATL_PP_RW \ 525 | BATL_MEMCOHERENCE) 526 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ 527 | BATU_BL_256M \ 528 | BATU_VS \ 529 | BATU_VP) 530 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 531 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 532 /* PCI MMIO space: cache-inhibit and guarded */ 533 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ 534 | BATL_PP_RW \ 535 | BATL_CACHEINHIBIT \ 536 | BATL_GUARDEDSTORAGE) 537 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ 538 | BATU_BL_256M \ 539 | BATU_VS \ 540 | BATU_VP) 541 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 542 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 543 #else 544 #define CONFIG_SYS_IBAT6L (0) 545 #define CONFIG_SYS_IBAT6U (0) 546 #define CONFIG_SYS_IBAT7L (0) 547 #define CONFIG_SYS_IBAT7U (0) 548 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 549 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 550 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 551 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 552 #endif 553 554 #if defined(CONFIG_CMD_KGDB) 555 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 556 #endif 557 558 /* 559 * Environment Configuration 560 */ #define CONFIG_ENV_OVERWRITE 561 562 #if defined(CONFIG_UEC_ETH) 563 #define CONFIG_HAS_ETH0 564 #define CONFIG_HAS_ETH1 565 #endif 566 567 #define CONFIG_BAUDRATE 115200 568 569 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 570 571 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 572 573 #define CONFIG_EXTRA_ENV_SETTINGS \ 574 "netdev=eth0\0" \ 575 "consoledev=ttyS0\0" \ 576 "ramdiskaddr=1000000\0" \ 577 "ramdiskfile=ramfs.83xx\0" \ 578 "fdtaddr=780000\0" \ 579 "fdtfile=mpc832x_mds.dtb\0" \ 580 "" 581 582 #define CONFIG_NFSBOOTCOMMAND \ 583 "setenv bootargs root=/dev/nfs rw " \ 584 "nfsroot=$serverip:$rootpath " \ 585 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 586 "$netdev:off " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "tftp $loadaddr $bootfile;" \ 589 "tftp $fdtaddr $fdtfile;" \ 590 "bootm $loadaddr - $fdtaddr" 591 592 #define CONFIG_RAMBOOTCOMMAND \ 593 "setenv bootargs root=/dev/ram rw " \ 594 "console=$consoledev,$baudrate $othbootargs;" \ 595 "tftp $ramdiskaddr $ramdiskfile;" \ 596 "tftp $loadaddr $bootfile;" \ 597 "tftp $fdtaddr $fdtfile;" \ 598 "bootm $loadaddr $ramdiskaddr $fdtaddr" 599 600 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 601 602 #endif /* __CONFIG_H */ 603