1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 18 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 19 20 #define CONFIG_PCI 1 21 22 /* 23 * System Clock Setup 24 */ 25 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 26 27 #ifndef CONFIG_SYS_CLK_FREQ 28 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 29 #endif 30 31 /* 32 * Hardware Reset Configuration Word 33 */ 34 #define CONFIG_SYS_HRCW_LOW (\ 35 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 36 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 37 HRCWL_VCO_1X2 |\ 38 HRCWL_CSB_TO_CLKIN_2X1 |\ 39 HRCWL_CORE_TO_CSB_2_5X1 |\ 40 HRCWL_CE_PLL_VCO_DIV_2 |\ 41 HRCWL_CE_PLL_DIV_1X1 |\ 42 HRCWL_CE_TO_PLL_1X3) 43 44 #define CONFIG_SYS_HRCW_HIGH (\ 45 HRCWH_PCI_HOST |\ 46 HRCWH_PCI1_ARBITER_ENABLE |\ 47 HRCWH_CORE_ENABLE |\ 48 HRCWH_FROM_0X00000100 |\ 49 HRCWH_BOOTSEQ_DISABLE |\ 50 HRCWH_SW_WATCHDOG_DISABLE |\ 51 HRCWH_ROM_LOC_LOCAL_16BIT |\ 52 HRCWH_BIG_ENDIAN |\ 53 HRCWH_LALE_NORMAL) 54 55 /* 56 * System IO Config 57 */ 58 #define CONFIG_SYS_SICRL 0x00000000 59 60 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 61 62 /* 63 * IMMR new address 64 */ 65 #define CONFIG_SYS_IMMR 0xE0000000 66 67 /* 68 * System performance 69 */ 70 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 71 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 72 #define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 73 74 /* 75 * DDR Setup 76 */ 77 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 79 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 80 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 81 82 #undef CONFIG_SPD_EEPROM 83 #if defined(CONFIG_SPD_EEPROM) 84 /* Determine DDR configuration from I2C interface 85 */ 86 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 87 #else 88 /* Manually set up DDR parameters 89 */ 90 #define CONFIG_SYS_DDR_SIZE 64 /* MB */ 91 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ 92 | CSCONFIG_ODT_WR_ACS \ 93 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) 94 /* 0x80010101 */ 95 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 96 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 97 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 98 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 99 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 100 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 101 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 102 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 103 /* 0x00220802 */ 104 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ 105 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 106 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ 107 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 108 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ 109 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ 110 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 111 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 112 /* 0x26253222 */ 113 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 114 | (31 << TIMING_CFG2_CPO_SHIFT ) \ 115 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 116 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 117 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 118 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 119 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 120 /* 0x1f9048c7 */ 121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 122 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 123 /* 0x02000000 */ 124 #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 125 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 126 /* 0x44480232 */ 127 #define CONFIG_SYS_DDR_MODE2 0x8000c000 128 #define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 129 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 130 /* 0x03200064 */ 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 132 #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ 133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 134 | SDRAM_CFG_32_BE ) 135 /* 0x43080000 */ 136 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 137 #endif 138 139 /* 140 * Memory test 141 */ 142 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 143 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ 144 #define CONFIG_SYS_MEMTEST_END 0x03f00000 145 146 /* 147 * The reserved memory 148 */ 149 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 150 151 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 152 #define CONFIG_SYS_RAMBOOT 153 #else 154 #undef CONFIG_SYS_RAMBOOT 155 #endif 156 157 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 158 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 159 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 160 161 /* 162 * Initial RAM Base Address Setup 163 */ 164 #define CONFIG_SYS_INIT_RAM_LOCK 1 165 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 166 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 167 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 168 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 169 170 /* 171 * Local Bus Configuration & Clock Setup 172 */ 173 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 174 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 175 #define CONFIG_SYS_LBC_LBCR 0x00000000 176 177 /* 178 * FLASH on the Local Bus 179 */ 180 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 181 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 182 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 183 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 184 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 185 186 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 187 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 188 189 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ 190 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 191 BR_V) /* valid */ 192 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 193 194 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 195 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 196 197 #undef CONFIG_SYS_FLASH_CHECKSUM 198 199 /* 200 * SDRAM on the Local Bus 201 */ 202 #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ 203 204 #ifdef CONFIG_SYS_LB_SDRAM 205 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 206 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 207 208 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 209 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 210 211 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 212 /* 213 * Base Register 2 and Option Register 2 configure SDRAM. 214 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 215 * 216 * For BR2, need: 217 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 218 * port size = 32-bits = BR2[19:20] = 11 219 * no parity checking = BR2[21:22] = 00 220 * SDRAM for MSEL = BR2[24:26] = 011 221 * Valid = BR[31] = 1 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 225 * 226 * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 227 * the top 17 bits of BR2. 228 */ 229 230 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 231 232 /* 233 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 234 * 235 * For OR2, need: 236 * 64MB mask for AM, OR2[0:7] = 1111 1100 237 * XAM, OR2[17:18] = 11 238 * 9 columns OR2[19-21] = 010 239 * 13 rows OR2[23-25] = 100 240 * EAD set for extra time OR[31] = 1 241 * 242 * 0 4 8 12 16 20 24 28 243 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 244 */ 245 246 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 247 248 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 249 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 250 251 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 252 253 #endif 254 255 /* 256 * Windows to access PIB via local bus 257 */ 258 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ 259 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 260 261 /* 262 * Serial Port 263 */ 264 #define CONFIG_CONS_INDEX 1 265 #undef CONFIG_SERIAL_SOFTWARE_FIFO 266 #define CONFIG_SYS_NS16550 267 #define CONFIG_SYS_NS16550_SERIAL 268 #define CONFIG_SYS_NS16550_REG_SIZE 1 269 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 270 271 #define CONFIG_SYS_BAUDRATE_TABLE \ 272 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 273 274 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 275 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 276 277 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 278 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 279 /* Use the HUSH parser */ 280 #define CONFIG_SYS_HUSH_PARSER 281 #ifdef CONFIG_SYS_HUSH_PARSER 282 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 283 #endif 284 285 /* pass open firmware flat tree */ 286 #define CONFIG_OF_LIBFDT 1 287 #define CONFIG_OF_BOARD_SETUP 1 288 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 289 290 /* I2C */ 291 #define CONFIG_HARD_I2C /* I2C with hardware support */ 292 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 293 #define CONFIG_FSL_I2C 294 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 295 #define CONFIG_SYS_I2C_SLAVE 0x7F 296 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 297 #define CONFIG_SYS_I2C_OFFSET 0x3000 298 299 /* 300 * Config on-board EEPROM 301 */ 302 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 303 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 304 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 305 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 306 307 /* 308 * General PCI 309 * Addresses are mapped 1-1. 310 */ 311 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 312 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 313 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 314 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 315 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 316 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 317 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 318 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 319 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ 320 321 #ifdef CONFIG_PCI 322 #define CONFIG_PCI_SKIP_HOST_BRIDGE 323 #define CONFIG_NET_MULTI 324 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 325 326 #undef CONFIG_EEPRO100 327 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 328 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 329 330 #endif /* CONFIG_PCI */ 331 332 333 #ifndef CONFIG_NET_MULTI 334 #define CONFIG_NET_MULTI 1 335 #endif 336 337 /* 338 * QE UEC ethernet configuration 339 */ 340 #define CONFIG_UEC_ETH 341 #define CONFIG_ETHPRIME "UEC0" 342 343 #define CONFIG_UEC_ETH1 /* ETH3 */ 344 345 #ifdef CONFIG_UEC_ETH1 346 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 347 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 348 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 349 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 350 #define CONFIG_SYS_UEC1_PHY_ADDR 4 351 #define CONFIG_SYS_UEC1_INTERFACE_TYPE MII 352 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 353 #endif 354 355 #define CONFIG_UEC_ETH2 /* ETH4 */ 356 357 #ifdef CONFIG_UEC_ETH2 358 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 359 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 360 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 361 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 362 #define CONFIG_SYS_UEC2_PHY_ADDR 0 363 #define CONFIG_SYS_UEC2_INTERFACE_TYPE MII 364 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 365 #endif 366 367 /* 368 * Environment 369 */ 370 #ifndef CONFIG_SYS_RAMBOOT 371 #define CONFIG_ENV_IS_IN_FLASH 1 372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 373 #define CONFIG_ENV_SECT_SIZE 0x20000 374 #define CONFIG_ENV_SIZE 0x2000 375 #else 376 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 377 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 378 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 379 #define CONFIG_ENV_SIZE 0x2000 380 #endif 381 382 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 383 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 384 385 /* 386 * BOOTP options 387 */ 388 #define CONFIG_BOOTP_BOOTFILESIZE 389 #define CONFIG_BOOTP_BOOTPATH 390 #define CONFIG_BOOTP_GATEWAY 391 #define CONFIG_BOOTP_HOSTNAME 392 393 /* 394 * Command line configuration. 395 */ 396 #include <config_cmd_default.h> 397 398 #define CONFIG_CMD_PING 399 #define CONFIG_CMD_I2C 400 #define CONFIG_CMD_EEPROM 401 #define CONFIG_CMD_ASKENV 402 403 #if defined(CONFIG_PCI) 404 #define CONFIG_CMD_PCI 405 #endif 406 #if defined(CONFIG_SYS_RAMBOOT) 407 #undef CONFIG_CMD_SAVEENV 408 #undef CONFIG_CMD_LOADS 409 #endif 410 411 #undef CONFIG_WATCHDOG /* watchdog disabled */ 412 413 /* 414 * Miscellaneous configurable options 415 */ 416 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 417 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 418 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 419 420 #if (CONFIG_CMD_KGDB) 421 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 422 #else 423 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 424 #endif 425 426 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 427 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 428 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 429 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 430 431 /* 432 * For booting Linux, the board info and command line data 433 * have to be in the first 8 MB of memory, since this is 434 * the maximum mapped by the Linux kernel during initialization. 435 */ 436 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 437 438 /* 439 * Core HID Setup 440 */ 441 #define CONFIG_SYS_HID0_INIT 0x000000000 442 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 443 HID0_ENABLE_INSTRUCTION_CACHE) 444 #define CONFIG_SYS_HID2 HID2_HBE 445 446 /* 447 * MMU Setup 448 */ 449 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 450 451 /* DDR: cache cacheable */ 452 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 453 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 454 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 455 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 456 457 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 458 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 459 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 460 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 461 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 462 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 463 464 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 465 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 466 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 467 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 468 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 469 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 470 471 #define CONFIG_SYS_IBAT3L (0) 472 #define CONFIG_SYS_IBAT3U (0) 473 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 474 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 475 476 /* Stack in dcache: cacheable, no memory coherence */ 477 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 478 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 479 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 480 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 481 482 #ifdef CONFIG_PCI 483 /* PCI MEM space: cacheable */ 484 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 485 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 486 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 487 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 488 /* PCI MMIO space: cache-inhibit and guarded */ 489 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ 490 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 491 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 492 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 493 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 494 #else 495 #define CONFIG_SYS_IBAT5L (0) 496 #define CONFIG_SYS_IBAT5U (0) 497 #define CONFIG_SYS_IBAT6L (0) 498 #define CONFIG_SYS_IBAT6U (0) 499 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 500 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 501 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 502 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 503 #endif 504 505 /* Nothing in BAT7 */ 506 #define CONFIG_SYS_IBAT7L (0) 507 #define CONFIG_SYS_IBAT7U (0) 508 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 509 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 510 511 /* 512 * Internal Definitions 513 * 514 * Boot Flags 515 */ 516 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 517 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 518 519 #if (CONFIG_CMD_KGDB) 520 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 521 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 522 #endif 523 524 /* 525 * Environment Configuration 526 */ 527 #define CONFIG_ENV_OVERWRITE 528 529 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 530 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 531 532 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ 533 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ 534 535 #define CONFIG_NETDEV eth1 536 537 #define CONFIG_HOSTNAME mpc8323erdb 538 #define CONFIG_ROOTPATH /nfsroot 539 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 540 #define CONFIG_BOOTFILE uImage 541 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 542 #define CONFIG_FDTFILE mpc832x_rdb.dtb 543 544 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 545 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 546 #define CONFIG_BAUDRATE 115200 547 548 #define XMK_STR(x) #x 549 #define MK_STR(x) XMK_STR(x) 550 551 #define CONFIG_EXTRA_ENV_SETTINGS \ 552 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 553 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 554 "tftpflash=tftp $loadaddr $uboot;" \ 555 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 556 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 557 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 558 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 559 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 560 "fdtaddr=780000\0" \ 561 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 562 "ramdiskaddr=1000000\0" \ 563 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 564 "console=ttyS0\0" \ 565 "setbootargs=setenv bootargs " \ 566 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 567 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 568 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 569 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 570 571 #define CONFIG_NFSBOOTCOMMAND \ 572 "setenv rootdev /dev/nfs;" \ 573 "run setbootargs;" \ 574 "run setipargs;" \ 575 "tftp $loadaddr $bootfile;" \ 576 "tftp $fdtaddr $fdtfile;" \ 577 "bootm $loadaddr - $fdtaddr" 578 579 #define CONFIG_RAMBOOTCOMMAND \ 580 "setenv rootdev /dev/ram;" \ 581 "run setbootargs;" \ 582 "tftp $ramdiskaddr $ramdiskfile;" \ 583 "tftp $loadaddr $bootfile;" \ 584 "tftp $fdtaddr $fdtfile;" \ 585 "bootm $loadaddr $ramdiskaddr $fdtaddr" 586 587 #undef MK_STR 588 #undef XMK_STR 589 590 #endif /* __CONFIG_H */ 591