1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 18 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_PCI 1 23 24 /* 25 * System Clock Setup 26 */ 27 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 28 29 #ifndef CONFIG_SYS_CLK_FREQ 30 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 31 #endif 32 33 /* 34 * Hardware Reset Configuration Word 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 39 HRCWL_VCO_1X2 |\ 40 HRCWL_CSB_TO_CLKIN_2X1 |\ 41 HRCWL_CORE_TO_CSB_2_5X1 |\ 42 HRCWL_CE_PLL_VCO_DIV_2 |\ 43 HRCWL_CE_PLL_DIV_1X1 |\ 44 HRCWL_CE_TO_PLL_1X3) 45 46 #define CONFIG_SYS_HRCW_HIGH (\ 47 HRCWH_PCI_HOST |\ 48 HRCWH_PCI1_ARBITER_ENABLE |\ 49 HRCWH_CORE_ENABLE |\ 50 HRCWH_FROM_0X00000100 |\ 51 HRCWH_BOOTSEQ_DISABLE |\ 52 HRCWH_SW_WATCHDOG_DISABLE |\ 53 HRCWH_ROM_LOC_LOCAL_16BIT |\ 54 HRCWH_BIG_ENDIAN |\ 55 HRCWH_LALE_NORMAL) 56 57 /* 58 * System IO Config 59 */ 60 #define CONFIG_SYS_SICRL 0x00000000 61 62 /* 63 * IMMR new address 64 */ 65 #define CONFIG_SYS_IMMR 0xE0000000 66 67 /* 68 * System performance 69 */ 70 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 71 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 72 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 73 #define CONFIG_SYS_SPCR_OPT 1 74 75 /* 76 * DDR Setup 77 */ 78 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 80 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 81 82 #undef CONFIG_SPD_EEPROM 83 #if defined(CONFIG_SPD_EEPROM) 84 /* Determine DDR configuration from I2C interface 85 */ 86 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 87 #else 88 /* Manually set up DDR parameters 89 */ 90 #define CONFIG_SYS_DDR_SIZE 64 /* MB */ 91 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 92 | CSCONFIG_ROW_BIT_13 \ 93 | CSCONFIG_COL_BIT_9) 94 /* 0x80010101 */ 95 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 96 | (0 << TIMING_CFG0_WRT_SHIFT) \ 97 | (0 << TIMING_CFG0_RRT_SHIFT) \ 98 | (0 << TIMING_CFG0_WWT_SHIFT) \ 99 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 100 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 101 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 102 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 103 /* 0x00220802 */ 104 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 105 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 106 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 107 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 108 | (3 << TIMING_CFG1_REFREC_SHIFT) \ 109 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 110 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 111 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 112 /* 0x26253222 */ 113 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 114 | (31 << TIMING_CFG2_CPO_SHIFT) \ 115 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 116 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 117 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 118 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 119 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 120 /* 0x1f9048c7 */ 121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 122 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 123 /* 0x02000000 */ 124 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 125 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 126 /* 0x44480232 */ 127 #define CONFIG_SYS_DDR_MODE2 0x8000c000 128 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 129 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 130 /* 0x03200064 */ 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 132 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 134 | SDRAM_CFG_32_BE) 135 /* 0x43080000 */ 136 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 137 #endif 138 139 /* 140 * Memory test 141 */ 142 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 143 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ 144 #define CONFIG_SYS_MEMTEST_END 0x03f00000 145 146 /* 147 * The reserved memory 148 */ 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 150 151 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 152 #define CONFIG_SYS_RAMBOOT 153 #else 154 #undef CONFIG_SYS_RAMBOOT 155 #endif 156 157 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 158 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 159 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 160 161 /* 162 * Initial RAM Base Address Setup 163 */ 164 #define CONFIG_SYS_INIT_RAM_LOCK 1 165 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 166 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 167 #define CONFIG_SYS_GBL_DATA_OFFSET \ 168 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 169 170 /* 171 * Local Bus Configuration & Clock Setup 172 */ 173 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 174 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 175 #define CONFIG_SYS_LBC_LBCR 0x00000000 176 177 /* 178 * FLASH on the Local Bus 179 */ 180 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 181 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 182 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 183 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 184 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 185 186 /* Window base at flash base */ 187 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 188 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 189 190 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 191 | BR_PS_16 /* 16 bit port */ \ 192 | BR_MS_GPCM /* MSEL = GPCM */ \ 193 | BR_V) /* valid */ 194 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 195 | OR_GPCM_XAM \ 196 | OR_GPCM_CSNT \ 197 | OR_GPCM_ACS_DIV2 \ 198 | OR_GPCM_XACS \ 199 | OR_GPCM_SCY_15 \ 200 | OR_GPCM_TRLX_SET \ 201 | OR_GPCM_EHTR_SET \ 202 | OR_GPCM_EAD) 203 /* 0xFE006FF7 */ 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 207 208 #undef CONFIG_SYS_FLASH_CHECKSUM 209 210 /* 211 * Serial Port 212 */ 213 #define CONFIG_CONS_INDEX 1 214 #define CONFIG_SYS_NS16550 215 #define CONFIG_SYS_NS16550_SERIAL 216 #define CONFIG_SYS_NS16550_REG_SIZE 1 217 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 218 219 #define CONFIG_SYS_BAUDRATE_TABLE \ 220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 221 222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 224 225 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 226 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 227 /* Use the HUSH parser */ 228 #define CONFIG_SYS_HUSH_PARSER 229 #ifdef CONFIG_SYS_HUSH_PARSER 230 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 231 #endif 232 233 /* pass open firmware flat tree */ 234 #define CONFIG_OF_LIBFDT 1 235 #define CONFIG_OF_BOARD_SETUP 1 236 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 237 238 /* I2C */ 239 #define CONFIG_HARD_I2C /* I2C with hardware support */ 240 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 241 #define CONFIG_FSL_I2C 242 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 243 #define CONFIG_SYS_I2C_SLAVE 0x7F 244 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 245 #define CONFIG_SYS_I2C_OFFSET 0x3000 246 247 /* 248 * Config on-board EEPROM 249 */ 250 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 254 255 /* 256 * General PCI 257 * Addresses are mapped 1-1. 258 */ 259 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 261 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 262 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 263 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 264 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 265 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 266 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 267 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ 268 269 #ifdef CONFIG_PCI 270 #define CONFIG_PCI_SKIP_HOST_BRIDGE 271 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 272 273 #undef CONFIG_EEPRO100 274 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 275 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 276 277 #endif /* CONFIG_PCI */ 278 279 /* 280 * QE UEC ethernet configuration 281 */ 282 #define CONFIG_UEC_ETH 283 #define CONFIG_ETHPRIME "UEC0" 284 285 #define CONFIG_UEC_ETH1 /* ETH3 */ 286 287 #ifdef CONFIG_UEC_ETH1 288 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 289 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 290 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 291 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 292 #define CONFIG_SYS_UEC1_PHY_ADDR 4 293 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 294 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 295 #endif 296 297 #define CONFIG_UEC_ETH2 /* ETH4 */ 298 299 #ifdef CONFIG_UEC_ETH2 300 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 301 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 302 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 303 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 304 #define CONFIG_SYS_UEC2_PHY_ADDR 0 305 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 306 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 307 #endif 308 309 /* 310 * Environment 311 */ 312 #ifndef CONFIG_SYS_RAMBOOT 313 #define CONFIG_ENV_IS_IN_FLASH 1 314 #define CONFIG_ENV_ADDR \ 315 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 316 #define CONFIG_ENV_SECT_SIZE 0x20000 317 #define CONFIG_ENV_SIZE 0x2000 318 #else 319 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 320 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 321 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 322 #define CONFIG_ENV_SIZE 0x2000 323 #endif 324 325 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 326 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 327 328 /* 329 * BOOTP options 330 */ 331 #define CONFIG_BOOTP_BOOTFILESIZE 332 #define CONFIG_BOOTP_BOOTPATH 333 #define CONFIG_BOOTP_GATEWAY 334 #define CONFIG_BOOTP_HOSTNAME 335 336 /* 337 * Command line configuration. 338 */ 339 #include <config_cmd_default.h> 340 341 #define CONFIG_CMD_PING 342 #define CONFIG_CMD_I2C 343 #define CONFIG_CMD_EEPROM 344 #define CONFIG_CMD_ASKENV 345 346 #if defined(CONFIG_PCI) 347 #define CONFIG_CMD_PCI 348 #endif 349 #if defined(CONFIG_SYS_RAMBOOT) 350 #undef CONFIG_CMD_SAVEENV 351 #undef CONFIG_CMD_LOADS 352 #endif 353 354 #undef CONFIG_WATCHDOG /* watchdog disabled */ 355 356 /* 357 * Miscellaneous configurable options 358 */ 359 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 360 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 361 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 362 363 #if (CONFIG_CMD_KGDB) 364 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 365 #else 366 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 367 #endif 368 369 /* Print Buffer Size */ 370 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 371 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 372 /* Boot Argument Buffer Size */ 373 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 374 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 375 376 /* 377 * For booting Linux, the board info and command line data 378 * have to be in the first 256 MB of memory, since this is 379 * the maximum mapped by the Linux kernel during initialization. 380 */ 381 /* Initial Memory map for Linux */ 382 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 383 384 /* 385 * Core HID Setup 386 */ 387 #define CONFIG_SYS_HID0_INIT 0x000000000 388 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 389 HID0_ENABLE_INSTRUCTION_CACHE) 390 #define CONFIG_SYS_HID2 HID2_HBE 391 392 /* 393 * MMU Setup 394 */ 395 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 396 397 /* DDR: cache cacheable */ 398 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 399 | BATL_PP_RW \ 400 | BATL_MEMCOHERENCE) 401 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 402 | BATU_BL_256M \ 403 | BATU_VS \ 404 | BATU_VP) 405 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 406 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 407 408 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 409 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 410 | BATL_PP_RW \ 411 | BATL_CACHEINHIBIT \ 412 | BATL_GUARDEDSTORAGE) 413 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 414 | BATU_BL_4M \ 415 | BATU_VS \ 416 | BATU_VP) 417 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 418 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 419 420 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 421 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 422 | BATL_PP_RW \ 423 | BATL_MEMCOHERENCE) 424 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 425 | BATU_BL_32M \ 426 | BATU_VS \ 427 | BATU_VP) 428 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 429 | BATL_PP_RW \ 430 | BATL_CACHEINHIBIT \ 431 | BATL_GUARDEDSTORAGE) 432 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 433 434 #define CONFIG_SYS_IBAT3L (0) 435 #define CONFIG_SYS_IBAT3U (0) 436 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 437 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 438 439 /* Stack in dcache: cacheable, no memory coherence */ 440 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 441 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ 442 | BATU_BL_128K \ 443 | BATU_VS \ 444 | BATU_VP) 445 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 446 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 447 448 #ifdef CONFIG_PCI 449 /* PCI MEM space: cacheable */ 450 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ 451 | BATL_PP_RW \ 452 | BATL_MEMCOHERENCE) 453 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ 454 | BATU_BL_256M \ 455 | BATU_VS \ 456 | BATU_VP) 457 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 458 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 459 /* PCI MMIO space: cache-inhibit and guarded */ 460 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ 461 | BATL_PP_RW \ 462 | BATL_CACHEINHIBIT \ 463 | BATL_GUARDEDSTORAGE) 464 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ 465 | BATU_BL_256M \ 466 | BATU_VS \ 467 | BATU_VP) 468 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 469 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 470 #else 471 #define CONFIG_SYS_IBAT5L (0) 472 #define CONFIG_SYS_IBAT5U (0) 473 #define CONFIG_SYS_IBAT6L (0) 474 #define CONFIG_SYS_IBAT6U (0) 475 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 476 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 477 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 478 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 479 #endif 480 481 /* Nothing in BAT7 */ 482 #define CONFIG_SYS_IBAT7L (0) 483 #define CONFIG_SYS_IBAT7U (0) 484 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 485 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 486 487 #if (CONFIG_CMD_KGDB) 488 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 489 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 490 #endif 491 492 /* 493 * Environment Configuration 494 */ 495 #define CONFIG_ENV_OVERWRITE 496 497 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 498 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 499 500 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM 501 * (see CONFIG_SYS_I2C_EEPROM) */ 502 /* MAC address offset in I2C EEPROM */ 503 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 504 505 #define CONFIG_NETDEV "eth1" 506 507 #define CONFIG_HOSTNAME mpc8323erdb 508 #define CONFIG_ROOTPATH "/nfsroot" 509 #define CONFIG_BOOTFILE "uImage" 510 /* U-Boot image on TFTP server */ 511 #define CONFIG_UBOOTPATH "u-boot.bin" 512 #define CONFIG_FDTFILE "mpc832x_rdb.dtb" 513 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 514 515 /* default location for tftp and bootm */ 516 #define CONFIG_LOADADDR 800000 517 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 518 #define CONFIG_BAUDRATE 115200 519 520 #define XMK_STR(x) #x 521 #define MK_STR(x) XMK_STR(x) 522 523 #define CONFIG_EXTRA_ENV_SETTINGS \ 524 "netdev=" CONFIG_NETDEV "\0" \ 525 "uboot=" CONFIG_UBOOTPATH "\0" \ 526 "tftpflash=tftp $loadaddr $uboot;" \ 527 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 528 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 529 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 530 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 531 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 532 "fdtaddr=780000\0" \ 533 "fdtfile=" CONFIG_FDTFILE "\0" \ 534 "ramdiskaddr=1000000\0" \ 535 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 536 "console=ttyS0\0" \ 537 "setbootargs=setenv bootargs " \ 538 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ 539 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 540 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 541 "$netdev:off "\ 542 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 543 544 #define CONFIG_NFSBOOTCOMMAND \ 545 "setenv rootdev /dev/nfs;" \ 546 "run setbootargs;" \ 547 "run setipargs;" \ 548 "tftp $loadaddr $bootfile;" \ 549 "tftp $fdtaddr $fdtfile;" \ 550 "bootm $loadaddr - $fdtaddr" 551 552 #define CONFIG_RAMBOOTCOMMAND \ 553 "setenv rootdev /dev/ram;" \ 554 "run setbootargs;" \ 555 "tftp $ramdiskaddr $ramdiskfile;" \ 556 "tftp $loadaddr $bootfile;" \ 557 "tftp $fdtaddr $fdtfile;" \ 558 "bootm $loadaddr $ramdiskaddr $fdtaddr" 559 560 #undef MK_STR 561 #undef XMK_STR 562 563 #endif /* __CONFIG_H */ 564