1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License version 2 as published
6  * by the Free Software Foundation.
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300		1	/* E300 family */
16 #define CONFIG_QE		1	/* Has QE */
17 #define CONFIG_MPC832x		1	/* MPC832x CPU specific */
18 
19 /*
20  * System Clock Setup
21  */
22 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
23 
24 #ifndef CONFIG_SYS_CLK_FREQ
25 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
26 #endif
27 
28 /*
29  * Hardware Reset Configuration Word
30  */
31 #define CONFIG_SYS_HRCW_LOW (\
32 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
33 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
34 	HRCWL_VCO_1X2 |\
35 	HRCWL_CSB_TO_CLKIN_2X1 |\
36 	HRCWL_CORE_TO_CSB_2_5X1 |\
37 	HRCWL_CE_PLL_VCO_DIV_2 |\
38 	HRCWL_CE_PLL_DIV_1X1 |\
39 	HRCWL_CE_TO_PLL_1X3)
40 
41 #define CONFIG_SYS_HRCW_HIGH (\
42 	HRCWH_PCI_HOST |\
43 	HRCWH_PCI1_ARBITER_ENABLE |\
44 	HRCWH_CORE_ENABLE |\
45 	HRCWH_FROM_0X00000100 |\
46 	HRCWH_BOOTSEQ_DISABLE |\
47 	HRCWH_SW_WATCHDOG_DISABLE |\
48 	HRCWH_ROM_LOC_LOCAL_16BIT |\
49 	HRCWH_BIG_ENDIAN |\
50 	HRCWH_LALE_NORMAL)
51 
52 /*
53  * System IO Config
54  */
55 #define CONFIG_SYS_SICRL		0x00000000
56 
57 /*
58  * IMMR new address
59  */
60 #define CONFIG_SYS_IMMR		0xE0000000
61 
62 /*
63  * System performance
64  */
65 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
66 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
67 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
68 #define CONFIG_SYS_SPCR_OPT	1
69 
70 /*
71  * DDR Setup
72  */
73 #define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
74 #define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
76 
77 #undef CONFIG_SPD_EEPROM
78 #if defined(CONFIG_SPD_EEPROM)
79 /* Determine DDR configuration from I2C interface
80  */
81 #define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
82 #else
83 /* Manually set up DDR parameters
84  */
85 #define CONFIG_SYS_DDR_SIZE	64	/* MB */
86 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
87 				| CSCONFIG_ROW_BIT_13 \
88 				| CSCONFIG_COL_BIT_9)
89 				/* 0x80010101 */
90 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
91 				| (0 << TIMING_CFG0_WRT_SHIFT) \
92 				| (0 << TIMING_CFG0_RRT_SHIFT) \
93 				| (0 << TIMING_CFG0_WWT_SHIFT) \
94 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
95 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
96 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
97 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
98 				/* 0x00220802 */
99 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
100 				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
101 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
102 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
103 				| (3 << TIMING_CFG1_REFREC_SHIFT) \
104 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
105 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
106 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
107 				/* 0x26253222 */
108 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
109 				| (31 << TIMING_CFG2_CPO_SHIFT) \
110 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
111 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
112 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
113 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
114 				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
115 				/* 0x1f9048c7 */
116 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
117 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
118 				/* 0x02000000 */
119 #define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
120 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
121 				/* 0x44480232 */
122 #define CONFIG_SYS_DDR_MODE2	0x8000c000
123 #define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
124 				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
125 				/* 0x03200064 */
126 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
127 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
128 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
129 				| SDRAM_CFG_32_BE)
130 				/* 0x43080000 */
131 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
132 #endif
133 
134 /*
135  * Memory test
136  */
137 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
138 #define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
139 #define CONFIG_SYS_MEMTEST_END		0x03f00000
140 
141 /*
142  * The reserved memory
143  */
144 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
145 
146 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
147 #define CONFIG_SYS_RAMBOOT
148 #else
149 #undef  CONFIG_SYS_RAMBOOT
150 #endif
151 
152 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
153 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
154 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
155 
156 /*
157  * Initial RAM Base Address Setup
158  */
159 #define CONFIG_SYS_INIT_RAM_LOCK	1
160 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
161 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
162 #define CONFIG_SYS_GBL_DATA_OFFSET	\
163 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 
165 /*
166  * Local Bus Configuration & Clock Setup
167  */
168 #define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
169 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
170 #define CONFIG_SYS_LBC_LBCR		0x00000000
171 
172 /*
173  * FLASH on the Local Bus
174  */
175 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
176 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
177 #define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
178 #define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
179 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
180 
181 					/* Window base at flash base */
182 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
183 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
184 
185 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
186 				| BR_PS_16	/* 16 bit port */ \
187 				| BR_MS_GPCM	/* MSEL = GPCM */ \
188 				| BR_V)		/* valid */
189 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
190 				| OR_GPCM_XAM \
191 				| OR_GPCM_CSNT \
192 				| OR_GPCM_ACS_DIV2 \
193 				| OR_GPCM_XACS \
194 				| OR_GPCM_SCY_15 \
195 				| OR_GPCM_TRLX_SET \
196 				| OR_GPCM_EHTR_SET \
197 				| OR_GPCM_EAD)
198 				/* 0xFE006FF7 */
199 
200 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
202 
203 #undef CONFIG_SYS_FLASH_CHECKSUM
204 
205 /*
206  * Serial Port
207  */
208 #define CONFIG_SYS_NS16550_SERIAL
209 #define CONFIG_SYS_NS16550_REG_SIZE	1
210 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
211 
212 #define CONFIG_SYS_BAUDRATE_TABLE  \
213 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
214 
215 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
216 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
217 
218 /* I2C */
219 #define CONFIG_SYS_I2C
220 #define CONFIG_SYS_I2C_FSL
221 #define CONFIG_SYS_FSL_I2C_SPEED	400000
222 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
223 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
224 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
225 
226 /*
227  * Config on-board EEPROM
228  */
229 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
233 
234 /*
235  * General PCI
236  * Addresses are mapped 1-1.
237  */
238 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
239 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
240 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
241 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
242 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
243 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
244 #define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
245 #define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
246 #define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
247 
248 #ifdef CONFIG_PCI
249 #define CONFIG_PCI_INDIRECT_BRIDGE
250 #define CONFIG_PCI_SKIP_HOST_BRIDGE
251 
252 #undef CONFIG_EEPRO100
253 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
254 #define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
255 
256 #endif	/* CONFIG_PCI */
257 
258 /*
259  * QE UEC ethernet configuration
260  */
261 #define CONFIG_UEC_ETH
262 #define CONFIG_ETHPRIME		"UEC0"
263 
264 #define CONFIG_UEC_ETH1		/* ETH3 */
265 
266 #ifdef CONFIG_UEC_ETH1
267 #define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
268 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
269 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
270 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
271 #define CONFIG_SYS_UEC1_PHY_ADDR	4
272 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
273 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
274 #endif
275 
276 #define CONFIG_UEC_ETH2		/* ETH4 */
277 
278 #ifdef CONFIG_UEC_ETH2
279 #define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
280 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
281 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
282 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
283 #define CONFIG_SYS_UEC2_PHY_ADDR	0
284 #define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
285 #define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
286 #endif
287 
288 /*
289  * Environment
290  */
291 #ifndef CONFIG_SYS_RAMBOOT
292 	#define CONFIG_ENV_ADDR		\
293 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
294 	#define CONFIG_ENV_SECT_SIZE	0x20000
295 	#define CONFIG_ENV_SIZE		0x2000
296 #else
297 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
298 	#define CONFIG_ENV_SIZE		0x2000
299 #endif
300 
301 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
302 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
303 
304 /*
305  * BOOTP options
306  */
307 #define CONFIG_BOOTP_BOOTFILESIZE
308 
309 /*
310  * Command line configuration.
311  */
312 
313 #undef CONFIG_WATCHDOG		/* watchdog disabled */
314 
315 /*
316  * Miscellaneous configurable options
317  */
318 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
319 
320 /*
321  * For booting Linux, the board info and command line data
322  * have to be in the first 256 MB of memory, since this is
323  * the maximum mapped by the Linux kernel during initialization.
324  */
325 					/* Initial Memory map for Linux */
326 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
327 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
328 
329 /*
330  * Core HID Setup
331  */
332 #define CONFIG_SYS_HID0_INIT	0x000000000
333 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
334 				 HID0_ENABLE_INSTRUCTION_CACHE)
335 #define CONFIG_SYS_HID2		HID2_HBE
336 
337 /*
338  * MMU Setup
339  */
340 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
341 
342 /* DDR: cache cacheable */
343 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
344 				| BATL_PP_RW \
345 				| BATL_MEMCOHERENCE)
346 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
347 				| BATU_BL_256M \
348 				| BATU_VS \
349 				| BATU_VP)
350 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
351 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
352 
353 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
354 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
355 				| BATL_PP_RW \
356 				| BATL_CACHEINHIBIT \
357 				| BATL_GUARDEDSTORAGE)
358 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
359 				| BATU_BL_4M \
360 				| BATU_VS \
361 				| BATU_VP)
362 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
363 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
364 
365 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
366 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
367 				| BATL_PP_RW \
368 				| BATL_MEMCOHERENCE)
369 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
370 				| BATU_BL_32M \
371 				| BATU_VS \
372 				| BATU_VP)
373 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
374 				| BATL_PP_RW \
375 				| BATL_CACHEINHIBIT \
376 				| BATL_GUARDEDSTORAGE)
377 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
378 
379 #define CONFIG_SYS_IBAT3L	(0)
380 #define CONFIG_SYS_IBAT3U	(0)
381 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
382 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
383 
384 /* Stack in dcache: cacheable, no memory coherence */
385 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
386 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
387 				| BATU_BL_128K \
388 				| BATU_VS \
389 				| BATU_VP)
390 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
391 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
392 
393 #ifdef CONFIG_PCI
394 /* PCI MEM space: cacheable */
395 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_MEM_PHYS \
396 				| BATL_PP_RW \
397 				| BATL_MEMCOHERENCE)
398 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_MEM_PHYS \
399 				| BATU_BL_256M \
400 				| BATU_VS \
401 				| BATU_VP)
402 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
403 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
404 /* PCI MMIO space: cache-inhibit and guarded */
405 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MMIO_PHYS \
406 				| BATL_PP_RW \
407 				| BATL_CACHEINHIBIT \
408 				| BATL_GUARDEDSTORAGE)
409 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MMIO_PHYS \
410 				| BATU_BL_256M \
411 				| BATU_VS \
412 				| BATU_VP)
413 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
414 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
415 #else
416 #define CONFIG_SYS_IBAT5L	(0)
417 #define CONFIG_SYS_IBAT5U	(0)
418 #define CONFIG_SYS_IBAT6L	(0)
419 #define CONFIG_SYS_IBAT6U	(0)
420 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
421 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
422 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
423 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
424 #endif
425 
426 /* Nothing in BAT7 */
427 #define CONFIG_SYS_IBAT7L	(0)
428 #define CONFIG_SYS_IBAT7U	(0)
429 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
430 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
431 
432 #if (CONFIG_CMD_KGDB)
433 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
434 #endif
435 
436 /*
437  * Environment Configuration
438  */
439 #define CONFIG_ENV_OVERWRITE
440 
441 #define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
442 #define CONFIG_HAS_ETH1		/* add support for "eth1addr" */
443 
444 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
445  * (see CONFIG_SYS_I2C_EEPROM) */
446 					/* MAC address offset in I2C EEPROM */
447 #define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00
448 
449 #define CONFIG_NETDEV		"eth1"
450 
451 #define CONFIG_HOSTNAME		mpc8323erdb
452 #define CONFIG_ROOTPATH		"/nfsroot"
453 #define CONFIG_BOOTFILE		"uImage"
454 				/* U-Boot image on TFTP server */
455 #define CONFIG_UBOOTPATH	"u-boot.bin"
456 #define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
457 #define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
458 
459 				/* default location for tftp and bootm */
460 #define CONFIG_LOADADDR		800000
461 
462 #define CONFIG_EXTRA_ENV_SETTINGS \
463 	"netdev=" CONFIG_NETDEV "\0"					\
464 	"uboot=" CONFIG_UBOOTPATH "\0"					\
465 	"tftpflash=tftp $loadaddr $uboot;"				\
466 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
467 			" +$filesize; "	\
468 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
469 			" +$filesize; "	\
470 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
471 			" $filesize; "	\
472 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
473 			" +$filesize; "	\
474 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
475 			" $filesize\0"	\
476 	"fdtaddr=780000\0"						\
477 	"fdtfile=" CONFIG_FDTFILE "\0"					\
478 	"ramdiskaddr=1000000\0"						\
479 	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
480 	"console=ttyS0\0"						\
481 	"setbootargs=setenv bootargs "					\
482 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
483 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
484 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
485 								"$netdev:off "\
486 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
487 
488 #define CONFIG_NFSBOOTCOMMAND						\
489 	"setenv rootdev /dev/nfs;"					\
490 	"run setbootargs;"						\
491 	"run setipargs;"						\
492 	"tftp $loadaddr $bootfile;"					\
493 	"tftp $fdtaddr $fdtfile;"					\
494 	"bootm $loadaddr - $fdtaddr"
495 
496 #define CONFIG_RAMBOOTCOMMAND						\
497 	"setenv rootdev /dev/ram;"					\
498 	"run setbootargs;"						\
499 	"tftp $ramdiskaddr $ramdiskfile;"				\
500 	"tftp $loadaddr $bootfile;"					\
501 	"tftp $fdtaddr $fdtfile;"					\
502 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
503 
504 #endif	/* __CONFIG_H */
505