1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC83XX 1 /* MPC83xx family */ 18 #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ 19 20 #define CONFIG_PCI 1 21 #define CONFIG_83XX_GENERIC_PCI 1 22 23 /* 24 * System Clock Setup 25 */ 26 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 27 28 #ifndef CONFIG_SYS_CLK_FREQ 29 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 30 #endif 31 32 /* 33 * Hardware Reset Configuration Word 34 */ 35 #define CFG_HRCW_LOW (\ 36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 37 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 38 HRCWL_VCO_1X2 |\ 39 HRCWL_CSB_TO_CLKIN_2X1 |\ 40 HRCWL_CORE_TO_CSB_2_5X1 |\ 41 HRCWL_CE_PLL_VCO_DIV_2 |\ 42 HRCWL_CE_PLL_DIV_1X1 |\ 43 HRCWL_CE_TO_PLL_1X3) 44 45 #define CFG_HRCW_HIGH (\ 46 HRCWH_PCI_HOST |\ 47 HRCWH_PCI1_ARBITER_ENABLE |\ 48 HRCWH_CORE_ENABLE |\ 49 HRCWH_FROM_0X00000100 |\ 50 HRCWH_BOOTSEQ_DISABLE |\ 51 HRCWH_SW_WATCHDOG_DISABLE |\ 52 HRCWH_ROM_LOC_LOCAL_16BIT |\ 53 HRCWH_BIG_ENDIAN |\ 54 HRCWH_LALE_NORMAL) 55 56 /* 57 * System IO Config 58 */ 59 #define CFG_SICRL 0x00000000 60 61 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 62 63 /* 64 * IMMR new address 65 */ 66 #define CFG_IMMR 0xE0000000 67 68 /* 69 * DDR Setup 70 */ 71 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 72 #define CFG_SDRAM_BASE CFG_DDR_BASE 73 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 74 #define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 75 76 #undef CONFIG_SPD_EEPROM 77 #if defined(CONFIG_SPD_EEPROM) 78 /* Determine DDR configuration from I2C interface 79 */ 80 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 81 #else 82 /* Manually set up DDR parameters 83 */ 84 #define CFG_DDR_SIZE 64 /* MB */ 85 #define CFG_DDR_CS0_CONFIG 0x80840101 86 #define CFG_DDR_TIMING_0 0x00220802 87 #define CFG_DDR_TIMING_1 0x3935d322 88 #define CFG_DDR_TIMING_2 0x0f9048ca 89 #define CFG_DDR_TIMING_3 0x00000000 90 #define CFG_DDR_CLK_CNTL 0x02000000 91 #define CFG_DDR_MODE 0x44400232 92 #define CFG_DDR_MODE2 0x8000c000 93 #define CFG_DDR_INTERVAL 0x03200064 94 #define CFG_DDR_CS0_BNDS 0x00000003 95 #define CFG_DDR_SDRAM_CFG 0x43080000 96 #define CFG_DDR_SDRAM_CFG2 0x00401000 97 #endif 98 99 /* 100 * Memory test 101 */ 102 #undef CFG_DRAM_TEST /* memory test, takes time */ 103 #define CFG_MEMTEST_START 0x00030000 /* memtest region */ 104 #define CFG_MEMTEST_END 0x03f00000 105 106 /* 107 * The reserved memory 108 */ 109 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 110 111 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 112 #define CFG_RAMBOOT 113 #else 114 #undef CFG_RAMBOOT 115 #endif 116 117 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 118 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 119 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 120 121 /* 122 * Initial RAM Base Address Setup 123 */ 124 #define CFG_INIT_RAM_LOCK 1 125 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 126 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 127 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 128 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 129 130 /* 131 * Local Bus Configuration & Clock Setup 132 */ 133 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) 134 #define CFG_LBC_LBCR 0x00000000 135 136 /* 137 * FLASH on the Local Bus 138 */ 139 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 140 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 141 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 142 #define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ 143 144 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 145 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 146 147 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ 148 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 149 BR_V) /* valid */ 150 #define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 151 152 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 153 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 154 155 #undef CFG_FLASH_CHECKSUM 156 157 /* 158 * SDRAM on the Local Bus 159 */ 160 #undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ 161 162 #ifdef CFG_LB_SDRAM 163 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 164 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 165 166 #define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE 167 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 168 169 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 170 /* 171 * Base Register 2 and Option Register 2 configure SDRAM. 172 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 173 * 174 * For BR2, need: 175 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 176 * port size = 32-bits = BR2[19:20] = 11 177 * no parity checking = BR2[21:22] = 00 178 * SDRAM for MSEL = BR2[24:26] = 011 179 * Valid = BR[31] = 1 180 * 181 * 0 4 8 12 16 20 24 28 182 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 183 * 184 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into 185 * the top 17 bits of BR2. 186 */ 187 188 #define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 189 190 /* 191 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 192 * 193 * For OR2, need: 194 * 64MB mask for AM, OR2[0:7] = 1111 1100 195 * XAM, OR2[17:18] = 11 196 * 9 columns OR2[19-21] = 010 197 * 13 rows OR2[23-25] = 100 198 * EAD set for extra time OR[31] = 1 199 * 200 * 0 4 8 12 16 20 24 28 201 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 202 */ 203 204 #define CFG_OR2_PRELIM 0xfc006901 205 206 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 207 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 208 209 /* 210 * LSDMR masks 211 */ 212 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 213 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 214 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 215 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 216 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 217 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 218 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 219 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 220 221 #define CFG_LBC_LSDMR_COMMON 0x0063b723 222 223 /* 224 * SDRAM Controller configuration sequence. 225 */ 226 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 227 | CFG_LBC_LSDMR_OP_PCHALL) 228 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 229 | CFG_LBC_LSDMR_OP_ARFRSH) 230 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 231 | CFG_LBC_LSDMR_OP_ARFRSH) 232 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 233 | CFG_LBC_LSDMR_OP_MRW) 234 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 235 | CFG_LBC_LSDMR_OP_NORMAL) 236 237 #endif 238 239 /* 240 * Windows to access PIB via local bus 241 */ 242 #define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ 243 #define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 244 245 /* 246 * Serial Port 247 */ 248 #define CONFIG_CONS_INDEX 1 249 #undef CONFIG_SERIAL_SOFTWARE_FIFO 250 #define CFG_NS16550 251 #define CFG_NS16550_SERIAL 252 #define CFG_NS16550_REG_SIZE 1 253 #define CFG_NS16550_CLK get_bus_freq(0) 254 255 #define CFG_BAUDRATE_TABLE \ 256 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 257 258 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 259 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 260 261 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 262 /* Use the HUSH parser */ 263 #define CFG_HUSH_PARSER 264 #ifdef CFG_HUSH_PARSER 265 #define CFG_PROMPT_HUSH_PS2 "> " 266 #endif 267 268 /* pass open firmware flat tree */ 269 #define CONFIG_OF_LIBFDT 1 270 #define CONFIG_OF_BOARD_SETUP 1 271 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 272 273 /* I2C */ 274 #define CONFIG_HARD_I2C /* I2C with hardware support */ 275 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 276 #define CONFIG_FSL_I2C 277 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 278 #define CFG_I2C_SLAVE 0x7F 279 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 280 #define CFG_I2C_OFFSET 0x3000 281 282 /* 283 * Config on-board RTC 284 */ 285 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 286 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 287 288 /* 289 * General PCI 290 * Addresses are mapped 1-1. 291 */ 292 #define CFG_PCI1_MEM_BASE 0x80000000 293 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 294 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 295 #define CFG_PCI1_MMIO_BASE 0x90000000 296 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 297 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 298 #define CFG_PCI1_IO_BASE 0xd0000000 299 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 300 #define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */ 301 302 #ifdef CONFIG_PCI 303 304 #define CONFIG_NET_MULTI 305 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 306 307 #undef CONFIG_EEPRO100 308 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 309 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 310 311 #endif /* CONFIG_PCI */ 312 313 314 #ifndef CONFIG_NET_MULTI 315 #define CONFIG_NET_MULTI 1 316 #endif 317 318 /* 319 * QE UEC ethernet configuration 320 */ 321 #define CONFIG_UEC_ETH 322 #define CONFIG_ETHPRIME "FSL UEC0" 323 324 #define CONFIG_UEC_ETH1 /* ETH3 */ 325 326 #ifdef CONFIG_UEC_ETH1 327 #define CFG_UEC1_UCC_NUM 2 /* UCC3 */ 328 #define CFG_UEC1_RX_CLK QE_CLK9 329 #define CFG_UEC1_TX_CLK QE_CLK10 330 #define CFG_UEC1_ETH_TYPE FAST_ETH 331 #define CFG_UEC1_PHY_ADDR 4 332 #define CFG_UEC1_INTERFACE_MODE ENET_100_MII 333 #endif 334 335 #define CONFIG_UEC_ETH2 /* ETH4 */ 336 337 #ifdef CONFIG_UEC_ETH2 338 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 339 #define CFG_UEC2_RX_CLK QE_CLK16 340 #define CFG_UEC2_TX_CLK QE_CLK3 341 #define CFG_UEC2_ETH_TYPE FAST_ETH 342 #define CFG_UEC2_PHY_ADDR 0 343 #define CFG_UEC2_INTERFACE_MODE ENET_100_MII 344 #endif 345 346 /* 347 * Environment 348 */ 349 #ifndef CFG_RAMBOOT 350 #define CFG_ENV_IS_IN_FLASH 1 351 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 352 #define CFG_ENV_SECT_SIZE 0x20000 353 #define CFG_ENV_SIZE 0x2000 354 #else 355 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 356 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 357 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 358 #define CFG_ENV_SIZE 0x2000 359 #endif 360 361 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 362 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 363 364 /* 365 * BOOTP options 366 */ 367 #define CONFIG_BOOTP_BOOTFILESIZE 368 #define CONFIG_BOOTP_BOOTPATH 369 #define CONFIG_BOOTP_GATEWAY 370 #define CONFIG_BOOTP_HOSTNAME 371 372 /* 373 * Command line configuration. 374 */ 375 #include <config_cmd_default.h> 376 377 #define CONFIG_CMD_PING 378 #define CONFIG_CMD_I2C 379 #define CONFIG_CMD_ASKENV 380 381 #if defined(CONFIG_PCI) 382 #define CONFIG_CMD_PCI 383 #endif 384 #if defined(CFG_RAMBOOT) 385 #undef CONFIG_CMD_ENV 386 #undef CONFIG_CMD_LOADS 387 #endif 388 389 #undef CONFIG_WATCHDOG /* watchdog disabled */ 390 391 /* 392 * Miscellaneous configurable options 393 */ 394 #define CFG_LONGHELP /* undef to save memory */ 395 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 396 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 397 398 #if (CONFIG_CMD_KGDB) 399 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 400 #else 401 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 402 #endif 403 404 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 405 #define CFG_MAXARGS 16 /* max number of command args */ 406 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 407 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 408 409 /* 410 * For booting Linux, the board info and command line data 411 * have to be in the first 8 MB of memory, since this is 412 * the maximum mapped by the Linux kernel during initialization. 413 */ 414 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 415 416 /* 417 * Core HID Setup 418 */ 419 #define CFG_HID0_INIT 0x000000000 420 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 421 #define CFG_HID2 HID2_HBE 422 423 /* 424 * MMU Setup 425 */ 426 427 /* DDR: cache cacheable */ 428 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 429 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 430 #define CFG_DBAT0L CFG_IBAT0L 431 #define CFG_DBAT0U CFG_IBAT0U 432 433 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 434 #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ 435 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 436 #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 437 #define CFG_DBAT1L CFG_IBAT1L 438 #define CFG_DBAT1U CFG_IBAT1U 439 440 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 441 #define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 442 #define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 443 #define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ 444 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 445 #define CFG_DBAT2U CFG_IBAT2U 446 447 #define CFG_IBAT3L (0) 448 #define CFG_IBAT3U (0) 449 #define CFG_DBAT3L CFG_IBAT3L 450 #define CFG_DBAT3U CFG_IBAT3U 451 452 /* Stack in dcache: cacheable, no memory coherence */ 453 #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) 454 #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 455 #define CFG_DBAT4L CFG_IBAT4L 456 #define CFG_DBAT4U CFG_IBAT4U 457 458 #ifdef CONFIG_PCI 459 /* PCI MEM space: cacheable */ 460 #define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 461 #define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 462 #define CFG_DBAT5L CFG_IBAT5L 463 #define CFG_DBAT5U CFG_IBAT5U 464 /* PCI MMIO space: cache-inhibit and guarded */ 465 #define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ 466 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 467 #define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 468 #define CFG_DBAT6L CFG_IBAT6L 469 #define CFG_DBAT6U CFG_IBAT6U 470 #else 471 #define CFG_IBAT5L (0) 472 #define CFG_IBAT5U (0) 473 #define CFG_IBAT6L (0) 474 #define CFG_IBAT6U (0) 475 #define CFG_DBAT5L CFG_IBAT5L 476 #define CFG_DBAT5U CFG_IBAT5U 477 #define CFG_DBAT6L CFG_IBAT6L 478 #define CFG_DBAT6U CFG_IBAT6U 479 #endif 480 481 /* Nothing in BAT7 */ 482 #define CFG_IBAT7L (0) 483 #define CFG_IBAT7U (0) 484 #define CFG_DBAT7L CFG_IBAT7L 485 #define CFG_DBAT7U CFG_IBAT7U 486 487 /* 488 * Internal Definitions 489 * 490 * Boot Flags 491 */ 492 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 493 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 494 495 #if (CONFIG_CMD_KGDB) 496 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 497 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 498 #endif 499 500 /* 501 * Environment Configuration 502 */ 503 #define CONFIG_ENV_OVERWRITE 504 505 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 506 #define CONFIG_ETHADDR 00:04:9f:ef:03:01 507 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 508 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 509 510 #define CONFIG_IPADDR 10.0.0.2 511 #define CONFIG_SERVERIP 10.0.0.1 512 #define CONFIG_GATEWAYIP 10.0.0.1 513 #define CONFIG_NETMASK 255.0.0.0 514 #define CONFIG_NETDEV eth1 515 516 #define CONFIG_HOSTNAME mpc8323erdb 517 #define CONFIG_ROOTPATH /nfsroot 518 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 519 #define CONFIG_BOOTFILE uImage 520 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 521 #define CONFIG_FDTFILE mpc832x_rdb.dtb 522 523 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 524 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 525 #define CONFIG_BAUDRATE 115200 526 527 #define XMK_STR(x) #x 528 #define MK_STR(x) XMK_STR(x) 529 530 #define CONFIG_EXTRA_ENV_SETTINGS \ 531 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 532 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 533 "tftpflash=tftp $loadaddr $uboot;" \ 534 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 535 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 536 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 537 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 538 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 539 "fdtaddr=400000\0" \ 540 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 541 "ramdiskaddr=1000000\0" \ 542 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 543 "console=ttyS0\0" \ 544 "setbootargs=setenv bootargs " \ 545 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 546 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 548 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 549 550 #define CONFIG_NFSBOOTCOMMAND \ 551 "setenv rootdev /dev/nfs;" \ 552 "run setbootargs;" \ 553 "run setipargs;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "tftp $fdtaddr $fdtfile;" \ 556 "bootm $loadaddr - $fdtaddr" 557 558 #define CONFIG_RAMBOOTCOMMAND \ 559 "setenv rootdev /dev/ram;" \ 560 "run setbootargs;" \ 561 "tftp $ramdiskaddr $ramdiskfile;" \ 562 "tftp $loadaddr $bootfile;" \ 563 "tftp $fdtaddr $fdtfile;" \ 564 "bootm $loadaddr $ramdiskaddr $fdtaddr" 565 566 #undef MK_STR 567 #undef XMK_STR 568 569 #endif /* __CONFIG_H */ 570