1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 18 19 #define CONFIG_SYS_TEXT_BASE 0xFE000000 20 21 #define CONFIG_PCI 1 22 23 /* 24 * System Clock Setup 25 */ 26 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 27 28 #ifndef CONFIG_SYS_CLK_FREQ 29 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 30 #endif 31 32 /* 33 * Hardware Reset Configuration Word 34 */ 35 #define CONFIG_SYS_HRCW_LOW (\ 36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 37 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 38 HRCWL_VCO_1X2 |\ 39 HRCWL_CSB_TO_CLKIN_2X1 |\ 40 HRCWL_CORE_TO_CSB_2_5X1 |\ 41 HRCWL_CE_PLL_VCO_DIV_2 |\ 42 HRCWL_CE_PLL_DIV_1X1 |\ 43 HRCWL_CE_TO_PLL_1X3) 44 45 #define CONFIG_SYS_HRCW_HIGH (\ 46 HRCWH_PCI_HOST |\ 47 HRCWH_PCI1_ARBITER_ENABLE |\ 48 HRCWH_CORE_ENABLE |\ 49 HRCWH_FROM_0X00000100 |\ 50 HRCWH_BOOTSEQ_DISABLE |\ 51 HRCWH_SW_WATCHDOG_DISABLE |\ 52 HRCWH_ROM_LOC_LOCAL_16BIT |\ 53 HRCWH_BIG_ENDIAN |\ 54 HRCWH_LALE_NORMAL) 55 56 /* 57 * System IO Config 58 */ 59 #define CONFIG_SYS_SICRL 0x00000000 60 61 /* 62 * IMMR new address 63 */ 64 #define CONFIG_SYS_IMMR 0xE0000000 65 66 /* 67 * System performance 68 */ 69 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 70 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 71 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 72 #define CONFIG_SYS_SPCR_OPT 1 73 74 /* 75 * DDR Setup 76 */ 77 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 79 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 80 81 #undef CONFIG_SPD_EEPROM 82 #if defined(CONFIG_SPD_EEPROM) 83 /* Determine DDR configuration from I2C interface 84 */ 85 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 86 #else 87 /* Manually set up DDR parameters 88 */ 89 #define CONFIG_SYS_DDR_SIZE 64 /* MB */ 90 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 91 | CSCONFIG_ROW_BIT_13 \ 92 | CSCONFIG_COL_BIT_9) 93 /* 0x80010101 */ 94 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 95 | (0 << TIMING_CFG0_WRT_SHIFT) \ 96 | (0 << TIMING_CFG0_RRT_SHIFT) \ 97 | (0 << TIMING_CFG0_WWT_SHIFT) \ 98 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 99 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 100 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 101 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 102 /* 0x00220802 */ 103 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 104 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 105 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 106 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 107 | (3 << TIMING_CFG1_REFREC_SHIFT) \ 108 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 109 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 110 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 111 /* 0x26253222 */ 112 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 113 | (31 << TIMING_CFG2_CPO_SHIFT) \ 114 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 115 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 116 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 117 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 118 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 119 /* 0x1f9048c7 */ 120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 121 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 122 /* 0x02000000 */ 123 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 124 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 125 /* 0x44480232 */ 126 #define CONFIG_SYS_DDR_MODE2 0x8000c000 127 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 128 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 129 /* 0x03200064 */ 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 131 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 132 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 133 | SDRAM_CFG_32_BE) 134 /* 0x43080000 */ 135 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 136 #endif 137 138 /* 139 * Memory test 140 */ 141 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 142 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ 143 #define CONFIG_SYS_MEMTEST_END 0x03f00000 144 145 /* 146 * The reserved memory 147 */ 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 149 150 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 151 #define CONFIG_SYS_RAMBOOT 152 #else 153 #undef CONFIG_SYS_RAMBOOT 154 #endif 155 156 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 157 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 158 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 159 160 /* 161 * Initial RAM Base Address Setup 162 */ 163 #define CONFIG_SYS_INIT_RAM_LOCK 1 164 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 165 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 166 #define CONFIG_SYS_GBL_DATA_OFFSET \ 167 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 168 169 /* 170 * Local Bus Configuration & Clock Setup 171 */ 172 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 173 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 174 #define CONFIG_SYS_LBC_LBCR 0x00000000 175 176 /* 177 * FLASH on the Local Bus 178 */ 179 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 180 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 181 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 182 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 183 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 184 185 /* Window base at flash base */ 186 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 187 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 188 189 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 190 | BR_PS_16 /* 16 bit port */ \ 191 | BR_MS_GPCM /* MSEL = GPCM */ \ 192 | BR_V) /* valid */ 193 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 194 | OR_GPCM_XAM \ 195 | OR_GPCM_CSNT \ 196 | OR_GPCM_ACS_DIV2 \ 197 | OR_GPCM_XACS \ 198 | OR_GPCM_SCY_15 \ 199 | OR_GPCM_TRLX_SET \ 200 | OR_GPCM_EHTR_SET \ 201 | OR_GPCM_EAD) 202 /* 0xFE006FF7 */ 203 204 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 205 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 206 207 #undef CONFIG_SYS_FLASH_CHECKSUM 208 209 /* 210 * Serial Port 211 */ 212 #define CONFIG_CONS_INDEX 1 213 #define CONFIG_SYS_NS16550_SERIAL 214 #define CONFIG_SYS_NS16550_REG_SIZE 1 215 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 216 217 #define CONFIG_SYS_BAUDRATE_TABLE \ 218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 219 220 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 221 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 222 223 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 224 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 225 226 /* I2C */ 227 #define CONFIG_SYS_I2C 228 #define CONFIG_SYS_I2C_FSL 229 #define CONFIG_SYS_FSL_I2C_SPEED 400000 230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 232 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 233 234 /* 235 * Config on-board EEPROM 236 */ 237 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 241 242 /* 243 * General PCI 244 * Addresses are mapped 1-1. 245 */ 246 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 247 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 248 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 249 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 250 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 251 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 252 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 253 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 254 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ 255 256 #ifdef CONFIG_PCI 257 #define CONFIG_PCI_INDIRECT_BRIDGE 258 #define CONFIG_PCI_SKIP_HOST_BRIDGE 259 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 260 261 #undef CONFIG_EEPRO100 262 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 263 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 264 265 #endif /* CONFIG_PCI */ 266 267 /* 268 * QE UEC ethernet configuration 269 */ 270 #define CONFIG_UEC_ETH 271 #define CONFIG_ETHPRIME "UEC0" 272 273 #define CONFIG_UEC_ETH1 /* ETH3 */ 274 275 #ifdef CONFIG_UEC_ETH1 276 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 277 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 278 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 279 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 280 #define CONFIG_SYS_UEC1_PHY_ADDR 4 281 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 282 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 283 #endif 284 285 #define CONFIG_UEC_ETH2 /* ETH4 */ 286 287 #ifdef CONFIG_UEC_ETH2 288 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 289 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 290 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 291 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 292 #define CONFIG_SYS_UEC2_PHY_ADDR 0 293 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 294 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 295 #endif 296 297 /* 298 * Environment 299 */ 300 #ifndef CONFIG_SYS_RAMBOOT 301 #define CONFIG_ENV_IS_IN_FLASH 1 302 #define CONFIG_ENV_ADDR \ 303 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 304 #define CONFIG_ENV_SECT_SIZE 0x20000 305 #define CONFIG_ENV_SIZE 0x2000 306 #else 307 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 308 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 309 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 310 #define CONFIG_ENV_SIZE 0x2000 311 #endif 312 313 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 314 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 315 316 /* 317 * BOOTP options 318 */ 319 #define CONFIG_BOOTP_BOOTFILESIZE 320 #define CONFIG_BOOTP_BOOTPATH 321 #define CONFIG_BOOTP_GATEWAY 322 #define CONFIG_BOOTP_HOSTNAME 323 324 /* 325 * Command line configuration. 326 */ 327 #define CONFIG_CMD_EEPROM 328 329 #if defined(CONFIG_PCI) 330 #define CONFIG_CMD_PCI 331 #endif 332 333 #undef CONFIG_WATCHDOG /* watchdog disabled */ 334 335 /* 336 * Miscellaneous configurable options 337 */ 338 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 339 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 340 341 #if (CONFIG_CMD_KGDB) 342 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 343 #else 344 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 345 #endif 346 347 /* Print Buffer Size */ 348 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 349 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 350 /* Boot Argument Buffer Size */ 351 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 352 353 /* 354 * For booting Linux, the board info and command line data 355 * have to be in the first 256 MB of memory, since this is 356 * the maximum mapped by the Linux kernel during initialization. 357 */ 358 /* Initial Memory map for Linux */ 359 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 360 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 361 362 /* 363 * Core HID Setup 364 */ 365 #define CONFIG_SYS_HID0_INIT 0x000000000 366 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 367 HID0_ENABLE_INSTRUCTION_CACHE) 368 #define CONFIG_SYS_HID2 HID2_HBE 369 370 /* 371 * MMU Setup 372 */ 373 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 374 375 /* DDR: cache cacheable */ 376 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 377 | BATL_PP_RW \ 378 | BATL_MEMCOHERENCE) 379 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 380 | BATU_BL_256M \ 381 | BATU_VS \ 382 | BATU_VP) 383 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 384 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 385 386 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 387 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 388 | BATL_PP_RW \ 389 | BATL_CACHEINHIBIT \ 390 | BATL_GUARDEDSTORAGE) 391 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 392 | BATU_BL_4M \ 393 | BATU_VS \ 394 | BATU_VP) 395 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 396 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 397 398 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 399 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 400 | BATL_PP_RW \ 401 | BATL_MEMCOHERENCE) 402 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 403 | BATU_BL_32M \ 404 | BATU_VS \ 405 | BATU_VP) 406 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 407 | BATL_PP_RW \ 408 | BATL_CACHEINHIBIT \ 409 | BATL_GUARDEDSTORAGE) 410 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 411 412 #define CONFIG_SYS_IBAT3L (0) 413 #define CONFIG_SYS_IBAT3U (0) 414 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 415 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 416 417 /* Stack in dcache: cacheable, no memory coherence */ 418 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 419 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ 420 | BATU_BL_128K \ 421 | BATU_VS \ 422 | BATU_VP) 423 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 424 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 425 426 #ifdef CONFIG_PCI 427 /* PCI MEM space: cacheable */ 428 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ 429 | BATL_PP_RW \ 430 | BATL_MEMCOHERENCE) 431 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ 432 | BATU_BL_256M \ 433 | BATU_VS \ 434 | BATU_VP) 435 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 436 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 437 /* PCI MMIO space: cache-inhibit and guarded */ 438 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ 439 | BATL_PP_RW \ 440 | BATL_CACHEINHIBIT \ 441 | BATL_GUARDEDSTORAGE) 442 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ 443 | BATU_BL_256M \ 444 | BATU_VS \ 445 | BATU_VP) 446 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 447 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 448 #else 449 #define CONFIG_SYS_IBAT5L (0) 450 #define CONFIG_SYS_IBAT5U (0) 451 #define CONFIG_SYS_IBAT6L (0) 452 #define CONFIG_SYS_IBAT6U (0) 453 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 454 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 455 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 456 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 457 #endif 458 459 /* Nothing in BAT7 */ 460 #define CONFIG_SYS_IBAT7L (0) 461 #define CONFIG_SYS_IBAT7U (0) 462 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 463 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 464 465 #if (CONFIG_CMD_KGDB) 466 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 467 #endif 468 469 /* 470 * Environment Configuration 471 */ 472 #define CONFIG_ENV_OVERWRITE 473 474 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 475 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 476 477 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM 478 * (see CONFIG_SYS_I2C_EEPROM) */ 479 /* MAC address offset in I2C EEPROM */ 480 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 481 482 #define CONFIG_NETDEV "eth1" 483 484 #define CONFIG_HOSTNAME mpc8323erdb 485 #define CONFIG_ROOTPATH "/nfsroot" 486 #define CONFIG_BOOTFILE "uImage" 487 /* U-Boot image on TFTP server */ 488 #define CONFIG_UBOOTPATH "u-boot.bin" 489 #define CONFIG_FDTFILE "mpc832x_rdb.dtb" 490 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 491 492 /* default location for tftp and bootm */ 493 #define CONFIG_LOADADDR 800000 494 #define CONFIG_BAUDRATE 115200 495 496 #define CONFIG_EXTRA_ENV_SETTINGS \ 497 "netdev=" CONFIG_NETDEV "\0" \ 498 "uboot=" CONFIG_UBOOTPATH "\0" \ 499 "tftpflash=tftp $loadaddr $uboot;" \ 500 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 501 " +$filesize; " \ 502 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 503 " +$filesize; " \ 504 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 505 " $filesize; " \ 506 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 507 " +$filesize; " \ 508 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 509 " $filesize\0" \ 510 "fdtaddr=780000\0" \ 511 "fdtfile=" CONFIG_FDTFILE "\0" \ 512 "ramdiskaddr=1000000\0" \ 513 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 514 "console=ttyS0\0" \ 515 "setbootargs=setenv bootargs " \ 516 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ 517 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 518 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 519 "$netdev:off "\ 520 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 521 522 #define CONFIG_NFSBOOTCOMMAND \ 523 "setenv rootdev /dev/nfs;" \ 524 "run setbootargs;" \ 525 "run setipargs;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr - $fdtaddr" 529 530 #define CONFIG_RAMBOOTCOMMAND \ 531 "setenv rootdev /dev/ram;" \ 532 "run setbootargs;" \ 533 "tftp $ramdiskaddr $ramdiskfile;" \ 534 "tftp $loadaddr $bootfile;" \ 535 "tftp $fdtaddr $fdtfile;" \ 536 "bootm $loadaddr $ramdiskaddr $fdtaddr" 537 538 #endif /* __CONFIG_H */ 539