1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 18 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_PCI 1 23 24 /* 25 * System Clock Setup 26 */ 27 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 28 29 #ifndef CONFIG_SYS_CLK_FREQ 30 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 31 #endif 32 33 /* 34 * Hardware Reset Configuration Word 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 39 HRCWL_VCO_1X2 |\ 40 HRCWL_CSB_TO_CLKIN_2X1 |\ 41 HRCWL_CORE_TO_CSB_2_5X1 |\ 42 HRCWL_CE_PLL_VCO_DIV_2 |\ 43 HRCWL_CE_PLL_DIV_1X1 |\ 44 HRCWL_CE_TO_PLL_1X3) 45 46 #define CONFIG_SYS_HRCW_HIGH (\ 47 HRCWH_PCI_HOST |\ 48 HRCWH_PCI1_ARBITER_ENABLE |\ 49 HRCWH_CORE_ENABLE |\ 50 HRCWH_FROM_0X00000100 |\ 51 HRCWH_BOOTSEQ_DISABLE |\ 52 HRCWH_SW_WATCHDOG_DISABLE |\ 53 HRCWH_ROM_LOC_LOCAL_16BIT |\ 54 HRCWH_BIG_ENDIAN |\ 55 HRCWH_LALE_NORMAL) 56 57 /* 58 * System IO Config 59 */ 60 #define CONFIG_SYS_SICRL 0x00000000 61 62 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 63 64 /* 65 * IMMR new address 66 */ 67 #define CONFIG_SYS_IMMR 0xE0000000 68 69 /* 70 * System performance 71 */ 72 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 73 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 74 #define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 75 76 /* 77 * DDR Setup 78 */ 79 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 81 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 82 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 83 84 #undef CONFIG_SPD_EEPROM 85 #if defined(CONFIG_SPD_EEPROM) 86 /* Determine DDR configuration from I2C interface 87 */ 88 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 89 #else 90 /* Manually set up DDR parameters 91 */ 92 #define CONFIG_SYS_DDR_SIZE 64 /* MB */ 93 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ 94 | CSCONFIG_ODT_WR_ACS \ 95 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) 96 /* 0x80010101 */ 97 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 98 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 99 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 100 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 101 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 102 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 103 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 104 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 105 /* 0x00220802 */ 106 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ 107 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 108 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ 109 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 110 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ 111 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ 112 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 113 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 114 /* 0x26253222 */ 115 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 116 | (31 << TIMING_CFG2_CPO_SHIFT ) \ 117 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 118 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 119 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 120 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 121 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 122 /* 0x1f9048c7 */ 123 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 124 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 125 /* 0x02000000 */ 126 #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 127 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 128 /* 0x44480232 */ 129 #define CONFIG_SYS_DDR_MODE2 0x8000c000 130 #define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 131 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 132 /* 0x03200064 */ 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 134 #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ 135 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 136 | SDRAM_CFG_32_BE ) 137 /* 0x43080000 */ 138 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 139 #endif 140 141 /* 142 * Memory test 143 */ 144 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 145 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ 146 #define CONFIG_SYS_MEMTEST_END 0x03f00000 147 148 /* 149 * The reserved memory 150 */ 151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 152 153 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 154 #define CONFIG_SYS_RAMBOOT 155 #else 156 #undef CONFIG_SYS_RAMBOOT 157 #endif 158 159 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 160 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 161 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 162 163 /* 164 * Initial RAM Base Address Setup 165 */ 166 #define CONFIG_SYS_INIT_RAM_LOCK 1 167 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 168 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 169 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 171 172 /* 173 * Local Bus Configuration & Clock Setup 174 */ 175 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 176 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 177 #define CONFIG_SYS_LBC_LBCR 0x00000000 178 179 /* 180 * FLASH on the Local Bus 181 */ 182 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 183 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 184 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 185 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 186 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 187 188 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 189 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 190 191 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ 192 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 193 BR_V) /* valid */ 194 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 195 196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 197 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 198 199 #undef CONFIG_SYS_FLASH_CHECKSUM 200 201 /* 202 * SDRAM on the Local Bus 203 */ 204 #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ 205 206 #ifdef CONFIG_SYS_LB_SDRAM 207 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 208 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 209 210 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 211 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 212 213 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 214 /* 215 * Base Register 2 and Option Register 2 configure SDRAM. 216 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 217 * 218 * For BR2, need: 219 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 220 * port size = 32-bits = BR2[19:20] = 11 221 * no parity checking = BR2[21:22] = 00 222 * SDRAM for MSEL = BR2[24:26] = 011 223 * Valid = BR[31] = 1 224 * 225 * 0 4 8 12 16 20 24 28 226 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 227 * 228 * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 229 * the top 17 bits of BR2. 230 */ 231 232 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 233 234 /* 235 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 236 * 237 * For OR2, need: 238 * 64MB mask for AM, OR2[0:7] = 1111 1100 239 * XAM, OR2[17:18] = 11 240 * 9 columns OR2[19-21] = 010 241 * 13 rows OR2[23-25] = 100 242 * EAD set for extra time OR[31] = 1 243 * 244 * 0 4 8 12 16 20 24 28 245 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 246 */ 247 248 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 249 250 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 251 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 252 253 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 254 255 #endif 256 257 /* 258 * Windows to access PIB via local bus 259 */ 260 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ 261 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 262 263 /* 264 * Serial Port 265 */ 266 #define CONFIG_CONS_INDEX 1 267 #define CONFIG_SYS_NS16550 268 #define CONFIG_SYS_NS16550_SERIAL 269 #define CONFIG_SYS_NS16550_REG_SIZE 1 270 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 271 272 #define CONFIG_SYS_BAUDRATE_TABLE \ 273 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 274 275 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 276 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 277 278 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 279 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 280 /* Use the HUSH parser */ 281 #define CONFIG_SYS_HUSH_PARSER 282 #ifdef CONFIG_SYS_HUSH_PARSER 283 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 284 #endif 285 286 /* pass open firmware flat tree */ 287 #define CONFIG_OF_LIBFDT 1 288 #define CONFIG_OF_BOARD_SETUP 1 289 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 290 291 /* I2C */ 292 #define CONFIG_HARD_I2C /* I2C with hardware support */ 293 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 294 #define CONFIG_FSL_I2C 295 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 296 #define CONFIG_SYS_I2C_SLAVE 0x7F 297 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 298 #define CONFIG_SYS_I2C_OFFSET 0x3000 299 300 /* 301 * Config on-board EEPROM 302 */ 303 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 304 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 305 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 306 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 307 308 /* 309 * General PCI 310 * Addresses are mapped 1-1. 311 */ 312 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 313 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 314 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 315 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 316 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 317 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 319 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 320 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ 321 322 #ifdef CONFIG_PCI 323 #define CONFIG_PCI_SKIP_HOST_BRIDGE 324 #define CONFIG_NET_MULTI 325 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 326 327 #undef CONFIG_EEPRO100 328 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 329 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 330 331 #endif /* CONFIG_PCI */ 332 333 334 #ifndef CONFIG_NET_MULTI 335 #define CONFIG_NET_MULTI 1 336 #endif 337 338 /* 339 * QE UEC ethernet configuration 340 */ 341 #define CONFIG_UEC_ETH 342 #define CONFIG_ETHPRIME "UEC0" 343 344 #define CONFIG_UEC_ETH1 /* ETH3 */ 345 346 #ifdef CONFIG_UEC_ETH1 347 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 348 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 349 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 350 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 351 #define CONFIG_SYS_UEC1_PHY_ADDR 4 352 #define CONFIG_SYS_UEC1_INTERFACE_TYPE MII 353 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 354 #endif 355 356 #define CONFIG_UEC_ETH2 /* ETH4 */ 357 358 #ifdef CONFIG_UEC_ETH2 359 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 360 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 361 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 362 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 363 #define CONFIG_SYS_UEC2_PHY_ADDR 0 364 #define CONFIG_SYS_UEC2_INTERFACE_TYPE MII 365 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 366 #endif 367 368 /* 369 * Environment 370 */ 371 #ifndef CONFIG_SYS_RAMBOOT 372 #define CONFIG_ENV_IS_IN_FLASH 1 373 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 374 #define CONFIG_ENV_SECT_SIZE 0x20000 375 #define CONFIG_ENV_SIZE 0x2000 376 #else 377 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 378 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 379 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 380 #define CONFIG_ENV_SIZE 0x2000 381 #endif 382 383 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 385 386 /* 387 * BOOTP options 388 */ 389 #define CONFIG_BOOTP_BOOTFILESIZE 390 #define CONFIG_BOOTP_BOOTPATH 391 #define CONFIG_BOOTP_GATEWAY 392 #define CONFIG_BOOTP_HOSTNAME 393 394 /* 395 * Command line configuration. 396 */ 397 #include <config_cmd_default.h> 398 399 #define CONFIG_CMD_PING 400 #define CONFIG_CMD_I2C 401 #define CONFIG_CMD_EEPROM 402 #define CONFIG_CMD_ASKENV 403 404 #if defined(CONFIG_PCI) 405 #define CONFIG_CMD_PCI 406 #endif 407 #if defined(CONFIG_SYS_RAMBOOT) 408 #undef CONFIG_CMD_SAVEENV 409 #undef CONFIG_CMD_LOADS 410 #endif 411 412 #undef CONFIG_WATCHDOG /* watchdog disabled */ 413 414 /* 415 * Miscellaneous configurable options 416 */ 417 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 418 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 419 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 420 421 #if (CONFIG_CMD_KGDB) 422 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 423 #else 424 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 425 #endif 426 427 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 428 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 429 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 430 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 431 432 /* 433 * For booting Linux, the board info and command line data 434 * have to be in the first 256 MB of memory, since this is 435 * the maximum mapped by the Linux kernel during initialization. 436 */ 437 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 438 439 /* 440 * Core HID Setup 441 */ 442 #define CONFIG_SYS_HID0_INIT 0x000000000 443 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 444 HID0_ENABLE_INSTRUCTION_CACHE) 445 #define CONFIG_SYS_HID2 HID2_HBE 446 447 /* 448 * MMU Setup 449 */ 450 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 451 452 /* DDR: cache cacheable */ 453 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 454 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 455 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 456 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 457 458 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 459 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 460 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 461 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 462 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 463 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 464 465 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 466 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 467 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 468 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 469 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 470 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 471 472 #define CONFIG_SYS_IBAT3L (0) 473 #define CONFIG_SYS_IBAT3U (0) 474 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 475 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 476 477 /* Stack in dcache: cacheable, no memory coherence */ 478 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 479 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 480 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 481 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 482 483 #ifdef CONFIG_PCI 484 /* PCI MEM space: cacheable */ 485 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 486 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 487 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 488 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 489 /* PCI MMIO space: cache-inhibit and guarded */ 490 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ 491 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 492 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 493 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 494 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 495 #else 496 #define CONFIG_SYS_IBAT5L (0) 497 #define CONFIG_SYS_IBAT5U (0) 498 #define CONFIG_SYS_IBAT6L (0) 499 #define CONFIG_SYS_IBAT6U (0) 500 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 501 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 502 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 503 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 504 #endif 505 506 /* Nothing in BAT7 */ 507 #define CONFIG_SYS_IBAT7L (0) 508 #define CONFIG_SYS_IBAT7U (0) 509 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 510 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 511 512 #if (CONFIG_CMD_KGDB) 513 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 514 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 515 #endif 516 517 /* 518 * Environment Configuration 519 */ 520 #define CONFIG_ENV_OVERWRITE 521 522 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 523 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 524 525 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ 526 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ 527 528 #define CONFIG_NETDEV eth1 529 530 #define CONFIG_HOSTNAME mpc8323erdb 531 #define CONFIG_ROOTPATH /nfsroot 532 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 533 #define CONFIG_BOOTFILE uImage 534 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 535 #define CONFIG_FDTFILE mpc832x_rdb.dtb 536 537 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 538 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 539 #define CONFIG_BAUDRATE 115200 540 541 #define XMK_STR(x) #x 542 #define MK_STR(x) XMK_STR(x) 543 544 #define CONFIG_EXTRA_ENV_SETTINGS \ 545 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 546 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 547 "tftpflash=tftp $loadaddr $uboot;" \ 548 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 549 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 550 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 551 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 552 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 553 "fdtaddr=780000\0" \ 554 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 555 "ramdiskaddr=1000000\0" \ 556 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 557 "console=ttyS0\0" \ 558 "setbootargs=setenv bootargs " \ 559 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 560 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 561 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 562 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 563 564 #define CONFIG_NFSBOOTCOMMAND \ 565 "setenv rootdev /dev/nfs;" \ 566 "run setbootargs;" \ 567 "run setipargs;" \ 568 "tftp $loadaddr $bootfile;" \ 569 "tftp $fdtaddr $fdtfile;" \ 570 "bootm $loadaddr - $fdtaddr" 571 572 #define CONFIG_RAMBOOTCOMMAND \ 573 "setenv rootdev /dev/ram;" \ 574 "run setbootargs;" \ 575 "tftp $ramdiskaddr $ramdiskfile;" \ 576 "tftp $loadaddr $bootfile;" \ 577 "tftp $fdtaddr $fdtfile;" \ 578 "bootm $loadaddr $ramdiskaddr $fdtaddr" 579 580 #undef MK_STR 581 #undef XMK_STR 582 583 #endif /* __CONFIG_H */ 584