1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #undef DEBUG 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 family */ 18 #define CONFIG_QE 1 /* Has QE */ 19 #define CONFIG_MPC83XX 1 /* MPC83xx family */ 20 #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ 21 22 #define CONFIG_PCI 1 23 #define CONFIG_83XX_GENERIC_PCI 1 24 25 /* 26 * System Clock Setup 27 */ 28 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 29 30 #ifndef CONFIG_SYS_CLK_FREQ 31 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 32 #endif 33 34 /* 35 * Hardware Reset Configuration Word 36 */ 37 #define CFG_HRCW_LOW (\ 38 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 39 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 40 HRCWL_VCO_1X2 |\ 41 HRCWL_CSB_TO_CLKIN_2X1 |\ 42 HRCWL_CORE_TO_CSB_2_5X1 |\ 43 HRCWL_CE_PLL_VCO_DIV_2 |\ 44 HRCWL_CE_PLL_DIV_1X1 |\ 45 HRCWL_CE_TO_PLL_1X3) 46 47 #define CFG_HRCW_HIGH (\ 48 HRCWH_PCI_HOST |\ 49 HRCWH_PCI1_ARBITER_ENABLE |\ 50 HRCWH_CORE_ENABLE |\ 51 HRCWH_FROM_0X00000100 |\ 52 HRCWH_BOOTSEQ_DISABLE |\ 53 HRCWH_SW_WATCHDOG_DISABLE |\ 54 HRCWH_ROM_LOC_LOCAL_16BIT |\ 55 HRCWH_BIG_ENDIAN |\ 56 HRCWH_LALE_NORMAL) 57 58 /* 59 * System IO Config 60 */ 61 #define CFG_SICRL 0x00000000 62 63 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 64 65 /* 66 * IMMR new address 67 */ 68 #define CFG_IMMR 0xE0000000 69 70 /* 71 * DDR Setup 72 */ 73 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 74 #define CFG_SDRAM_BASE CFG_DDR_BASE 75 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 76 #define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 77 78 #undef CONFIG_SPD_EEPROM 79 #if defined(CONFIG_SPD_EEPROM) 80 /* Determine DDR configuration from I2C interface 81 */ 82 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 83 #else 84 /* Manually set up DDR parameters 85 */ 86 #define CFG_DDR_SIZE 64 /* MB */ 87 #define CFG_DDR_CS0_CONFIG 0x80840101 88 #define CFG_DDR_TIMING_0 0x00220802 89 #define CFG_DDR_TIMING_1 0x3935d322 90 #define CFG_DDR_TIMING_2 0x0f9048ca 91 #define CFG_DDR_TIMING_3 0x00000000 92 #define CFG_DDR_CLK_CNTL 0x02000000 93 #define CFG_DDR_MODE 0x44400232 94 #define CFG_DDR_MODE2 0x8000c000 95 #define CFG_DDR_INTERVAL 0x03200064 96 #define CFG_DDR_CS0_BNDS 0x00000003 97 #define CFG_DDR_SDRAM_CFG 0x43080000 98 #define CFG_DDR_SDRAM_CFG2 0x00401000 99 #endif 100 101 /* 102 * Memory test 103 */ 104 #undef CFG_DRAM_TEST /* memory test, takes time */ 105 #define CFG_MEMTEST_START 0x00030000 /* memtest region */ 106 #define CFG_MEMTEST_END 0x03f00000 107 108 /* 109 * The reserved memory 110 */ 111 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 112 113 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 114 #define CFG_RAMBOOT 115 #else 116 #undef CFG_RAMBOOT 117 #endif 118 119 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 120 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 121 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 122 123 /* 124 * Initial RAM Base Address Setup 125 */ 126 #define CFG_INIT_RAM_LOCK 1 127 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 128 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 129 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 130 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 131 132 /* 133 * Local Bus Configuration & Clock Setup 134 */ 135 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) 136 #define CFG_LBC_LBCR 0x00000000 137 138 /* 139 * FLASH on the Local Bus 140 */ 141 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 142 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 143 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 144 #define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ 145 146 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 147 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 148 149 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ 150 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 151 BR_V) /* valid */ 152 #define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 153 154 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 155 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 156 157 #undef CFG_FLASH_CHECKSUM 158 159 /* 160 * SDRAM on the Local Bus 161 */ 162 #undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ 163 164 #ifdef CFG_LB_SDRAM 165 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 166 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 167 168 #define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE 169 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 170 171 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 172 /* 173 * Base Register 2 and Option Register 2 configure SDRAM. 174 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 175 * 176 * For BR2, need: 177 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 178 * port size = 32-bits = BR2[19:20] = 11 179 * no parity checking = BR2[21:22] = 00 180 * SDRAM for MSEL = BR2[24:26] = 011 181 * Valid = BR[31] = 1 182 * 183 * 0 4 8 12 16 20 24 28 184 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 185 * 186 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into 187 * the top 17 bits of BR2. 188 */ 189 190 #define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 191 192 /* 193 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 194 * 195 * For OR2, need: 196 * 64MB mask for AM, OR2[0:7] = 1111 1100 197 * XAM, OR2[17:18] = 11 198 * 9 columns OR2[19-21] = 010 199 * 13 rows OR2[23-25] = 100 200 * EAD set for extra time OR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 204 */ 205 206 #define CFG_OR2_PRELIM 0xfc006901 207 208 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 209 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 210 211 /* 212 * LSDMR masks 213 */ 214 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 215 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 216 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 217 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 218 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 219 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 220 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 221 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 222 223 #define CFG_LBC_LSDMR_COMMON 0x0063b723 224 225 /* 226 * SDRAM Controller configuration sequence. 227 */ 228 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 229 | CFG_LBC_LSDMR_OP_PCHALL) 230 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 231 | CFG_LBC_LSDMR_OP_ARFRSH) 232 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 233 | CFG_LBC_LSDMR_OP_ARFRSH) 234 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 235 | CFG_LBC_LSDMR_OP_MRW) 236 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 237 | CFG_LBC_LSDMR_OP_NORMAL) 238 239 #endif 240 241 /* 242 * Windows to access PIB via local bus 243 */ 244 #define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ 245 #define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 246 247 /* 248 * Serial Port 249 */ 250 #define CONFIG_CONS_INDEX 1 251 #undef CONFIG_SERIAL_SOFTWARE_FIFO 252 #define CFG_NS16550 253 #define CFG_NS16550_SERIAL 254 #define CFG_NS16550_REG_SIZE 1 255 #define CFG_NS16550_CLK get_bus_freq(0) 256 257 #define CFG_BAUDRATE_TABLE \ 258 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 259 260 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 261 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 262 263 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 264 /* Use the HUSH parser */ 265 #define CFG_HUSH_PARSER 266 #ifdef CFG_HUSH_PARSER 267 #define CFG_PROMPT_HUSH_PS2 "> " 268 #endif 269 270 /* pass open firmware flat tree */ 271 #define CONFIG_OF_LIBFDT 1 272 #define CONFIG_OF_BOARD_SETUP 1 273 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 274 275 /* I2C */ 276 #define CONFIG_HARD_I2C /* I2C with hardware support */ 277 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 278 #define CONFIG_FSL_I2C 279 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 280 #define CFG_I2C_SLAVE 0x7F 281 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 282 #define CFG_I2C_OFFSET 0x3000 283 284 /* 285 * Config on-board RTC 286 */ 287 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 288 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 289 290 /* 291 * General PCI 292 * Addresses are mapped 1-1. 293 */ 294 #define CFG_PCI1_MEM_BASE 0x80000000 295 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 296 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 297 #define CFG_PCI1_MMIO_BASE 0x90000000 298 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 299 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 300 #define CFG_PCI1_IO_BASE 0xd0000000 301 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 302 #define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */ 303 304 #ifdef CONFIG_PCI 305 306 #define CONFIG_NET_MULTI 307 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 308 309 #undef CONFIG_EEPRO100 310 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 311 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 312 313 #endif /* CONFIG_PCI */ 314 315 316 #ifndef CONFIG_NET_MULTI 317 #define CONFIG_NET_MULTI 1 318 #endif 319 320 /* 321 * QE UEC ethernet configuration 322 */ 323 #define CONFIG_UEC_ETH 324 #define CONFIG_ETHPRIME "Freescale GETH" 325 326 #define CONFIG_UEC_ETH1 /* ETH3 */ 327 328 #ifdef CONFIG_UEC_ETH1 329 #define CFG_UEC1_UCC_NUM 2 /* UCC3 */ 330 #define CFG_UEC1_RX_CLK QE_CLK9 331 #define CFG_UEC1_TX_CLK QE_CLK10 332 #define CFG_UEC1_ETH_TYPE FAST_ETH 333 #define CFG_UEC1_PHY_ADDR 4 334 #define CFG_UEC1_INTERFACE_MODE ENET_100_MII 335 #endif 336 337 #define CONFIG_UEC_ETH2 /* ETH4 */ 338 339 #ifdef CONFIG_UEC_ETH2 340 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 341 #define CFG_UEC2_RX_CLK QE_CLK16 342 #define CFG_UEC2_TX_CLK QE_CLK3 343 #define CFG_UEC2_ETH_TYPE FAST_ETH 344 #define CFG_UEC2_PHY_ADDR 0 345 #define CFG_UEC2_INTERFACE_MODE ENET_100_MII 346 #endif 347 348 /* 349 * Environment 350 */ 351 #ifndef CFG_RAMBOOT 352 #define CFG_ENV_IS_IN_FLASH 1 353 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 354 #define CFG_ENV_SECT_SIZE 0x20000 355 #define CFG_ENV_SIZE 0x2000 356 #else 357 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 358 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 359 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 360 #define CFG_ENV_SIZE 0x2000 361 #endif 362 363 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 364 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 365 366 /* 367 * BOOTP options 368 */ 369 #define CONFIG_BOOTP_BOOTFILESIZE 370 #define CONFIG_BOOTP_BOOTPATH 371 #define CONFIG_BOOTP_GATEWAY 372 #define CONFIG_BOOTP_HOSTNAME 373 374 /* 375 * Command line configuration. 376 */ 377 #include <config_cmd_default.h> 378 379 #define CONFIG_CMD_PING 380 #define CONFIG_CMD_I2C 381 #define CONFIG_CMD_ASKENV 382 383 #if defined(CONFIG_PCI) 384 #define CONFIG_CMD_PCI 385 #endif 386 #if defined(CFG_RAMBOOT) 387 #undef CONFIG_CMD_ENV 388 #undef CONFIG_CMD_LOADS 389 #endif 390 391 #undef CONFIG_WATCHDOG /* watchdog disabled */ 392 393 /* 394 * Miscellaneous configurable options 395 */ 396 #define CFG_LONGHELP /* undef to save memory */ 397 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 398 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 399 400 #if (CONFIG_CMD_KGDB) 401 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 402 #else 403 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 404 #endif 405 406 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 407 #define CFG_MAXARGS 16 /* max number of command args */ 408 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 409 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 410 411 /* 412 * For booting Linux, the board info and command line data 413 * have to be in the first 8 MB of memory, since this is 414 * the maximum mapped by the Linux kernel during initialization. 415 */ 416 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 417 418 /* 419 * Core HID Setup 420 */ 421 #define CFG_HID0_INIT 0x000000000 422 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 423 #define CFG_HID2 HID2_HBE 424 425 /* 426 * MMU Setup 427 */ 428 429 /* DDR: cache cacheable */ 430 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 431 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 432 #define CFG_DBAT0L CFG_IBAT0L 433 #define CFG_DBAT0U CFG_IBAT0U 434 435 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 436 #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ 437 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 438 #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 439 #define CFG_DBAT1L CFG_IBAT1L 440 #define CFG_DBAT1U CFG_IBAT1U 441 442 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 443 #define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 444 #define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 445 #define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ 446 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 447 #define CFG_DBAT2U CFG_IBAT2U 448 449 #define CFG_IBAT3L (0) 450 #define CFG_IBAT3U (0) 451 #define CFG_DBAT3L CFG_IBAT3L 452 #define CFG_DBAT3U CFG_IBAT3U 453 454 /* Stack in dcache: cacheable, no memory coherence */ 455 #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) 456 #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 457 #define CFG_DBAT4L CFG_IBAT4L 458 #define CFG_DBAT4U CFG_IBAT4U 459 460 #ifdef CONFIG_PCI 461 /* PCI MEM space: cacheable */ 462 #define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 463 #define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 464 #define CFG_DBAT5L CFG_IBAT5L 465 #define CFG_DBAT5U CFG_IBAT5U 466 /* PCI MMIO space: cache-inhibit and guarded */ 467 #define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ 468 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 469 #define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 470 #define CFG_DBAT6L CFG_IBAT6L 471 #define CFG_DBAT6U CFG_IBAT6U 472 #else 473 #define CFG_IBAT5L (0) 474 #define CFG_IBAT5U (0) 475 #define CFG_IBAT6L (0) 476 #define CFG_IBAT6U (0) 477 #define CFG_DBAT5L CFG_IBAT5L 478 #define CFG_DBAT5U CFG_IBAT5U 479 #define CFG_DBAT6L CFG_IBAT6L 480 #define CFG_DBAT6U CFG_IBAT6U 481 #endif 482 483 /* Nothing in BAT7 */ 484 #define CFG_IBAT7L (0) 485 #define CFG_IBAT7U (0) 486 #define CFG_DBAT7L CFG_IBAT7L 487 #define CFG_DBAT7U CFG_IBAT7U 488 489 /* 490 * Internal Definitions 491 * 492 * Boot Flags 493 */ 494 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 495 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 496 497 #if (CONFIG_CMD_KGDB) 498 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 499 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 500 #endif 501 502 /* 503 * Environment Configuration 504 */ 505 #define CONFIG_ENV_OVERWRITE 506 507 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 508 #define CONFIG_ETHADDR 00:04:9f:ef:03:01 509 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 510 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 511 512 #define CONFIG_IPADDR 10.0.0.2 513 #define CONFIG_SERVERIP 10.0.0.1 514 #define CONFIG_GATEWAYIP 10.0.0.1 515 #define CONFIG_NETMASK 255.0.0.0 516 #define CONFIG_NETDEV eth1 517 518 #define CONFIG_HOSTNAME mpc8323erdb 519 #define CONFIG_ROOTPATH /nfsroot 520 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 521 #define CONFIG_BOOTFILE uImage 522 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 523 #define CONFIG_FDTFILE mpc832x_rdb.dtb 524 525 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 526 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 527 #define CONFIG_BAUDRATE 115200 528 529 #define XMK_STR(x) #x 530 #define MK_STR(x) XMK_STR(x) 531 532 #define CONFIG_EXTRA_ENV_SETTINGS \ 533 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 534 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 535 "tftpflash=tftp $loadaddr $uboot;" \ 536 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 537 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 538 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 539 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 540 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 541 "fdtaddr=400000\0" \ 542 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 543 "ramdiskaddr=1000000\0" \ 544 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 545 "console=ttyS0\0" \ 546 "setbootargs=setenv bootargs " \ 547 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 548 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 549 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 550 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 551 552 #define CONFIG_NFSBOOTCOMMAND \ 553 "setenv rootdev /dev/nfs;" \ 554 "run setbootargs;" \ 555 "run setipargs;" \ 556 "tftp $loadaddr $bootfile;" \ 557 "tftp $fdtaddr $fdtfile;" \ 558 "bootm $loadaddr - $fdtaddr" 559 560 #define CONFIG_RAMBOOTCOMMAND \ 561 "setenv rootdev /dev/ram;" \ 562 "run setbootargs;" \ 563 "tftp $ramdiskaddr $ramdiskfile;" \ 564 "tftp $loadaddr $bootfile;" \ 565 "tftp $fdtaddr $fdtfile;" \ 566 "bootm $loadaddr $ramdiskaddr $fdtaddr" 567 568 #undef MK_STR 569 #undef XMK_STR 570 571 #endif /* __CONFIG_H */ 572