1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC83XX 1 /* MPC83xx family */ 18 #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ 19 20 #define CONFIG_PCI 1 21 #define CONFIG_83XX_GENERIC_PCI 1 22 23 /* 24 * System Clock Setup 25 */ 26 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 27 28 #ifndef CONFIG_SYS_CLK_FREQ 29 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 30 #endif 31 32 /* 33 * Hardware Reset Configuration Word 34 */ 35 #define CFG_HRCW_LOW (\ 36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 37 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 38 HRCWL_VCO_1X2 |\ 39 HRCWL_CSB_TO_CLKIN_2X1 |\ 40 HRCWL_CORE_TO_CSB_2_5X1 |\ 41 HRCWL_CE_PLL_VCO_DIV_2 |\ 42 HRCWL_CE_PLL_DIV_1X1 |\ 43 HRCWL_CE_TO_PLL_1X3) 44 45 #define CFG_HRCW_HIGH (\ 46 HRCWH_PCI_HOST |\ 47 HRCWH_PCI1_ARBITER_ENABLE |\ 48 HRCWH_CORE_ENABLE |\ 49 HRCWH_FROM_0X00000100 |\ 50 HRCWH_BOOTSEQ_DISABLE |\ 51 HRCWH_SW_WATCHDOG_DISABLE |\ 52 HRCWH_ROM_LOC_LOCAL_16BIT |\ 53 HRCWH_BIG_ENDIAN |\ 54 HRCWH_LALE_NORMAL) 55 56 /* 57 * System IO Config 58 */ 59 #define CFG_SICRL 0x00000000 60 61 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 62 63 /* 64 * IMMR new address 65 */ 66 #define CFG_IMMR 0xE0000000 67 68 /* 69 * System performance 70 */ 71 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 72 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 73 #define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 74 75 /* 76 * DDR Setup 77 */ 78 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 79 #define CFG_SDRAM_BASE CFG_DDR_BASE 80 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 81 #define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 82 83 #undef CONFIG_SPD_EEPROM 84 #if defined(CONFIG_SPD_EEPROM) 85 /* Determine DDR configuration from I2C interface 86 */ 87 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 88 #else 89 /* Manually set up DDR parameters 90 */ 91 #define CFG_DDR_SIZE 64 /* MB */ 92 #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ 93 | CSCONFIG_ODT_WR_ACS \ 94 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) 95 /* 0x80010101 */ 96 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 97 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 98 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 99 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 100 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 101 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 102 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 103 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 104 /* 0x00220802 */ 105 #define CFG_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ 106 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 107 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ 108 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 109 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ 110 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ 111 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 112 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 113 /* 0x26253222 */ 114 #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 115 | (31 << TIMING_CFG2_CPO_SHIFT ) \ 116 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 117 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 118 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 119 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 120 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 121 /* 0x1f9048c7 */ 122 #define CFG_DDR_TIMING_3 0x00000000 123 #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 124 /* 0x02000000 */ 125 #define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 126 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 127 /* 0x44480232 */ 128 #define CFG_DDR_MODE2 0x8000c000 129 #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 130 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 131 /* 0x03200064 */ 132 #define CFG_DDR_CS0_BNDS 0x00000003 133 #define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ 134 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 135 | SDRAM_CFG_32_BE ) 136 /* 0x43080000 */ 137 #define CFG_DDR_SDRAM_CFG2 0x00401000 138 #endif 139 140 /* 141 * Memory test 142 */ 143 #undef CFG_DRAM_TEST /* memory test, takes time */ 144 #define CFG_MEMTEST_START 0x00030000 /* memtest region */ 145 #define CFG_MEMTEST_END 0x03f00000 146 147 /* 148 * The reserved memory 149 */ 150 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 151 152 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 153 #define CFG_RAMBOOT 154 #else 155 #undef CFG_RAMBOOT 156 #endif 157 158 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 159 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 160 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 161 162 /* 163 * Initial RAM Base Address Setup 164 */ 165 #define CFG_INIT_RAM_LOCK 1 166 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 167 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 168 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 169 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 170 171 /* 172 * Local Bus Configuration & Clock Setup 173 */ 174 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) 175 #define CFG_LBC_LBCR 0x00000000 176 177 /* 178 * FLASH on the Local Bus 179 */ 180 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 181 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 182 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 183 #define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ 184 185 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 186 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 187 188 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ 189 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 190 BR_V) /* valid */ 191 #define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 192 193 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 194 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 195 196 #undef CFG_FLASH_CHECKSUM 197 198 /* 199 * SDRAM on the Local Bus 200 */ 201 #undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ 202 203 #ifdef CFG_LB_SDRAM 204 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 205 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 206 207 #define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE 208 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 209 210 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 211 /* 212 * Base Register 2 and Option Register 2 configure SDRAM. 213 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 214 * 215 * For BR2, need: 216 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 217 * port size = 32-bits = BR2[19:20] = 11 218 * no parity checking = BR2[21:22] = 00 219 * SDRAM for MSEL = BR2[24:26] = 011 220 * Valid = BR[31] = 1 221 * 222 * 0 4 8 12 16 20 24 28 223 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 224 * 225 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into 226 * the top 17 bits of BR2. 227 */ 228 229 #define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 230 231 /* 232 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 233 * 234 * For OR2, need: 235 * 64MB mask for AM, OR2[0:7] = 1111 1100 236 * XAM, OR2[17:18] = 11 237 * 9 columns OR2[19-21] = 010 238 * 13 rows OR2[23-25] = 100 239 * EAD set for extra time OR[31] = 1 240 * 241 * 0 4 8 12 16 20 24 28 242 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 243 */ 244 245 #define CFG_OR2_PRELIM 0xfc006901 246 247 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 248 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 249 250 /* 251 * LSDMR masks 252 */ 253 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 254 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 255 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 260 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 261 262 #define CFG_LBC_LSDMR_COMMON 0x0063b723 263 264 /* 265 * SDRAM Controller configuration sequence. 266 */ 267 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 268 | CFG_LBC_LSDMR_OP_PCHALL) 269 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 270 | CFG_LBC_LSDMR_OP_ARFRSH) 271 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 272 | CFG_LBC_LSDMR_OP_ARFRSH) 273 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 274 | CFG_LBC_LSDMR_OP_MRW) 275 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 276 | CFG_LBC_LSDMR_OP_NORMAL) 277 278 #endif 279 280 /* 281 * Windows to access PIB via local bus 282 */ 283 #define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ 284 #define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 285 286 /* 287 * Serial Port 288 */ 289 #define CONFIG_CONS_INDEX 1 290 #undef CONFIG_SERIAL_SOFTWARE_FIFO 291 #define CFG_NS16550 292 #define CFG_NS16550_SERIAL 293 #define CFG_NS16550_REG_SIZE 1 294 #define CFG_NS16550_CLK get_bus_freq(0) 295 296 #define CFG_BAUDRATE_TABLE \ 297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 298 299 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 300 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 301 302 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 303 /* Use the HUSH parser */ 304 #define CFG_HUSH_PARSER 305 #ifdef CFG_HUSH_PARSER 306 #define CFG_PROMPT_HUSH_PS2 "> " 307 #endif 308 309 /* pass open firmware flat tree */ 310 #define CONFIG_OF_LIBFDT 1 311 #define CONFIG_OF_BOARD_SETUP 1 312 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 313 314 /* I2C */ 315 #define CONFIG_HARD_I2C /* I2C with hardware support */ 316 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 317 #define CONFIG_FSL_I2C 318 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 319 #define CFG_I2C_SLAVE 0x7F 320 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 321 #define CFG_I2C_OFFSET 0x3000 322 323 /* 324 * Config on-board RTC 325 */ 326 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 327 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 328 329 /* 330 * General PCI 331 * Addresses are mapped 1-1. 332 */ 333 #define CFG_PCI1_MEM_BASE 0x80000000 334 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 335 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 336 #define CFG_PCI1_MMIO_BASE 0x90000000 337 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 338 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 339 #define CFG_PCI1_IO_BASE 0xd0000000 340 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 341 #define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */ 342 343 #ifdef CONFIG_PCI 344 345 #define CONFIG_NET_MULTI 346 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 347 348 #undef CONFIG_EEPRO100 349 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 350 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 351 352 #endif /* CONFIG_PCI */ 353 354 355 #ifndef CONFIG_NET_MULTI 356 #define CONFIG_NET_MULTI 1 357 #endif 358 359 /* 360 * QE UEC ethernet configuration 361 */ 362 #define CONFIG_UEC_ETH 363 #define CONFIG_ETHPRIME "FSL UEC0" 364 365 #define CONFIG_UEC_ETH1 /* ETH3 */ 366 367 #ifdef CONFIG_UEC_ETH1 368 #define CFG_UEC1_UCC_NUM 2 /* UCC3 */ 369 #define CFG_UEC1_RX_CLK QE_CLK9 370 #define CFG_UEC1_TX_CLK QE_CLK10 371 #define CFG_UEC1_ETH_TYPE FAST_ETH 372 #define CFG_UEC1_PHY_ADDR 4 373 #define CFG_UEC1_INTERFACE_MODE ENET_100_MII 374 #endif 375 376 #define CONFIG_UEC_ETH2 /* ETH4 */ 377 378 #ifdef CONFIG_UEC_ETH2 379 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 380 #define CFG_UEC2_RX_CLK QE_CLK16 381 #define CFG_UEC2_TX_CLK QE_CLK3 382 #define CFG_UEC2_ETH_TYPE FAST_ETH 383 #define CFG_UEC2_PHY_ADDR 0 384 #define CFG_UEC2_INTERFACE_MODE ENET_100_MII 385 #endif 386 387 /* 388 * Environment 389 */ 390 #ifndef CFG_RAMBOOT 391 #define CFG_ENV_IS_IN_FLASH 1 392 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 393 #define CFG_ENV_SECT_SIZE 0x20000 394 #define CFG_ENV_SIZE 0x2000 395 #else 396 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 397 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 398 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 399 #define CFG_ENV_SIZE 0x2000 400 #endif 401 402 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 403 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 404 405 /* 406 * BOOTP options 407 */ 408 #define CONFIG_BOOTP_BOOTFILESIZE 409 #define CONFIG_BOOTP_BOOTPATH 410 #define CONFIG_BOOTP_GATEWAY 411 #define CONFIG_BOOTP_HOSTNAME 412 413 /* 414 * Command line configuration. 415 */ 416 #include <config_cmd_default.h> 417 418 #define CONFIG_CMD_PING 419 #define CONFIG_CMD_I2C 420 #define CONFIG_CMD_ASKENV 421 422 #if defined(CONFIG_PCI) 423 #define CONFIG_CMD_PCI 424 #endif 425 #if defined(CFG_RAMBOOT) 426 #undef CONFIG_CMD_ENV 427 #undef CONFIG_CMD_LOADS 428 #endif 429 430 #undef CONFIG_WATCHDOG /* watchdog disabled */ 431 432 /* 433 * Miscellaneous configurable options 434 */ 435 #define CFG_LONGHELP /* undef to save memory */ 436 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 437 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 438 439 #if (CONFIG_CMD_KGDB) 440 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 441 #else 442 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 443 #endif 444 445 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 446 #define CFG_MAXARGS 16 /* max number of command args */ 447 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 448 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 449 450 /* 451 * For booting Linux, the board info and command line data 452 * have to be in the first 8 MB of memory, since this is 453 * the maximum mapped by the Linux kernel during initialization. 454 */ 455 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 456 457 /* 458 * Core HID Setup 459 */ 460 #define CFG_HID0_INIT 0x000000000 461 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 462 #define CFG_HID2 HID2_HBE 463 464 /* 465 * MMU Setup 466 */ 467 468 /* DDR: cache cacheable */ 469 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 470 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 471 #define CFG_DBAT0L CFG_IBAT0L 472 #define CFG_DBAT0U CFG_IBAT0U 473 474 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 475 #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ 476 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 477 #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 478 #define CFG_DBAT1L CFG_IBAT1L 479 #define CFG_DBAT1U CFG_IBAT1U 480 481 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 482 #define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 483 #define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 484 #define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ 485 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 486 #define CFG_DBAT2U CFG_IBAT2U 487 488 #define CFG_IBAT3L (0) 489 #define CFG_IBAT3U (0) 490 #define CFG_DBAT3L CFG_IBAT3L 491 #define CFG_DBAT3U CFG_IBAT3U 492 493 /* Stack in dcache: cacheable, no memory coherence */ 494 #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) 495 #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 496 #define CFG_DBAT4L CFG_IBAT4L 497 #define CFG_DBAT4U CFG_IBAT4U 498 499 #ifdef CONFIG_PCI 500 /* PCI MEM space: cacheable */ 501 #define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 502 #define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 503 #define CFG_DBAT5L CFG_IBAT5L 504 #define CFG_DBAT5U CFG_IBAT5U 505 /* PCI MMIO space: cache-inhibit and guarded */ 506 #define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ 507 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 508 #define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 509 #define CFG_DBAT6L CFG_IBAT6L 510 #define CFG_DBAT6U CFG_IBAT6U 511 #else 512 #define CFG_IBAT5L (0) 513 #define CFG_IBAT5U (0) 514 #define CFG_IBAT6L (0) 515 #define CFG_IBAT6U (0) 516 #define CFG_DBAT5L CFG_IBAT5L 517 #define CFG_DBAT5U CFG_IBAT5U 518 #define CFG_DBAT6L CFG_IBAT6L 519 #define CFG_DBAT6U CFG_IBAT6U 520 #endif 521 522 /* Nothing in BAT7 */ 523 #define CFG_IBAT7L (0) 524 #define CFG_IBAT7U (0) 525 #define CFG_DBAT7L CFG_IBAT7L 526 #define CFG_DBAT7U CFG_IBAT7U 527 528 /* 529 * Internal Definitions 530 * 531 * Boot Flags 532 */ 533 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 534 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 535 536 #if (CONFIG_CMD_KGDB) 537 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 538 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 539 #endif 540 541 /* 542 * Environment Configuration 543 */ 544 #define CONFIG_ENV_OVERWRITE 545 546 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 547 #define CONFIG_ETHADDR 00:04:9f:ef:03:01 548 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 549 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 550 551 #define CONFIG_IPADDR 10.0.0.2 552 #define CONFIG_SERVERIP 10.0.0.1 553 #define CONFIG_GATEWAYIP 10.0.0.1 554 #define CONFIG_NETMASK 255.0.0.0 555 #define CONFIG_NETDEV eth1 556 557 #define CONFIG_HOSTNAME mpc8323erdb 558 #define CONFIG_ROOTPATH /nfsroot 559 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 560 #define CONFIG_BOOTFILE uImage 561 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 562 #define CONFIG_FDTFILE mpc832x_rdb.dtb 563 564 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 565 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 566 #define CONFIG_BAUDRATE 115200 567 568 #define XMK_STR(x) #x 569 #define MK_STR(x) XMK_STR(x) 570 571 #define CONFIG_EXTRA_ENV_SETTINGS \ 572 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 573 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 574 "tftpflash=tftp $loadaddr $uboot;" \ 575 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 576 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 577 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 578 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 579 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 580 "fdtaddr=400000\0" \ 581 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 582 "ramdiskaddr=1000000\0" \ 583 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 584 "console=ttyS0\0" \ 585 "setbootargs=setenv bootargs " \ 586 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 587 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 588 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 589 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 590 591 #define CONFIG_NFSBOOTCOMMAND \ 592 "setenv rootdev /dev/nfs;" \ 593 "run setbootargs;" \ 594 "run setipargs;" \ 595 "tftp $loadaddr $bootfile;" \ 596 "tftp $fdtaddr $fdtfile;" \ 597 "bootm $loadaddr - $fdtaddr" 598 599 #define CONFIG_RAMBOOTCOMMAND \ 600 "setenv rootdev /dev/ram;" \ 601 "run setbootargs;" \ 602 "tftp $ramdiskaddr $ramdiskfile;" \ 603 "tftp $loadaddr $bootfile;" \ 604 "tftp $fdtaddr $fdtfile;" \ 605 "bootm $loadaddr $ramdiskaddr $fdtaddr" 606 607 #undef MK_STR 608 #undef XMK_STR 609 610 #endif /* __CONFIG_H */ 611