1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License version 2 as published
6  * by the Free Software Foundation.
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300		1	/* E300 family */
16 #define CONFIG_QE		1	/* Has QE */
17 #define CONFIG_MPC83XX		1	/* MPC83xx family */
18 #define CONFIG_MPC832X		1	/* MPC832x CPU specific */
19 
20 #define CONFIG_PCI		1
21 #define CONFIG_83XX_GENERIC_PCI	1
22 
23 /*
24  * System Clock Setup
25  */
26 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
27 
28 #ifndef CONFIG_SYS_CLK_FREQ
29 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
30 #endif
31 
32 /*
33  * Hardware Reset Configuration Word
34  */
35 #define CFG_HRCW_LOW (\
36 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
37 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
38 	HRCWL_VCO_1X2 |\
39 	HRCWL_CSB_TO_CLKIN_2X1 |\
40 	HRCWL_CORE_TO_CSB_2_5X1 |\
41 	HRCWL_CE_PLL_VCO_DIV_2 |\
42 	HRCWL_CE_PLL_DIV_1X1 |\
43 	HRCWL_CE_TO_PLL_1X3)
44 
45 #define CFG_HRCW_HIGH (\
46 	HRCWH_PCI_HOST |\
47 	HRCWH_PCI1_ARBITER_ENABLE |\
48 	HRCWH_CORE_ENABLE |\
49 	HRCWH_FROM_0X00000100 |\
50 	HRCWH_BOOTSEQ_DISABLE |\
51 	HRCWH_SW_WATCHDOG_DISABLE |\
52 	HRCWH_ROM_LOC_LOCAL_16BIT |\
53 	HRCWH_BIG_ENDIAN |\
54 	HRCWH_LALE_NORMAL)
55 
56 /*
57  * System IO Config
58  */
59 #define CFG_SICRL		0x00000000
60 
61 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
62 
63 /*
64  * IMMR new address
65  */
66 #define CFG_IMMR		0xE0000000
67 
68 /*
69  * System performance
70  */
71 #define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
72 #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
73 #define CFG_SPCR_OPT		1	/* (0-1) Optimize transactions between  CSB and the SEC and QUICC Engine block */
74 
75 /*
76  * DDR Setup
77  */
78 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
79 #define CFG_SDRAM_BASE		CFG_DDR_BASE
80 #define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
81 #define CFG_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
82 
83 #undef CONFIG_SPD_EEPROM
84 #if defined(CONFIG_SPD_EEPROM)
85 /* Determine DDR configuration from I2C interface
86  */
87 #define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
88 #else
89 /* Manually set up DDR parameters
90  */
91 #define CFG_DDR_SIZE		64	/* MB */
92 #define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
93 				| CSCONFIG_ODT_WR_ACS \
94 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
95 				/* 0x80010101 */
96 #define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
97 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
98 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
99 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
100 				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
101 				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
102 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
103 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
104 				/* 0x00220802 */
105 #define CFG_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
106 				| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
107 				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
108 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
109 				| ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
110 				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
111 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
112 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
113 				/* 0x26253222 */
114 #define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
115 				| (31 << TIMING_CFG2_CPO_SHIFT ) \
116 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
117 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
118 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
119 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
120 				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
121 				/* 0x1f9048c7 */
122 #define CFG_DDR_TIMING_3	0x00000000
123 #define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124 				/* 0x02000000 */
125 #define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
126 				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
127 				/* 0x44480232 */
128 #define CFG_DDR_MODE2		0x8000c000
129 #define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
130 				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
131 				/* 0x03200064 */
132 #define CFG_DDR_CS0_BNDS	0x00000003
133 #define CFG_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
134 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
135 				| SDRAM_CFG_32_BE )
136 				/* 0x43080000 */
137 #define CFG_DDR_SDRAM_CFG2	0x00401000
138 #endif
139 
140 /*
141  * Memory test
142  */
143 #undef CFG_DRAM_TEST		/* memory test, takes time */
144 #define CFG_MEMTEST_START	0x00030000	/* memtest region */
145 #define CFG_MEMTEST_END		0x03f00000
146 
147 /*
148  * The reserved memory
149  */
150 #define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
151 
152 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
153 #define CFG_RAMBOOT
154 #else
155 #undef  CFG_RAMBOOT
156 #endif
157 
158 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
159 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
160 #define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
161 
162 /*
163  * Initial RAM Base Address Setup
164  */
165 #define CFG_INIT_RAM_LOCK	1
166 #define CFG_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
167 #define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM */
168 #define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
169 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
170 
171 /*
172  * Local Bus Configuration & Clock Setup
173  */
174 #define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
175 #define CFG_LBC_LBCR		0x00000000
176 
177 /*
178  * FLASH on the Local Bus
179  */
180 #define CFG_FLASH_CFI		/* use the Common Flash Interface */
181 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
182 #define CFG_FLASH_BASE		0xFE000000	/* FLASH base address */
183 #define CFG_FLASH_SIZE		16	/* FLASH size is 16M */
184 
185 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
186 #define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
187 
188 #define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
189 			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
190 			BR_V)			/* valid */
191 #define CFG_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
192 
193 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
194 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
195 
196 #undef CFG_FLASH_CHECKSUM
197 
198 /*
199  * SDRAM on the Local Bus
200  */
201 #undef CFG_LB_SDRAM		/* The board has not SRDAM on local bus */
202 
203 #ifdef CFG_LB_SDRAM
204 #define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
205 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
206 
207 #define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
208 #define CFG_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
209 
210 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
211 /*
212  * Base Register 2 and Option Register 2 configure SDRAM.
213  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
214  *
215  * For BR2, need:
216  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
217  *    port size = 32-bits = BR2[19:20] = 11
218  *    no parity checking = BR2[21:22] = 00
219  *    SDRAM for MSEL = BR2[24:26] = 011
220  *    Valid = BR[31] = 1
221  *
222  * 0    4    8    12   16   20   24   28
223  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
224  *
225  * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
226  * the top 17 bits of BR2.
227  */
228 
229 #define CFG_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
230 
231 /*
232  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
233  *
234  * For OR2, need:
235  *    64MB mask for AM, OR2[0:7] = 1111 1100
236  *                 XAM, OR2[17:18] = 11
237  *    9 columns OR2[19-21] = 010
238  *    13 rows   OR2[23-25] = 100
239  *    EAD set for extra time OR[31] = 1
240  *
241  * 0    4    8    12   16   20   24   28
242  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
243  */
244 
245 #define CFG_OR2_PRELIM	0xfc006901
246 
247 #define CFG_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
248 #define CFG_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
249 
250 /*
251  * LSDMR masks
252  */
253 #define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
254 #define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
255 #define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
256 #define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
257 #define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
258 #define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
259 #define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
260 #define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
261 
262 #define CFG_LBC_LSDMR_COMMON	0x0063b723
263 
264 /*
265  * SDRAM Controller configuration sequence.
266  */
267 #define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
268 				| CFG_LBC_LSDMR_OP_PCHALL)
269 #define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
270 				| CFG_LBC_LSDMR_OP_ARFRSH)
271 #define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
272 				| CFG_LBC_LSDMR_OP_ARFRSH)
273 #define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
274 				| CFG_LBC_LSDMR_OP_MRW)
275 #define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
276 				| CFG_LBC_LSDMR_OP_NORMAL)
277 
278 #endif
279 
280 /*
281  * Windows to access PIB via local bus
282  */
283 #define CFG_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
284 #define CFG_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
285 
286 /*
287  * Serial Port
288  */
289 #define CONFIG_CONS_INDEX	1
290 #undef CONFIG_SERIAL_SOFTWARE_FIFO
291 #define CFG_NS16550
292 #define CFG_NS16550_SERIAL
293 #define CFG_NS16550_REG_SIZE	1
294 #define CFG_NS16550_CLK		get_bus_freq(0)
295 
296 #define CFG_BAUDRATE_TABLE  \
297 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
298 
299 #define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
300 #define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
301 
302 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
303 /* Use the HUSH parser */
304 #define CFG_HUSH_PARSER
305 #ifdef CFG_HUSH_PARSER
306 #define CFG_PROMPT_HUSH_PS2 "> "
307 #endif
308 
309 /* pass open firmware flat tree */
310 #define CONFIG_OF_LIBFDT	1
311 #define CONFIG_OF_BOARD_SETUP	1
312 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
313 
314 /* I2C */
315 #define CONFIG_HARD_I2C		/* I2C with hardware support */
316 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
317 #define CONFIG_FSL_I2C
318 #define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
319 #define CFG_I2C_SLAVE	0x7F
320 #define CFG_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
321 #define CFG_I2C_OFFSET	0x3000
322 
323 /*
324  * Config on-board EEPROM
325  */
326 #define CFG_I2C_EEPROM_ADDR		0x50
327 #define CFG_I2C_EEPROM_ADDR_LEN		2
328 #define CFG_EEPROM_PAGE_WRITE_BITS	6
329 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
330 #define CFG_EEPROM_PAGE_WRITE_ENABLE
331 
332 /*
333  * General PCI
334  * Addresses are mapped 1-1.
335  */
336 #define CFG_PCI1_MEM_BASE	0x80000000
337 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
338 #define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
339 #define CFG_PCI1_MMIO_BASE	0x90000000
340 #define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
341 #define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
342 #define CFG_PCI1_IO_BASE		0xd0000000
343 #define CFG_PCI1_IO_PHYS		CFG_PCI1_IO_BASE
344 #define CFG_PCI1_IO_SIZE		0x04000000	/* 64M */
345 
346 #ifdef CONFIG_PCI
347 #define CONFIG_PCI_SKIP_HOST_BRIDGE
348 #define CONFIG_NET_MULTI
349 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
350 
351 #undef CONFIG_EEPRO100
352 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
353 #define CFG_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
354 
355 #endif	/* CONFIG_PCI */
356 
357 
358 #ifndef CONFIG_NET_MULTI
359 #define CONFIG_NET_MULTI	1
360 #endif
361 
362 /*
363  * QE UEC ethernet configuration
364  */
365 #define CONFIG_UEC_ETH
366 #define CONFIG_ETHPRIME		"FSL UEC0"
367 
368 #define CONFIG_UEC_ETH1		/* ETH3 */
369 
370 #ifdef CONFIG_UEC_ETH1
371 #define CFG_UEC1_UCC_NUM	2	/* UCC3 */
372 #define CFG_UEC1_RX_CLK		QE_CLK9
373 #define CFG_UEC1_TX_CLK		QE_CLK10
374 #define CFG_UEC1_ETH_TYPE	FAST_ETH
375 #define CFG_UEC1_PHY_ADDR	4
376 #define CFG_UEC1_INTERFACE_MODE	ENET_100_MII
377 #endif
378 
379 #define CONFIG_UEC_ETH2		/* ETH4 */
380 
381 #ifdef CONFIG_UEC_ETH2
382 #define CFG_UEC2_UCC_NUM	1	/* UCC2 */
383 #define CFG_UEC2_RX_CLK		QE_CLK16
384 #define CFG_UEC2_TX_CLK		QE_CLK3
385 #define CFG_UEC2_ETH_TYPE	FAST_ETH
386 #define CFG_UEC2_PHY_ADDR	0
387 #define CFG_UEC2_INTERFACE_MODE	ENET_100_MII
388 #endif
389 
390 /*
391  * Environment
392  */
393 #ifndef CFG_RAMBOOT
394 	#define CFG_ENV_IS_IN_FLASH	1
395 	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
396 	#define CFG_ENV_SECT_SIZE	0x20000
397 	#define CFG_ENV_SIZE		0x2000
398 #else
399 	#define CFG_NO_FLASH		1	/* Flash is not usable now */
400 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
401 	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
402 	#define CFG_ENV_SIZE		0x2000
403 #endif
404 
405 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
406 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
407 
408 /*
409  * BOOTP options
410  */
411 #define CONFIG_BOOTP_BOOTFILESIZE
412 #define CONFIG_BOOTP_BOOTPATH
413 #define CONFIG_BOOTP_GATEWAY
414 #define CONFIG_BOOTP_HOSTNAME
415 
416 /*
417  * Command line configuration.
418  */
419 #include <config_cmd_default.h>
420 
421 #define CONFIG_CMD_PING
422 #define CONFIG_CMD_I2C
423 #define CONFIG_CMD_EEPROM
424 #define CONFIG_CMD_ASKENV
425 
426 #if defined(CONFIG_PCI)
427 	#define CONFIG_CMD_PCI
428 #endif
429 #if defined(CFG_RAMBOOT)
430 	#undef CONFIG_CMD_ENV
431 	#undef CONFIG_CMD_LOADS
432 #endif
433 
434 #undef CONFIG_WATCHDOG		/* watchdog disabled */
435 
436 /*
437  * Miscellaneous configurable options
438  */
439 #define CFG_LONGHELP		/* undef to save memory */
440 #define CFG_LOAD_ADDR		0x2000000	/* default load address */
441 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
442 
443 #if (CONFIG_CMD_KGDB)
444 	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
445 #else
446 	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
447 #endif
448 
449 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
450 #define CFG_MAXARGS	16		/* max number of command args */
451 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
452 #define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
453 
454 /*
455  * For booting Linux, the board info and command line data
456  * have to be in the first 8 MB of memory, since this is
457  * the maximum mapped by the Linux kernel during initialization.
458  */
459 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
460 
461 /*
462  * Core HID Setup
463  */
464 #define CFG_HID0_INIT		0x000000000
465 #define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
466 #define CFG_HID2		HID2_HBE
467 
468 /*
469  * MMU Setup
470  */
471 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
472 
473 /* DDR: cache cacheable */
474 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
475 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
476 #define CFG_DBAT0L	CFG_IBAT0L
477 #define CFG_DBAT0U	CFG_IBAT0U
478 
479 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
480 #define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
481 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
482 #define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
483 #define CFG_DBAT1L	CFG_IBAT1L
484 #define CFG_DBAT1U	CFG_IBAT1U
485 
486 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
487 #define CFG_IBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
488 #define CFG_IBAT2U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
489 #define CFG_DBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | \
490 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
491 #define CFG_DBAT2U	CFG_IBAT2U
492 
493 #define CFG_IBAT3L	(0)
494 #define CFG_IBAT3U	(0)
495 #define CFG_DBAT3L	CFG_IBAT3L
496 #define CFG_DBAT3U	CFG_IBAT3U
497 
498 /* Stack in dcache: cacheable, no memory coherence */
499 #define CFG_IBAT4L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
500 #define CFG_IBAT4U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
501 #define CFG_DBAT4L	CFG_IBAT4L
502 #define CFG_DBAT4U	CFG_IBAT4U
503 
504 #ifdef CONFIG_PCI
505 /* PCI MEM space: cacheable */
506 #define CFG_IBAT5L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
507 #define CFG_IBAT5U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
508 #define CFG_DBAT5L	CFG_IBAT5L
509 #define CFG_DBAT5U	CFG_IBAT5U
510 /* PCI MMIO space: cache-inhibit and guarded */
511 #define CFG_IBAT6L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
512 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
513 #define CFG_IBAT6U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
514 #define CFG_DBAT6L	CFG_IBAT6L
515 #define CFG_DBAT6U	CFG_IBAT6U
516 #else
517 #define CFG_IBAT5L	(0)
518 #define CFG_IBAT5U	(0)
519 #define CFG_IBAT6L	(0)
520 #define CFG_IBAT6U	(0)
521 #define CFG_DBAT5L	CFG_IBAT5L
522 #define CFG_DBAT5U	CFG_IBAT5U
523 #define CFG_DBAT6L	CFG_IBAT6L
524 #define CFG_DBAT6U	CFG_IBAT6U
525 #endif
526 
527 /* Nothing in BAT7 */
528 #define CFG_IBAT7L	(0)
529 #define CFG_IBAT7U	(0)
530 #define CFG_DBAT7L	CFG_IBAT7L
531 #define CFG_DBAT7U	CFG_IBAT7U
532 
533 /*
534  * Internal Definitions
535  *
536  * Boot Flags
537  */
538 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
539 #define BOOTFLAG_WARM	0x02	/* Software reboot */
540 
541 #if (CONFIG_CMD_KGDB)
542 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
543 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
544 #endif
545 
546 /*
547  * Environment Configuration
548  */
549 #define CONFIG_ENV_OVERWRITE
550 
551 #define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
552 #define CONFIG_ETHADDR	00:04:9f:ef:03:01
553 #define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
554 #define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
555 
556 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
557 #define CFG_I2C_MAC_OFFSET	0x7f00	/* MAC address offset in I2C EEPROM */
558 
559 #define CONFIG_IPADDR		10.0.0.2
560 #define CONFIG_SERVERIP		10.0.0.1
561 #define CONFIG_GATEWAYIP	10.0.0.1
562 #define CONFIG_NETMASK		255.0.0.0
563 #define CONFIG_NETDEV		eth1
564 
565 #define CONFIG_HOSTNAME		mpc8323erdb
566 #define CONFIG_ROOTPATH		/nfsroot
567 #define CONFIG_RAMDISKFILE	rootfs.ext2.gz.uboot
568 #define CONFIG_BOOTFILE		uImage
569 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
570 #define CONFIG_FDTFILE		mpc832x_rdb.dtb
571 
572 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
573 #define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
574 #define CONFIG_BAUDRATE		115200
575 
576 #define XMK_STR(x)	#x
577 #define MK_STR(x)	XMK_STR(x)
578 
579 #define CONFIG_EXTRA_ENV_SETTINGS \
580 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
581 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
582 	"tftpflash=tftp $loadaddr $uboot;"				\
583 		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
584 		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
585 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
586 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
587 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
588 	"fdtaddr=400000\0"						\
589 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
590 	"ramdiskaddr=1000000\0"						\
591 	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"			\
592 	"console=ttyS0\0"						\
593 	"setbootargs=setenv bootargs "					\
594 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
595 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
596 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
597 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
598 
599 #define CONFIG_NFSBOOTCOMMAND						\
600 	"setenv rootdev /dev/nfs;"					\
601 	"run setbootargs;"						\
602 	"run setipargs;"						\
603 	"tftp $loadaddr $bootfile;"					\
604 	"tftp $fdtaddr $fdtfile;"					\
605 	"bootm $loadaddr - $fdtaddr"
606 
607 #define CONFIG_RAMBOOTCOMMAND						\
608 	"setenv rootdev /dev/ram;"					\
609 	"run setbootargs;"						\
610 	"tftp $ramdiskaddr $ramdiskfile;"				\
611 	"tftp $loadaddr $bootfile;"					\
612 	"tftp $fdtaddr $fdtfile;"					\
613 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
614 
615 #undef MK_STR
616 #undef XMK_STR
617 
618 #endif	/* __CONFIG_H */
619