1 /* 2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 13 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 14 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 15 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 16 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 17 18 #ifdef CONFIG_NAND_U_BOOT 19 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 20 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 21 #ifdef CONFIG_NAND_SPL 22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 23 #endif /* CONFIG_NAND_SPL */ 24 #endif /* CONFIG_NAND_U_BOOT */ 25 26 #ifndef CONFIG_SYS_TEXT_BASE 27 #define CONFIG_SYS_TEXT_BASE 0xFE000000 28 #endif 29 30 #ifndef CONFIG_SYS_MONITOR_BASE 31 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 32 #endif 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 family */ 38 #define CONFIG_MPC831x 1 /* MPC831x CPU family */ 39 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ 40 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ 41 42 /* 43 * System Clock Setup 44 */ 45 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 46 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 47 48 /* 49 * Hardware Reset Configuration Word 50 * if CLKIN is 66.66MHz, then 51 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz 52 */ 53 #define CONFIG_SYS_HRCW_LOW (\ 54 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 56 HRCWL_SVCOD_DIV_2 |\ 57 HRCWL_CSB_TO_CLKIN_2X1 |\ 58 HRCWL_CORE_TO_CSB_3X1) 59 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 60 HRCWH_PCI_HOST |\ 61 HRCWH_PCI1_ARBITER_ENABLE |\ 62 HRCWH_CORE_ENABLE |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_TSEC1M_IN_RGMII |\ 66 HRCWH_TSEC2M_IN_RGMII |\ 67 HRCWH_BIG_ENDIAN |\ 68 HRCWH_LALE_NORMAL) 69 70 #ifdef CONFIG_NAND_SPL 71 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 72 HRCWH_FROM_0XFFF00100 |\ 73 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 74 HRCWH_RL_EXT_NAND) 75 #else 76 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 77 HRCWH_FROM_0X00000100 |\ 78 HRCWH_ROM_LOC_LOCAL_16BIT |\ 79 HRCWH_RL_EXT_LEGACY) 80 #endif 81 82 /* 83 * System IO Config 84 */ 85 #define CONFIG_SYS_SICRH 0x00000000 86 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ 87 88 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 89 #define CONFIG_HWCONFIG 90 91 /* 92 * IMMR new address 93 */ 94 #define CONFIG_SYS_IMMR 0xE0000000 95 96 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 97 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 98 #endif 99 100 /* 101 * Arbiter Setup 102 */ 103 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 104 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 105 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 106 107 /* 108 * DDR Setup 109 */ 110 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 112 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 113 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 114 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 115 | DDRCDR_PZ_LOZ \ 116 | DDRCDR_NZ_LOZ \ 117 | DDRCDR_ODT \ 118 | DDRCDR_Q_DRN) 119 /* 0x7b880001 */ 120 /* 121 * Manually set up DDR parameters 122 * consist of two chips HY5PS12621BFP-C4 from HYNIX 123 */ 124 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 125 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 126 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 127 | CSCONFIG_ODT_RD_NEVER \ 128 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 129 | CSCONFIG_ROW_BIT_13 \ 130 | CSCONFIG_COL_BIT_10) 131 /* 0x80010102 */ 132 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 133 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 134 | (0 << TIMING_CFG0_WRT_SHIFT) \ 135 | (0 << TIMING_CFG0_RRT_SHIFT) \ 136 | (0 << TIMING_CFG0_WWT_SHIFT) \ 137 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 138 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 139 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 140 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 141 /* 0x00220802 */ 142 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 143 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 144 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 145 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 146 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 147 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 148 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 149 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 150 /* 0x27256222 */ 151 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 152 | (4 << TIMING_CFG2_CPO_SHIFT) \ 153 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 154 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 155 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 156 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 157 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 158 /* 0x121048c5 */ 159 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 160 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 161 /* 0x03600100 */ 162 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 163 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 164 | SDRAM_CFG_DBW_32) 165 /* 0x43080000 */ 166 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 167 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 168 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 169 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 170 #define CONFIG_SYS_DDR_MODE2 0x00000000 171 172 /* 173 * Memory test 174 */ 175 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 176 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 177 #define CONFIG_SYS_MEMTEST_END 0x00140000 178 179 /* 180 * The reserved memory 181 */ 182 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 183 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 184 185 /* 186 * Initial RAM Base Address Setup 187 */ 188 #define CONFIG_SYS_INIT_RAM_LOCK 1 189 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 190 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 191 #define CONFIG_SYS_GBL_DATA_OFFSET \ 192 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 193 194 /* 195 * Local Bus Configuration & Clock Setup 196 */ 197 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 198 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 199 #define CONFIG_SYS_LBC_LBCR 0x00040000 200 #define CONFIG_FSL_ELBC 1 201 202 /* 203 * FLASH on the Local Bus 204 */ 205 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 206 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 207 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 208 209 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 210 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 211 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 212 213 /* Window base at flash base */ 214 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 215 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 216 217 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 218 | BR_PS_16 /* 16 bit port */ \ 219 | BR_MS_GPCM /* MSEL = GPCM */ \ 220 | BR_V) /* valid */ 221 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 222 | OR_UPM_XAM \ 223 | OR_GPCM_CSNT \ 224 | OR_GPCM_ACS_DIV2 \ 225 | OR_GPCM_XACS \ 226 | OR_GPCM_SCY_15 \ 227 | OR_GPCM_TRLX_SET \ 228 | OR_GPCM_EHTR_SET \ 229 | OR_GPCM_EAD) 230 231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 232 /* 127 64KB sectors and 8 8KB top sectors per device */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 135 234 235 #undef CONFIG_SYS_FLASH_CHECKSUM 236 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 237 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 238 239 /* 240 * NAND Flash on the Local Bus 241 */ 242 243 #ifdef CONFIG_NAND_SPL 244 #define CONFIG_SYS_NAND_BASE 0xFFF00000 245 #else 246 #define CONFIG_SYS_NAND_BASE 0xE0600000 247 #endif 248 249 #define CONFIG_MTD_DEVICE 250 #define CONFIG_MTD_PARTITION 251 #define CONFIG_CMD_MTDPARTS 252 #define MTDIDS_DEFAULT "nand0=e0600000.flash" 253 #define MTDPARTS_DEFAULT \ 254 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 255 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 258 #define CONFIG_CMD_NAND 1 259 #define CONFIG_NAND_FSL_ELBC 1 260 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 261 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 262 263 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 264 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 265 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 266 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 267 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 268 269 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 270 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 271 | BR_PS_8 /* 8 bit port */ \ 272 | BR_MS_FCM /* MSEL = FCM */ \ 273 | BR_V) /* valid */ 274 #define CONFIG_SYS_NAND_OR_PRELIM \ 275 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 276 | OR_FCM_CSCT \ 277 | OR_FCM_CST \ 278 | OR_FCM_CHT \ 279 | OR_FCM_SCY_1 \ 280 | OR_FCM_TRLX \ 281 | OR_FCM_EHTR) 282 /* 0xFFFF8396 */ 283 284 #ifdef CONFIG_NAND_U_BOOT 285 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 286 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 287 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 288 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 289 #else 290 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 291 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 292 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 293 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 294 #endif 295 296 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 297 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 298 299 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 300 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 301 302 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ 303 !defined(CONFIG_NAND_SPL) 304 #define CONFIG_SYS_RAMBOOT 305 #else 306 #undef CONFIG_SYS_RAMBOOT 307 #endif 308 309 /* 310 * Serial Port 311 */ 312 #define CONFIG_CONS_INDEX 1 313 #define CONFIG_SYS_NS16550 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 317 318 #define CONFIG_SYS_BAUDRATE_TABLE \ 319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 320 321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 323 324 /* Use the HUSH parser */ 325 #define CONFIG_SYS_HUSH_PARSER 326 327 /* Pass open firmware flat tree */ 328 #define CONFIG_OF_LIBFDT 1 329 #define CONFIG_OF_BOARD_SETUP 1 330 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 331 332 /* I2C */ 333 #define CONFIG_SYS_I2C 334 #define CONFIG_SYS_I2C_FSL 335 #define CONFIG_SYS_FSL_I2C_SPEED 400000 336 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 337 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 338 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 339 340 /* 341 * Board info - revision and where boot from 342 */ 343 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 344 345 /* 346 * Config on-board RTC 347 */ 348 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 349 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 350 351 /* 352 * General PCI 353 * Addresses are mapped 1-1. 354 */ 355 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 356 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 357 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 358 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 359 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 360 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 361 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 362 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 363 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 364 365 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 366 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 367 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 368 369 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 370 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 371 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 372 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 373 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 374 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 375 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 376 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 377 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 378 379 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 380 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 381 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 382 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 383 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 384 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 385 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 386 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 387 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 388 389 #define CONFIG_PCI 390 #define CONFIG_PCI_INDIRECT_BRIDGE 391 #define CONFIG_PCIE 392 393 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 394 395 #define CONFIG_EEPRO100 396 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 397 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 398 399 #define CONFIG_HAS_FSL_DR_USB 400 #define CONFIG_SYS_SCCR_USBDRCM 3 401 402 #define CONFIG_CMD_USB 403 #define CONFIG_USB_STORAGE 404 #define CONFIG_USB_EHCI 405 #define CONFIG_USB_EHCI_FSL 406 #define CONFIG_USB_PHY_TYPE "utmi" 407 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 408 409 /* 410 * TSEC 411 */ 412 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 413 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 414 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 415 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 416 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 417 418 /* 419 * TSEC ethernet configuration 420 */ 421 #define CONFIG_MII 1 /* MII PHY management */ 422 #define CONFIG_TSEC1 1 423 #define CONFIG_TSEC1_NAME "eTSEC0" 424 #define CONFIG_TSEC2 1 425 #define CONFIG_TSEC2_NAME "eTSEC1" 426 #define TSEC1_PHY_ADDR 0 427 #define TSEC2_PHY_ADDR 1 428 #define TSEC1_PHYIDX 0 429 #define TSEC2_PHYIDX 0 430 #define TSEC1_FLAGS TSEC_GIGABIT 431 #define TSEC2_FLAGS TSEC_GIGABIT 432 433 /* Options are: eTSEC[0-1] */ 434 #define CONFIG_ETHPRIME "eTSEC1" 435 436 /* 437 * SATA 438 */ 439 #define CONFIG_LIBATA 440 #define CONFIG_FSL_SATA 441 442 #define CONFIG_SYS_SATA_MAX_DEVICE 2 443 #define CONFIG_SATA1 444 #define CONFIG_SYS_SATA1_OFFSET 0x18000 445 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 446 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 447 #define CONFIG_SATA2 448 #define CONFIG_SYS_SATA2_OFFSET 0x19000 449 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 450 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 451 452 #ifdef CONFIG_FSL_SATA 453 #define CONFIG_LBA48 454 #define CONFIG_CMD_SATA 455 #define CONFIG_DOS_PARTITION 456 #define CONFIG_CMD_EXT2 457 #endif 458 459 /* 460 * Environment 461 */ 462 #if defined(CONFIG_NAND_U_BOOT) 463 #define CONFIG_ENV_IS_IN_NAND 1 464 #define CONFIG_ENV_OFFSET (512 * 1024) 465 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 466 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 467 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 468 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 469 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 470 CONFIG_ENV_RANGE) 471 #elif !defined(CONFIG_SYS_RAMBOOT) 472 #define CONFIG_ENV_IS_IN_FLASH 1 473 #define CONFIG_ENV_ADDR \ 474 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 475 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 476 #define CONFIG_ENV_SIZE 0x2000 477 #else 478 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 479 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 480 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 481 #define CONFIG_ENV_SIZE 0x2000 482 #endif 483 484 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 485 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 486 487 /* 488 * BOOTP options 489 */ 490 #define CONFIG_BOOTP_BOOTFILESIZE 491 #define CONFIG_BOOTP_BOOTPATH 492 #define CONFIG_BOOTP_GATEWAY 493 #define CONFIG_BOOTP_HOSTNAME 494 495 /* 496 * Command line configuration. 497 */ 498 #include <config_cmd_default.h> 499 500 #define CONFIG_CMD_PING 501 #define CONFIG_CMD_I2C 502 #define CONFIG_CMD_MII 503 #define CONFIG_CMD_DATE 504 #define CONFIG_CMD_PCI 505 506 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 507 #undef CONFIG_CMD_SAVEENV 508 #undef CONFIG_CMD_LOADS 509 #endif 510 511 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 512 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 513 514 #undef CONFIG_WATCHDOG /* watchdog disabled */ 515 516 /* 517 * Miscellaneous configurable options 518 */ 519 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 520 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 521 522 #if defined(CONFIG_CMD_KGDB) 523 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 524 #else 525 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 526 #endif 527 528 /* Print Buffer Size */ 529 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 530 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 531 /* Boot Argument Buffer Size */ 532 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 533 534 /* 535 * For booting Linux, the board info and command line data 536 * have to be in the first 256 MB of memory, since this is 537 * the maximum mapped by the Linux kernel during initialization. 538 */ 539 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 540 541 /* 542 * Core HID Setup 543 */ 544 #define CONFIG_SYS_HID0_INIT 0x000000000 545 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 546 HID0_ENABLE_INSTRUCTION_CACHE | \ 547 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 548 #define CONFIG_SYS_HID2 HID2_HBE 549 550 /* 551 * MMU Setup 552 */ 553 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 554 555 /* DDR: cache cacheable */ 556 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 557 | BATL_PP_RW \ 558 | BATL_MEMCOHERENCE) 559 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 560 | BATU_BL_128M \ 561 | BATU_VS \ 562 | BATU_VP) 563 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 564 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 565 566 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 567 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 568 | BATL_PP_RW \ 569 | BATL_CACHEINHIBIT \ 570 | BATL_GUARDEDSTORAGE) 571 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 572 | BATU_BL_8M \ 573 | BATU_VS \ 574 | BATU_VP) 575 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 576 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 577 578 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 579 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 580 | BATL_PP_RW \ 581 | BATL_MEMCOHERENCE) 582 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 583 | BATU_BL_32M \ 584 | BATU_VS \ 585 | BATU_VP) 586 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 587 | BATL_PP_RW \ 588 | BATL_CACHEINHIBIT \ 589 | BATL_GUARDEDSTORAGE) 590 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 591 592 /* Stack in dcache: cacheable, no memory coherence */ 593 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 594 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ 595 | BATU_BL_128K \ 596 | BATU_VS \ 597 | BATU_VP) 598 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 599 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 600 601 /* PCI MEM space: cacheable */ 602 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ 603 | BATL_PP_RW \ 604 | BATL_MEMCOHERENCE) 605 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ 606 | BATU_BL_256M \ 607 | BATU_VS \ 608 | BATU_VP) 609 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 610 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 611 612 /* PCI MMIO space: cache-inhibit and guarded */ 613 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ 614 | BATL_PP_RW \ 615 | BATL_CACHEINHIBIT \ 616 | BATL_GUARDEDSTORAGE) 617 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ 618 | BATU_BL_256M \ 619 | BATU_VS \ 620 | BATU_VP) 621 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 622 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 623 624 #define CONFIG_SYS_IBAT6L 0 625 #define CONFIG_SYS_IBAT6U 0 626 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 627 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 628 629 #define CONFIG_SYS_IBAT7L 0 630 #define CONFIG_SYS_IBAT7U 0 631 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 632 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 633 634 #if defined(CONFIG_CMD_KGDB) 635 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 636 #endif 637 638 /* 639 * Environment Configuration 640 */ 641 642 #define CONFIG_ENV_OVERWRITE 643 644 #if defined(CONFIG_TSEC_ENET) 645 #define CONFIG_HAS_ETH0 646 #define CONFIG_HAS_ETH1 647 #endif 648 649 #define CONFIG_BAUDRATE 115200 650 651 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 652 653 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 654 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 655 656 #define CONFIG_EXTRA_ENV_SETTINGS \ 657 "netdev=eth0\0" \ 658 "consoledev=ttyS0\0" \ 659 "ramdiskaddr=1000000\0" \ 660 "ramdiskfile=ramfs.83xx\0" \ 661 "fdtaddr=780000\0" \ 662 "fdtfile=mpc8315erdb.dtb\0" \ 663 "usb_phy_type=utmi\0" \ 664 "" 665 666 #define CONFIG_NFSBOOTCOMMAND \ 667 "setenv bootargs root=/dev/nfs rw " \ 668 "nfsroot=$serverip:$rootpath " \ 669 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 670 "$netdev:off " \ 671 "console=$consoledev,$baudrate $othbootargs;" \ 672 "tftp $loadaddr $bootfile;" \ 673 "tftp $fdtaddr $fdtfile;" \ 674 "bootm $loadaddr - $fdtaddr" 675 676 #define CONFIG_RAMBOOTCOMMAND \ 677 "setenv bootargs root=/dev/ram rw " \ 678 "console=$consoledev,$baudrate $othbootargs;" \ 679 "tftp $ramdiskaddr $ramdiskfile;" \ 680 "tftp $loadaddr $bootfile;" \ 681 "tftp $fdtaddr $fdtfile;" \ 682 "bootm $loadaddr $ramdiskaddr $fdtaddr" 683 684 685 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 686 687 #endif /* __CONFIG_H */ 688