1 /*
2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
13 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
14 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
15 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
16 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17 
18 #ifndef CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SYS_TEXT_BASE	0xFE000000
20 #endif
21 
22 #ifndef CONFIG_SYS_MONITOR_BASE
23 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
24 #endif
25 
26 /*
27  * High Level Configuration Options
28  */
29 #define CONFIG_E300		1 /* E300 family */
30 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
31 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
32 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
33 
34 /*
35  * System Clock Setup
36  */
37 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
38 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
39 
40 /*
41  * Hardware Reset Configuration Word
42  * if CLKIN is 66.66MHz, then
43  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
44  */
45 #define CONFIG_SYS_HRCW_LOW (\
46 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
47 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
48 	HRCWL_SVCOD_DIV_2 |\
49 	HRCWL_CSB_TO_CLKIN_2X1 |\
50 	HRCWL_CORE_TO_CSB_3X1)
51 #define CONFIG_SYS_HRCW_HIGH_BASE (\
52 	HRCWH_PCI_HOST |\
53 	HRCWH_PCI1_ARBITER_ENABLE |\
54 	HRCWH_CORE_ENABLE |\
55 	HRCWH_BOOTSEQ_DISABLE |\
56 	HRCWH_SW_WATCHDOG_DISABLE |\
57 	HRCWH_TSEC1M_IN_RGMII |\
58 	HRCWH_TSEC2M_IN_RGMII |\
59 	HRCWH_BIG_ENDIAN |\
60 	HRCWH_LALE_NORMAL)
61 
62 #ifdef CONFIG_NAND_SPL
63 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
64 		       HRCWH_FROM_0XFFF00100 |\
65 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
66 		       HRCWH_RL_EXT_NAND)
67 #else
68 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
69 		       HRCWH_FROM_0X00000100 |\
70 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
71 		       HRCWH_RL_EXT_LEGACY)
72 #endif
73 
74 /*
75  * System IO Config
76  */
77 #define CONFIG_SYS_SICRH		0x00000000
78 #define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
79 
80 #define CONFIG_HWCONFIG
81 
82 /*
83  * IMMR new address
84  */
85 #define CONFIG_SYS_IMMR		0xE0000000
86 
87 /*
88  * Arbiter Setup
89  */
90 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
91 #define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
92 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
93 
94 /*
95  * DDR Setup
96  */
97 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
98 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
99 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
100 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
101 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
102 				| DDRCDR_PZ_LOZ \
103 				| DDRCDR_NZ_LOZ \
104 				| DDRCDR_ODT \
105 				| DDRCDR_Q_DRN)
106 				/* 0x7b880001 */
107 /*
108  * Manually set up DDR parameters
109  * consist of two chips HY5PS12621BFP-C4 from HYNIX
110  */
111 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
112 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
113 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
114 				| CSCONFIG_ODT_RD_NEVER \
115 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
116 				| CSCONFIG_ROW_BIT_13 \
117 				| CSCONFIG_COL_BIT_10)
118 				/* 0x80010102 */
119 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
120 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
121 				| (0 << TIMING_CFG0_WRT_SHIFT) \
122 				| (0 << TIMING_CFG0_RRT_SHIFT) \
123 				| (0 << TIMING_CFG0_WWT_SHIFT) \
124 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
125 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
126 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
127 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
128 				/* 0x00220802 */
129 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
130 				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
131 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
132 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
133 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
134 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
135 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
136 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
137 				/* 0x27256222 */
138 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
139 				| (4 << TIMING_CFG2_CPO_SHIFT) \
140 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
141 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
142 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
143 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
144 				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
145 				/* 0x121048c5 */
146 #define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
147 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
148 				/* 0x03600100 */
149 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
150 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
151 				| SDRAM_CFG_DBW_32)
152 				/* 0x43080000 */
153 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
154 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
155 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
156 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
157 #define CONFIG_SYS_DDR_MODE2	0x00000000
158 
159 /*
160  * Memory test
161  */
162 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
163 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
164 #define CONFIG_SYS_MEMTEST_END		0x00140000
165 
166 /*
167  * The reserved memory
168  */
169 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
170 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
171 
172 /*
173  * Initial RAM Base Address Setup
174  */
175 #define CONFIG_SYS_INIT_RAM_LOCK	1
176 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
177 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
178 #define CONFIG_SYS_GBL_DATA_OFFSET	\
179 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180 
181 /*
182  * Local Bus Configuration & Clock Setup
183  */
184 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
185 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
186 #define CONFIG_SYS_LBC_LBCR		0x00040000
187 #define CONFIG_FSL_ELBC		1
188 
189 /*
190  * FLASH on the Local Bus
191  */
192 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
193 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
194 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
195 
196 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
197 #define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
198 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
199 
200 					/* Window base at flash base */
201 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
202 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
203 
204 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
205 					| BR_PS_16	/* 16 bit port */ \
206 					| BR_MS_GPCM	/* MSEL = GPCM */ \
207 					| BR_V)		/* valid */
208 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
209 					| OR_UPM_XAM \
210 					| OR_GPCM_CSNT \
211 					| OR_GPCM_ACS_DIV2 \
212 					| OR_GPCM_XACS \
213 					| OR_GPCM_SCY_15 \
214 					| OR_GPCM_TRLX_SET \
215 					| OR_GPCM_EHTR_SET \
216 					| OR_GPCM_EAD)
217 
218 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
219 /* 127 64KB sectors and 8 8KB top sectors per device */
220 #define CONFIG_SYS_MAX_FLASH_SECT	135
221 
222 #undef CONFIG_SYS_FLASH_CHECKSUM
223 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
225 
226 /*
227  * NAND Flash on the Local Bus
228  */
229 
230 #ifdef CONFIG_NAND_SPL
231 #define CONFIG_SYS_NAND_BASE		0xFFF00000
232 #else
233 #define CONFIG_SYS_NAND_BASE		0xE0600000
234 #endif
235 
236 #define CONFIG_MTD_DEVICE
237 #define CONFIG_MTD_PARTITION
238 #define MTDIDS_DEFAULT			"nand0=e0600000.flash"
239 #define MTDPARTS_DEFAULT		\
240 	"mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
241 
242 #define CONFIG_SYS_MAX_NAND_DEVICE	1
243 #define CONFIG_NAND_FSL_ELBC		1
244 #define CONFIG_SYS_NAND_BLOCK_SIZE	16384
245 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
246 
247 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
248 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
249 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
250 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
251 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
252 
253 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
254 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
255 				| BR_PS_8		/* 8 bit port */ \
256 				| BR_MS_FCM		/* MSEL = FCM */ \
257 				| BR_V)			/* valid */
258 #define CONFIG_SYS_NAND_OR_PRELIM	\
259 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
260 				| OR_FCM_CSCT \
261 				| OR_FCM_CST \
262 				| OR_FCM_CHT \
263 				| OR_FCM_SCY_1 \
264 				| OR_FCM_TRLX \
265 				| OR_FCM_EHTR)
266 				/* 0xFFFF8396 */
267 
268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
270 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
271 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
272 
273 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
274 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
275 
276 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
277 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
278 
279 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
280 	!defined(CONFIG_NAND_SPL)
281 #define CONFIG_SYS_RAMBOOT
282 #else
283 #undef CONFIG_SYS_RAMBOOT
284 #endif
285 
286 /*
287  * Serial Port
288  */
289 #define CONFIG_CONS_INDEX	1
290 #define CONFIG_SYS_NS16550_SERIAL
291 #define CONFIG_SYS_NS16550_REG_SIZE	1
292 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
293 
294 #define CONFIG_SYS_BAUDRATE_TABLE  \
295 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
296 
297 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
298 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
299 
300 /* I2C */
301 #define CONFIG_SYS_I2C
302 #define CONFIG_SYS_I2C_FSL
303 #define CONFIG_SYS_FSL_I2C_SPEED	400000
304 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
305 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
306 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
307 
308 /*
309  * Board info - revision and where boot from
310  */
311 #define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
312 
313 /*
314  * Config on-board RTC
315  */
316 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
317 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
318 
319 /*
320  * General PCI
321  * Addresses are mapped 1-1.
322  */
323 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
324 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
325 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
326 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
327 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
328 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
329 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
330 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
331 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
332 
333 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
334 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
335 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
336 
337 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
338 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
339 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
340 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
341 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
342 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
343 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
344 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
345 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
346 
347 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
348 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
349 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
350 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
351 #define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
352 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
353 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
354 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
355 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
356 
357 #define CONFIG_PCI_INDIRECT_BRIDGE
358 #define CONFIG_PCIE
359 
360 #define CONFIG_EEPRO100
361 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
362 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
363 
364 #define CONFIG_HAS_FSL_DR_USB
365 #define CONFIG_SYS_SCCR_USBDRCM		3
366 
367 #define CONFIG_USB_EHCI_FSL
368 #define CONFIG_USB_PHY_TYPE	"utmi"
369 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
370 
371 /*
372  * TSEC
373  */
374 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
375 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
376 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
377 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
378 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
379 
380 /*
381  * TSEC ethernet configuration
382  */
383 #define CONFIG_MII		1 /* MII PHY management */
384 #define CONFIG_TSEC1		1
385 #define CONFIG_TSEC1_NAME	"eTSEC0"
386 #define CONFIG_TSEC2		1
387 #define CONFIG_TSEC2_NAME	"eTSEC1"
388 #define TSEC1_PHY_ADDR		0
389 #define TSEC2_PHY_ADDR		1
390 #define TSEC1_PHYIDX		0
391 #define TSEC2_PHYIDX		0
392 #define TSEC1_FLAGS		TSEC_GIGABIT
393 #define TSEC2_FLAGS		TSEC_GIGABIT
394 
395 /* Options are: eTSEC[0-1] */
396 #define CONFIG_ETHPRIME		"eTSEC1"
397 
398 /*
399  * SATA
400  */
401 #define CONFIG_LIBATA
402 #define CONFIG_FSL_SATA
403 
404 #define CONFIG_SYS_SATA_MAX_DEVICE	2
405 #define CONFIG_SATA1
406 #define CONFIG_SYS_SATA1_OFFSET	0x18000
407 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
408 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
409 #define CONFIG_SATA2
410 #define CONFIG_SYS_SATA2_OFFSET	0x19000
411 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
412 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
413 
414 #ifdef CONFIG_FSL_SATA
415 #define CONFIG_LBA48
416 #endif
417 
418 /*
419  * Environment
420  */
421 #if !defined(CONFIG_SYS_RAMBOOT)
422 	#define CONFIG_ENV_ADDR		\
423 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
424 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
425 	#define CONFIG_ENV_SIZE		0x2000
426 #else
427 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
428 	#define CONFIG_ENV_SIZE		0x2000
429 #endif
430 
431 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
432 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
433 
434 /*
435  * BOOTP options
436  */
437 #define CONFIG_BOOTP_BOOTFILESIZE
438 #define CONFIG_BOOTP_BOOTPATH
439 #define CONFIG_BOOTP_GATEWAY
440 #define CONFIG_BOOTP_HOSTNAME
441 
442 /*
443  * Command line configuration.
444  */
445 
446 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
447 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
448 
449 #undef CONFIG_WATCHDOG		/* watchdog disabled */
450 
451 /*
452  * Miscellaneous configurable options
453  */
454 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
455 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
456 
457 /*
458  * For booting Linux, the board info and command line data
459  * have to be in the first 256 MB of memory, since this is
460  * the maximum mapped by the Linux kernel during initialization.
461  */
462 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
463 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
464 
465 /*
466  * Core HID Setup
467  */
468 #define CONFIG_SYS_HID0_INIT	0x000000000
469 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
470 				 HID0_ENABLE_INSTRUCTION_CACHE | \
471 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
472 #define CONFIG_SYS_HID2		HID2_HBE
473 
474 /*
475  * MMU Setup
476  */
477 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
478 
479 /* DDR: cache cacheable */
480 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
481 				| BATL_PP_RW \
482 				| BATL_MEMCOHERENCE)
483 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
484 				| BATU_BL_128M \
485 				| BATU_VS \
486 				| BATU_VP)
487 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
488 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
489 
490 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
491 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
492 				| BATL_PP_RW \
493 				| BATL_CACHEINHIBIT \
494 				| BATL_GUARDEDSTORAGE)
495 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
496 				| BATU_BL_8M \
497 				| BATU_VS \
498 				| BATU_VP)
499 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
500 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
501 
502 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
503 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
504 				| BATL_PP_RW \
505 				| BATL_MEMCOHERENCE)
506 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
507 				| BATU_BL_32M \
508 				| BATU_VS \
509 				| BATU_VP)
510 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
511 				| BATL_PP_RW \
512 				| BATL_CACHEINHIBIT \
513 				| BATL_GUARDEDSTORAGE)
514 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
515 
516 /* Stack in dcache: cacheable, no memory coherence */
517 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
518 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
519 				| BATU_BL_128K \
520 				| BATU_VS \
521 				| BATU_VP)
522 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
523 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
524 
525 /* PCI MEM space: cacheable */
526 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
527 				| BATL_PP_RW \
528 				| BATL_MEMCOHERENCE)
529 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
530 				| BATU_BL_256M \
531 				| BATU_VS \
532 				| BATU_VP)
533 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
534 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
535 
536 /* PCI MMIO space: cache-inhibit and guarded */
537 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
538 				| BATL_PP_RW \
539 				| BATL_CACHEINHIBIT \
540 				| BATL_GUARDEDSTORAGE)
541 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
542 				| BATU_BL_256M \
543 				| BATU_VS \
544 				| BATU_VP)
545 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
546 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
547 
548 #define CONFIG_SYS_IBAT6L	0
549 #define CONFIG_SYS_IBAT6U	0
550 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
551 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
552 
553 #define CONFIG_SYS_IBAT7L	0
554 #define CONFIG_SYS_IBAT7U	0
555 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
556 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
557 
558 #if defined(CONFIG_CMD_KGDB)
559 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
560 #endif
561 
562 /*
563  * Environment Configuration
564  */
565 
566 #define CONFIG_ENV_OVERWRITE
567 
568 #if defined(CONFIG_TSEC_ENET)
569 #define CONFIG_HAS_ETH0
570 #define CONFIG_HAS_ETH1
571 #endif
572 
573 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
574 
575 #define CONFIG_EXTRA_ENV_SETTINGS					\
576 	"netdev=eth0\0"							\
577 	"consoledev=ttyS0\0"						\
578 	"ramdiskaddr=1000000\0"						\
579 	"ramdiskfile=ramfs.83xx\0"					\
580 	"fdtaddr=780000\0"						\
581 	"fdtfile=mpc8315erdb.dtb\0"					\
582 	"usb_phy_type=utmi\0"						\
583 	""
584 
585 #define CONFIG_NFSBOOTCOMMAND						\
586 	"setenv bootargs root=/dev/nfs rw "				\
587 		"nfsroot=$serverip:$rootpath "				\
588 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
589 							"$netdev:off "	\
590 		"console=$consoledev,$baudrate $othbootargs;"		\
591 	"tftp $loadaddr $bootfile;"					\
592 	"tftp $fdtaddr $fdtfile;"					\
593 	"bootm $loadaddr - $fdtaddr"
594 
595 #define CONFIG_RAMBOOTCOMMAND						\
596 	"setenv bootargs root=/dev/ram rw "				\
597 		"console=$consoledev,$baudrate $othbootargs;"		\
598 	"tftp $ramdiskaddr $ramdiskfile;"				\
599 	"tftp $loadaddr $bootfile;"					\
600 	"tftp $fdtaddr $fdtfile;"					\
601 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
602 
603 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
604 
605 #endif	/* __CONFIG_H */
606