1 /* 2 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 #ifdef CONFIG_MK_NAND 29 #define CONFIG_NAND_U_BOOT 1 30 #define CONFIG_RAMBOOT_TEXT_BASE 0x00100000 31 #endif 32 33 /* 34 * High Level Configuration Options 35 */ 36 #define CONFIG_E300 1 /* E300 family */ 37 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 38 #define CONFIG_MPC831x 1 /* MPC831x CPU family */ 39 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ 40 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ 41 42 /* 43 * System Clock Setup 44 */ 45 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 46 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 47 48 /* 49 * Hardware Reset Configuration Word 50 * if CLKIN is 66.66MHz, then 51 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz 52 */ 53 #define CONFIG_SYS_HRCW_LOW (\ 54 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 56 HRCWL_SVCOD_DIV_2 |\ 57 HRCWL_CSB_TO_CLKIN_2X1 |\ 58 HRCWL_CORE_TO_CSB_3X1) 59 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 60 HRCWH_PCI_HOST |\ 61 HRCWH_PCI1_ARBITER_ENABLE |\ 62 HRCWH_CORE_ENABLE |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_TSEC1M_IN_RGMII |\ 66 HRCWH_TSEC2M_IN_RGMII |\ 67 HRCWH_BIG_ENDIAN |\ 68 HRCWH_LALE_NORMAL) 69 70 #ifdef CONFIG_NAND_SPL 71 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 72 HRCWH_FROM_0XFFF00100 |\ 73 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 74 HRCWH_RL_EXT_NAND) 75 #else 76 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 77 HRCWH_FROM_0X00000100 |\ 78 HRCWH_ROM_LOC_LOCAL_16BIT |\ 79 HRCWH_RL_EXT_LEGACY) 80 #endif 81 82 /* 83 * System IO Config 84 */ 85 #define CONFIG_SYS_SICRH 0x00000000 86 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ 87 88 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 89 #define CONFIG_HWCONFIG 90 91 /* 92 * IMMR new address 93 */ 94 #define CONFIG_SYS_IMMR 0xE0000000 95 96 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 97 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 98 #endif 99 100 /* 101 * Arbiter Setup 102 */ 103 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 104 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 105 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 106 107 /* 108 * DDR Setup 109 */ 110 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 112 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 113 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 114 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 115 | DDRCDR_PZ_LOZ \ 116 | DDRCDR_NZ_LOZ \ 117 | DDRCDR_ODT \ 118 | DDRCDR_Q_DRN ) 119 /* 0x7b880001 */ 120 /* 121 * Manually set up DDR parameters 122 * consist of two chips HY5PS12621BFP-C4 from HYNIX 123 */ 124 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 125 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 126 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ 127 | 0x00010000 /* ODT_WR to CSn */ \ 128 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 129 /* 0x80010102 */ 130 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 131 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 132 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 133 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 134 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 135 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 136 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 137 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 138 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 139 /* 0x00220802 */ 140 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ 141 | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 142 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ 143 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 144 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ 145 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ 146 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 147 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 148 /* 0x27256222 */ 149 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 150 | ( 4 << TIMING_CFG2_CPO_SHIFT ) \ 151 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 152 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 153 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 154 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 155 | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 156 /* 0x121048c5 */ 157 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 158 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 159 /* 0x03600100 */ 160 #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ 161 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 162 | SDRAM_CFG_32_BE ) 163 /* 0x43080000 */ 164 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 165 #define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ 166 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 167 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 168 #define CONFIG_SYS_DDR_MODE2 0x00000000 169 170 /* 171 * Memory test 172 */ 173 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 174 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 175 #define CONFIG_SYS_MEMTEST_END 0x00140000 176 177 /* 178 * The reserved memory 179 */ 180 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 181 182 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 183 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 184 185 /* 186 * Initial RAM Base Address Setup 187 */ 188 #define CONFIG_SYS_INIT_RAM_LOCK 1 189 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 190 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 191 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 192 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 193 194 /* 195 * Local Bus Configuration & Clock Setup 196 */ 197 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 198 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 199 #define CONFIG_SYS_LBC_LBCR 0x00040000 200 201 /* 202 * FLASH on the Local Bus 203 */ 204 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 205 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 206 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 207 208 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 209 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 210 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 211 212 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 213 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ 214 215 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 216 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ 217 | BR_V ) /* valid */ 218 #define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 219 | OR_UPM_XAM \ 220 | OR_GPCM_CSNT \ 221 | OR_GPCM_ACS_DIV2 \ 222 | OR_GPCM_XACS \ 223 | OR_GPCM_SCY_15 \ 224 | OR_GPCM_TRLX \ 225 | OR_GPCM_EHTR \ 226 | OR_GPCM_EAD ) 227 228 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 229 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */ 230 231 #undef CONFIG_SYS_FLASH_CHECKSUM 232 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 233 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 234 235 /* 236 * NAND Flash on the Local Bus 237 */ 238 239 #ifdef CONFIG_NAND_SPL 240 #define CONFIG_SYS_NAND_BASE 0xFFF00000 241 #else 242 #define CONFIG_SYS_NAND_BASE 0xE0600000 243 #endif 244 245 #define CONFIG_SYS_MAX_NAND_DEVICE 1 246 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 247 #define CONFIG_CMD_NAND 1 248 #define CONFIG_NAND_FSL_ELBC 1 249 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 250 251 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 252 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 253 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 254 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 255 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 256 257 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 258 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 259 | BR_PS_8 /* Port Size = 8 bit */ \ 260 | BR_MS_FCM /* MSEL = FCM */ \ 261 | BR_V ) /* valid */ 262 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ 263 | OR_FCM_CSCT \ 264 | OR_FCM_CST \ 265 | OR_FCM_CHT \ 266 | OR_FCM_SCY_1 \ 267 | OR_FCM_TRLX \ 268 | OR_FCM_EHTR ) 269 /* 0xFFFF8396 */ 270 271 #ifdef CONFIG_NAND_U_BOOT 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 274 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 275 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 276 #else 277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 279 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 280 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 281 #endif 282 283 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 284 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 285 286 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 287 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 288 289 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ 290 !defined(CONFIG_NAND_SPL) 291 #define CONFIG_SYS_RAMBOOT 292 #else 293 #undef CONFIG_SYS_RAMBOOT 294 #endif 295 296 /* 297 * Serial Port 298 */ 299 #define CONFIG_CONS_INDEX 1 300 #undef CONFIG_SERIAL_SOFTWARE_FIFO 301 #define CONFIG_SYS_NS16550 302 #define CONFIG_SYS_NS16550_SERIAL 303 #define CONFIG_SYS_NS16550_REG_SIZE 1 304 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 305 306 #define CONFIG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 308 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 311 312 /* Use the HUSH parser */ 313 #define CONFIG_SYS_HUSH_PARSER 314 #ifdef CONFIG_SYS_HUSH_PARSER 315 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 316 #endif 317 318 /* Pass open firmware flat tree */ 319 #define CONFIG_OF_LIBFDT 1 320 #define CONFIG_OF_BOARD_SETUP 1 321 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 322 323 /* I2C */ 324 #define CONFIG_HARD_I2C /* I2C with hardware support */ 325 #define CONFIG_FSL_I2C 326 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 327 #define CONFIG_SYS_I2C_SLAVE 0x7F 328 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 329 #define CONFIG_SYS_I2C_OFFSET 0x3000 330 #define CONFIG_SYS_I2C2_OFFSET 0x3100 331 332 /* 333 * Board info - revision and where boot from 334 */ 335 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 336 337 /* 338 * Config on-board RTC 339 */ 340 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 342 343 /* 344 * General PCI 345 * Addresses are mapped 1-1. 346 */ 347 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 348 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 349 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 350 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 351 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 352 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 353 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 354 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 355 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 356 357 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 358 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 359 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 360 361 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 362 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 363 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 364 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 365 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 366 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 367 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 368 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 369 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 370 371 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 372 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 373 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 374 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 375 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 376 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 377 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 378 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 379 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 380 381 #define CONFIG_PCI 382 #define CONFIG_PCIE 383 384 #define CONFIG_NET_MULTI 385 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 386 387 #define CONFIG_EEPRO100 388 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 389 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 390 391 #ifndef CONFIG_NET_MULTI 392 #define CONFIG_NET_MULTI 1 393 #endif 394 395 #define CONFIG_HAS_FSL_DR_USB 396 #define CONFIG_SYS_SCCR_USBDRCM 3 397 398 #define CONFIG_CMD_USB 399 #define CONFIG_USB_STORAGE 400 #define CONFIG_USB_EHCI 401 #define CONFIG_USB_EHCI_FSL 402 #define CONFIG_USB_PHY_TYPE "utmi" 403 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 404 405 /* 406 * TSEC 407 */ 408 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 409 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 410 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 411 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 412 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 413 414 /* 415 * TSEC ethernet configuration 416 */ 417 #define CONFIG_MII 1 /* MII PHY management */ 418 #define CONFIG_TSEC1 1 419 #define CONFIG_TSEC1_NAME "eTSEC0" 420 #define CONFIG_TSEC2 1 421 #define CONFIG_TSEC2_NAME "eTSEC1" 422 #define TSEC1_PHY_ADDR 0 423 #define TSEC2_PHY_ADDR 1 424 #define TSEC1_PHYIDX 0 425 #define TSEC2_PHYIDX 0 426 #define TSEC1_FLAGS TSEC_GIGABIT 427 #define TSEC2_FLAGS TSEC_GIGABIT 428 429 /* Options are: eTSEC[0-1] */ 430 #define CONFIG_ETHPRIME "eTSEC1" 431 432 /* 433 * SATA 434 */ 435 #define CONFIG_LIBATA 436 #define CONFIG_FSL_SATA 437 438 #define CONFIG_SYS_SATA_MAX_DEVICE 2 439 #define CONFIG_SATA1 440 #define CONFIG_SYS_SATA1_OFFSET 0x18000 441 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 442 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 443 #define CONFIG_SATA2 444 #define CONFIG_SYS_SATA2_OFFSET 0x19000 445 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 446 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 447 448 #ifdef CONFIG_FSL_SATA 449 #define CONFIG_LBA48 450 #define CONFIG_CMD_SATA 451 #define CONFIG_DOS_PARTITION 452 #define CONFIG_CMD_EXT2 453 #endif 454 455 /* 456 * Environment 457 */ 458 #if defined(CONFIG_NAND_U_BOOT) 459 #define CONFIG_ENV_IS_IN_NAND 1 460 #define CONFIG_ENV_OFFSET (512 * 1024) 461 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 462 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 463 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 464 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 465 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 466 CONFIG_ENV_RANGE) 467 #elif !defined(CONFIG_SYS_RAMBOOT) 468 #define CONFIG_ENV_IS_IN_FLASH 1 469 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 470 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 471 #define CONFIG_ENV_SIZE 0x2000 472 #else 473 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 474 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 475 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 476 #define CONFIG_ENV_SIZE 0x2000 477 #endif 478 479 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 480 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 481 482 /* 483 * BOOTP options 484 */ 485 #define CONFIG_BOOTP_BOOTFILESIZE 486 #define CONFIG_BOOTP_BOOTPATH 487 #define CONFIG_BOOTP_GATEWAY 488 #define CONFIG_BOOTP_HOSTNAME 489 490 /* 491 * Command line configuration. 492 */ 493 #include <config_cmd_default.h> 494 495 #define CONFIG_CMD_PING 496 #define CONFIG_CMD_I2C 497 #define CONFIG_CMD_MII 498 #define CONFIG_CMD_DATE 499 #define CONFIG_CMD_PCI 500 501 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 502 #undef CONFIG_CMD_SAVEENV 503 #undef CONFIG_CMD_LOADS 504 #endif 505 506 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 507 508 #undef CONFIG_WATCHDOG /* watchdog disabled */ 509 510 /* 511 * Miscellaneous configurable options 512 */ 513 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 514 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 515 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 516 517 #if defined(CONFIG_CMD_KGDB) 518 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 519 #else 520 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 521 #endif 522 523 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 524 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 525 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 526 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 527 528 /* 529 * For booting Linux, the board info and command line data 530 * have to be in the first 8 MB of memory, since this is 531 * the maximum mapped by the Linux kernel during initialization. 532 */ 533 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 534 535 /* 536 * Core HID Setup 537 */ 538 #define CONFIG_SYS_HID0_INIT 0x000000000 539 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 540 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 541 #define CONFIG_SYS_HID2 HID2_HBE 542 543 /* 544 * MMU Setup 545 */ 546 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 547 548 /* DDR: cache cacheable */ 549 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 550 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) 551 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 552 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 553 554 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 555 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 556 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 557 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 558 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 559 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 560 561 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 562 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 563 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ 564 BATU_VS | BATU_VP) 565 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 566 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 567 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 568 569 /* Stack in dcache: cacheable, no memory coherence */ 570 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 571 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 572 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 573 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 574 575 /* PCI MEM space: cacheable */ 576 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 577 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 578 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 579 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 580 581 /* PCI MMIO space: cache-inhibit and guarded */ 582 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ 583 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 584 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 585 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 586 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 587 588 #define CONFIG_SYS_IBAT6L 0 589 #define CONFIG_SYS_IBAT6U 0 590 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 591 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 592 593 #define CONFIG_SYS_IBAT7L 0 594 #define CONFIG_SYS_IBAT7U 0 595 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 596 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 597 598 /* 599 * Internal Definitions 600 * 601 * Boot Flags 602 */ 603 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 604 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 605 606 #if defined(CONFIG_CMD_KGDB) 607 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 608 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 609 #endif 610 611 /* 612 * Environment Configuration 613 */ 614 615 #define CONFIG_ENV_OVERWRITE 616 617 #if defined(CONFIG_TSEC_ENET) 618 #define CONFIG_HAS_ETH0 619 #define CONFIG_HAS_ETH1 620 #endif 621 622 #define CONFIG_BAUDRATE 115200 623 624 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 625 626 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 627 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 628 629 #define CONFIG_EXTRA_ENV_SETTINGS \ 630 "netdev=eth0\0" \ 631 "consoledev=ttyS0\0" \ 632 "ramdiskaddr=1000000\0" \ 633 "ramdiskfile=ramfs.83xx\0" \ 634 "fdtaddr=780000\0" \ 635 "fdtfile=mpc8315erdb.dtb\0" \ 636 "usb_phy_type=utmi\0" \ 637 "" 638 639 #define CONFIG_NFSBOOTCOMMAND \ 640 "setenv bootargs root=/dev/nfs rw " \ 641 "nfsroot=$serverip:$rootpath " \ 642 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 643 "console=$consoledev,$baudrate $othbootargs;" \ 644 "tftp $loadaddr $bootfile;" \ 645 "tftp $fdtaddr $fdtfile;" \ 646 "bootm $loadaddr - $fdtaddr" 647 648 #define CONFIG_RAMBOOTCOMMAND \ 649 "setenv bootargs root=/dev/ram rw " \ 650 "console=$consoledev,$baudrate $othbootargs;" \ 651 "tftp $ramdiskaddr $ramdiskfile;" \ 652 "tftp $loadaddr $bootfile;" \ 653 "tftp $fdtaddr $fdtfile;" \ 654 "bootm $loadaddr $ramdiskaddr $fdtaddr" 655 656 657 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 658 659 #endif /* __CONFIG_H */ 660