1 /* 2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 15 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 16 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 17 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 18 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 19 20 #ifndef CONFIG_SYS_TEXT_BASE 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 #endif 23 24 #ifndef CONFIG_SYS_MONITOR_BASE 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 26 #endif 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_E300 1 /* E300 family */ 32 #define CONFIG_MPC831x 1 /* MPC831x CPU family */ 33 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ 34 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ 35 36 /* 37 * System Clock Setup 38 */ 39 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 40 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 41 42 /* 43 * Hardware Reset Configuration Word 44 * if CLKIN is 66.66MHz, then 45 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz 46 */ 47 #define CONFIG_SYS_HRCW_LOW (\ 48 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 50 HRCWL_SVCOD_DIV_2 |\ 51 HRCWL_CSB_TO_CLKIN_2X1 |\ 52 HRCWL_CORE_TO_CSB_3X1) 53 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 54 HRCWH_PCI_HOST |\ 55 HRCWH_PCI1_ARBITER_ENABLE |\ 56 HRCWH_CORE_ENABLE |\ 57 HRCWH_BOOTSEQ_DISABLE |\ 58 HRCWH_SW_WATCHDOG_DISABLE |\ 59 HRCWH_TSEC1M_IN_RGMII |\ 60 HRCWH_TSEC2M_IN_RGMII |\ 61 HRCWH_BIG_ENDIAN |\ 62 HRCWH_LALE_NORMAL) 63 64 #ifdef CONFIG_NAND_SPL 65 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 66 HRCWH_FROM_0XFFF00100 |\ 67 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 68 HRCWH_RL_EXT_NAND) 69 #else 70 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 71 HRCWH_FROM_0X00000100 |\ 72 HRCWH_ROM_LOC_LOCAL_16BIT |\ 73 HRCWH_RL_EXT_LEGACY) 74 #endif 75 76 /* 77 * System IO Config 78 */ 79 #define CONFIG_SYS_SICRH 0x00000000 80 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ 81 82 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 83 #define CONFIG_HWCONFIG 84 85 /* 86 * IMMR new address 87 */ 88 #define CONFIG_SYS_IMMR 0xE0000000 89 90 /* 91 * Arbiter Setup 92 */ 93 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 94 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 95 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 96 97 /* 98 * DDR Setup 99 */ 100 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 102 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 103 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 104 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 105 | DDRCDR_PZ_LOZ \ 106 | DDRCDR_NZ_LOZ \ 107 | DDRCDR_ODT \ 108 | DDRCDR_Q_DRN) 109 /* 0x7b880001 */ 110 /* 111 * Manually set up DDR parameters 112 * consist of two chips HY5PS12621BFP-C4 from HYNIX 113 */ 114 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 115 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 116 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 117 | CSCONFIG_ODT_RD_NEVER \ 118 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 119 | CSCONFIG_ROW_BIT_13 \ 120 | CSCONFIG_COL_BIT_10) 121 /* 0x80010102 */ 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 123 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 124 | (0 << TIMING_CFG0_WRT_SHIFT) \ 125 | (0 << TIMING_CFG0_RRT_SHIFT) \ 126 | (0 << TIMING_CFG0_WWT_SHIFT) \ 127 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 128 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 129 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 130 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 131 /* 0x00220802 */ 132 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 133 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 134 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 135 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 136 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 137 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 138 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 139 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 140 /* 0x27256222 */ 141 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 142 | (4 << TIMING_CFG2_CPO_SHIFT) \ 143 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 144 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 145 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 146 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 147 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 148 /* 0x121048c5 */ 149 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 150 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 151 /* 0x03600100 */ 152 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 153 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 154 | SDRAM_CFG_DBW_32) 155 /* 0x43080000 */ 156 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 157 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 158 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 159 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 160 #define CONFIG_SYS_DDR_MODE2 0x00000000 161 162 /* 163 * Memory test 164 */ 165 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 166 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 167 #define CONFIG_SYS_MEMTEST_END 0x00140000 168 169 /* 170 * The reserved memory 171 */ 172 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 173 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 174 175 /* 176 * Initial RAM Base Address Setup 177 */ 178 #define CONFIG_SYS_INIT_RAM_LOCK 1 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 180 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 181 #define CONFIG_SYS_GBL_DATA_OFFSET \ 182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 183 184 /* 185 * Local Bus Configuration & Clock Setup 186 */ 187 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 188 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 189 #define CONFIG_SYS_LBC_LBCR 0x00040000 190 #define CONFIG_FSL_ELBC 1 191 192 /* 193 * FLASH on the Local Bus 194 */ 195 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 196 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 197 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 198 199 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 200 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 201 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 202 203 /* Window base at flash base */ 204 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 205 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 206 207 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 208 | BR_PS_16 /* 16 bit port */ \ 209 | BR_MS_GPCM /* MSEL = GPCM */ \ 210 | BR_V) /* valid */ 211 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 212 | OR_UPM_XAM \ 213 | OR_GPCM_CSNT \ 214 | OR_GPCM_ACS_DIV2 \ 215 | OR_GPCM_XACS \ 216 | OR_GPCM_SCY_15 \ 217 | OR_GPCM_TRLX_SET \ 218 | OR_GPCM_EHTR_SET \ 219 | OR_GPCM_EAD) 220 221 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 222 /* 127 64KB sectors and 8 8KB top sectors per device */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 135 224 225 #undef CONFIG_SYS_FLASH_CHECKSUM 226 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 227 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 228 229 /* 230 * NAND Flash on the Local Bus 231 */ 232 233 #ifdef CONFIG_NAND_SPL 234 #define CONFIG_SYS_NAND_BASE 0xFFF00000 235 #else 236 #define CONFIG_SYS_NAND_BASE 0xE0600000 237 #endif 238 239 #define CONFIG_MTD_DEVICE 240 #define CONFIG_MTD_PARTITION 241 #define CONFIG_CMD_MTDPARTS 242 #define MTDIDS_DEFAULT "nand0=e0600000.flash" 243 #define MTDPARTS_DEFAULT \ 244 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 245 246 #define CONFIG_SYS_MAX_NAND_DEVICE 1 247 #define CONFIG_CMD_NAND 1 248 #define CONFIG_NAND_FSL_ELBC 1 249 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 250 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 251 252 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 253 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 254 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 255 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 256 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 257 258 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 259 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 260 | BR_PS_8 /* 8 bit port */ \ 261 | BR_MS_FCM /* MSEL = FCM */ \ 262 | BR_V) /* valid */ 263 #define CONFIG_SYS_NAND_OR_PRELIM \ 264 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 265 | OR_FCM_CSCT \ 266 | OR_FCM_CST \ 267 | OR_FCM_CHT \ 268 | OR_FCM_SCY_1 \ 269 | OR_FCM_TRLX \ 270 | OR_FCM_EHTR) 271 /* 0xFFFF8396 */ 272 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 277 278 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 279 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 280 281 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 282 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 283 284 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ 285 !defined(CONFIG_NAND_SPL) 286 #define CONFIG_SYS_RAMBOOT 287 #else 288 #undef CONFIG_SYS_RAMBOOT 289 #endif 290 291 /* 292 * Serial Port 293 */ 294 #define CONFIG_CONS_INDEX 1 295 #define CONFIG_SYS_NS16550_SERIAL 296 #define CONFIG_SYS_NS16550_REG_SIZE 1 297 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 298 299 #define CONFIG_SYS_BAUDRATE_TABLE \ 300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 301 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 304 305 /* Use the HUSH parser */ 306 #define CONFIG_SYS_HUSH_PARSER 307 308 /* I2C */ 309 #define CONFIG_SYS_I2C 310 #define CONFIG_SYS_I2C_FSL 311 #define CONFIG_SYS_FSL_I2C_SPEED 400000 312 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 313 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 314 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 315 316 /* 317 * Board info - revision and where boot from 318 */ 319 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 320 321 /* 322 * Config on-board RTC 323 */ 324 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 325 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 326 327 /* 328 * General PCI 329 * Addresses are mapped 1-1. 330 */ 331 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 332 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 333 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 334 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 335 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 336 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 337 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 338 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 339 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 340 341 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 342 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 343 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 344 345 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 346 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 347 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 348 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 349 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 350 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 351 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 352 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 353 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 354 355 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 356 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 357 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 358 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 359 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 360 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 361 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 362 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 363 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 364 365 #define CONFIG_PCI 366 #define CONFIG_PCI_INDIRECT_BRIDGE 367 #define CONFIG_PCIE 368 369 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 370 371 #define CONFIG_EEPRO100 372 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 373 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 374 375 #define CONFIG_HAS_FSL_DR_USB 376 #define CONFIG_SYS_SCCR_USBDRCM 3 377 378 #define CONFIG_CMD_USB 379 #define CONFIG_USB_STORAGE 380 #define CONFIG_USB_EHCI 381 #define CONFIG_USB_EHCI_FSL 382 #define CONFIG_USB_PHY_TYPE "utmi" 383 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 384 385 /* 386 * TSEC 387 */ 388 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 389 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 390 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 391 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 392 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 393 394 /* 395 * TSEC ethernet configuration 396 */ 397 #define CONFIG_MII 1 /* MII PHY management */ 398 #define CONFIG_TSEC1 1 399 #define CONFIG_TSEC1_NAME "eTSEC0" 400 #define CONFIG_TSEC2 1 401 #define CONFIG_TSEC2_NAME "eTSEC1" 402 #define TSEC1_PHY_ADDR 0 403 #define TSEC2_PHY_ADDR 1 404 #define TSEC1_PHYIDX 0 405 #define TSEC2_PHYIDX 0 406 #define TSEC1_FLAGS TSEC_GIGABIT 407 #define TSEC2_FLAGS TSEC_GIGABIT 408 409 /* Options are: eTSEC[0-1] */ 410 #define CONFIG_ETHPRIME "eTSEC1" 411 412 /* 413 * SATA 414 */ 415 #define CONFIG_LIBATA 416 #define CONFIG_FSL_SATA 417 418 #define CONFIG_SYS_SATA_MAX_DEVICE 2 419 #define CONFIG_SATA1 420 #define CONFIG_SYS_SATA1_OFFSET 0x18000 421 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 422 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 423 #define CONFIG_SATA2 424 #define CONFIG_SYS_SATA2_OFFSET 0x19000 425 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 426 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 427 428 #ifdef CONFIG_FSL_SATA 429 #define CONFIG_LBA48 430 #define CONFIG_CMD_SATA 431 #define CONFIG_DOS_PARTITION 432 #define CONFIG_CMD_EXT2 433 #endif 434 435 /* 436 * Environment 437 */ 438 #if !defined(CONFIG_SYS_RAMBOOT) 439 #define CONFIG_ENV_IS_IN_FLASH 1 440 #define CONFIG_ENV_ADDR \ 441 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 442 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 443 #define CONFIG_ENV_SIZE 0x2000 444 #else 445 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 446 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 448 #define CONFIG_ENV_SIZE 0x2000 449 #endif 450 451 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 452 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 453 454 /* 455 * BOOTP options 456 */ 457 #define CONFIG_BOOTP_BOOTFILESIZE 458 #define CONFIG_BOOTP_BOOTPATH 459 #define CONFIG_BOOTP_GATEWAY 460 #define CONFIG_BOOTP_HOSTNAME 461 462 /* 463 * Command line configuration. 464 */ 465 #define CONFIG_CMD_PING 466 #define CONFIG_CMD_I2C 467 #define CONFIG_CMD_MII 468 #define CONFIG_CMD_DATE 469 #define CONFIG_CMD_PCI 470 471 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 472 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 473 474 #undef CONFIG_WATCHDOG /* watchdog disabled */ 475 476 /* 477 * Miscellaneous configurable options 478 */ 479 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 480 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 481 482 #if defined(CONFIG_CMD_KGDB) 483 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 484 #else 485 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 486 #endif 487 488 /* Print Buffer Size */ 489 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 490 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 491 /* Boot Argument Buffer Size */ 492 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 493 494 /* 495 * For booting Linux, the board info and command line data 496 * have to be in the first 256 MB of memory, since this is 497 * the maximum mapped by the Linux kernel during initialization. 498 */ 499 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 500 501 /* 502 * Core HID Setup 503 */ 504 #define CONFIG_SYS_HID0_INIT 0x000000000 505 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 506 HID0_ENABLE_INSTRUCTION_CACHE | \ 507 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 508 #define CONFIG_SYS_HID2 HID2_HBE 509 510 /* 511 * MMU Setup 512 */ 513 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 514 515 /* DDR: cache cacheable */ 516 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 517 | BATL_PP_RW \ 518 | BATL_MEMCOHERENCE) 519 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 520 | BATU_BL_128M \ 521 | BATU_VS \ 522 | BATU_VP) 523 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 524 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 525 526 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 527 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 528 | BATL_PP_RW \ 529 | BATL_CACHEINHIBIT \ 530 | BATL_GUARDEDSTORAGE) 531 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 532 | BATU_BL_8M \ 533 | BATU_VS \ 534 | BATU_VP) 535 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 536 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 537 538 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 539 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 540 | BATL_PP_RW \ 541 | BATL_MEMCOHERENCE) 542 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 543 | BATU_BL_32M \ 544 | BATU_VS \ 545 | BATU_VP) 546 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 547 | BATL_PP_RW \ 548 | BATL_CACHEINHIBIT \ 549 | BATL_GUARDEDSTORAGE) 550 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 551 552 /* Stack in dcache: cacheable, no memory coherence */ 553 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 554 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ 555 | BATU_BL_128K \ 556 | BATU_VS \ 557 | BATU_VP) 558 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 559 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 560 561 /* PCI MEM space: cacheable */ 562 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ 563 | BATL_PP_RW \ 564 | BATL_MEMCOHERENCE) 565 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ 566 | BATU_BL_256M \ 567 | BATU_VS \ 568 | BATU_VP) 569 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 570 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 571 572 /* PCI MMIO space: cache-inhibit and guarded */ 573 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ 574 | BATL_PP_RW \ 575 | BATL_CACHEINHIBIT \ 576 | BATL_GUARDEDSTORAGE) 577 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ 578 | BATU_BL_256M \ 579 | BATU_VS \ 580 | BATU_VP) 581 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 582 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 583 584 #define CONFIG_SYS_IBAT6L 0 585 #define CONFIG_SYS_IBAT6U 0 586 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 587 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 588 589 #define CONFIG_SYS_IBAT7L 0 590 #define CONFIG_SYS_IBAT7U 0 591 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 592 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 593 594 #if defined(CONFIG_CMD_KGDB) 595 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 596 #endif 597 598 /* 599 * Environment Configuration 600 */ 601 602 #define CONFIG_ENV_OVERWRITE 603 604 #if defined(CONFIG_TSEC_ENET) 605 #define CONFIG_HAS_ETH0 606 #define CONFIG_HAS_ETH1 607 #endif 608 609 #define CONFIG_BAUDRATE 115200 610 611 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 612 613 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 614 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 615 616 #define CONFIG_EXTRA_ENV_SETTINGS \ 617 "netdev=eth0\0" \ 618 "consoledev=ttyS0\0" \ 619 "ramdiskaddr=1000000\0" \ 620 "ramdiskfile=ramfs.83xx\0" \ 621 "fdtaddr=780000\0" \ 622 "fdtfile=mpc8315erdb.dtb\0" \ 623 "usb_phy_type=utmi\0" \ 624 "" 625 626 #define CONFIG_NFSBOOTCOMMAND \ 627 "setenv bootargs root=/dev/nfs rw " \ 628 "nfsroot=$serverip:$rootpath " \ 629 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 630 "$netdev:off " \ 631 "console=$consoledev,$baudrate $othbootargs;" \ 632 "tftp $loadaddr $bootfile;" \ 633 "tftp $fdtaddr $fdtfile;" \ 634 "bootm $loadaddr - $fdtaddr" 635 636 #define CONFIG_RAMBOOTCOMMAND \ 637 "setenv bootargs root=/dev/ram rw " \ 638 "console=$consoledev,$baudrate $othbootargs;" \ 639 "tftp $ramdiskaddr $ramdiskfile;" \ 640 "tftp $loadaddr $bootfile;" \ 641 "tftp $fdtaddr $fdtfile;" \ 642 "bootm $loadaddr $ramdiskaddr $fdtaddr" 643 644 645 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 646 647 #endif /* __CONFIG_H */ 648