1 /*
2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #ifndef __CONFIG_H
26 #define __CONFIG_H
27 
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
32 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
33 
34 #ifdef CONFIG_NAND_U_BOOT
35 #define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
36 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
37 #ifdef CONFIG_NAND_SPL
38 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
39 #endif /* CONFIG_NAND_SPL */
40 #endif /* CONFIG_NAND_U_BOOT */
41 
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE	0xFE000000
44 #endif
45 
46 #ifndef CONFIG_SYS_MONITOR_BASE
47 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
48 #endif
49 
50 /*
51  * High Level Configuration Options
52  */
53 #define CONFIG_E300		1 /* E300 family */
54 #define CONFIG_MPC83xx		1 /* MPC83xx family */
55 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
56 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
57 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
58 
59 /*
60  * System Clock Setup
61  */
62 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
63 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
64 
65 /*
66  * Hardware Reset Configuration Word
67  * if CLKIN is 66.66MHz, then
68  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
69  */
70 #define CONFIG_SYS_HRCW_LOW (\
71 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
72 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
73 	HRCWL_SVCOD_DIV_2 |\
74 	HRCWL_CSB_TO_CLKIN_2X1 |\
75 	HRCWL_CORE_TO_CSB_3X1)
76 #define CONFIG_SYS_HRCW_HIGH_BASE (\
77 	HRCWH_PCI_HOST |\
78 	HRCWH_PCI1_ARBITER_ENABLE |\
79 	HRCWH_CORE_ENABLE |\
80 	HRCWH_BOOTSEQ_DISABLE |\
81 	HRCWH_SW_WATCHDOG_DISABLE |\
82 	HRCWH_TSEC1M_IN_RGMII |\
83 	HRCWH_TSEC2M_IN_RGMII |\
84 	HRCWH_BIG_ENDIAN |\
85 	HRCWH_LALE_NORMAL)
86 
87 #ifdef CONFIG_NAND_SPL
88 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
89 		       HRCWH_FROM_0XFFF00100 |\
90 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
91 		       HRCWH_RL_EXT_NAND)
92 #else
93 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
94 		       HRCWH_FROM_0X00000100 |\
95 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
96 		       HRCWH_RL_EXT_LEGACY)
97 #endif
98 
99 /*
100  * System IO Config
101  */
102 #define CONFIG_SYS_SICRH		0x00000000
103 #define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
104 
105 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
106 #define CONFIG_HWCONFIG
107 
108 /*
109  * IMMR new address
110  */
111 #define CONFIG_SYS_IMMR		0xE0000000
112 
113 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
114 #define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
115 #endif
116 
117 /*
118  * Arbiter Setup
119  */
120 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
121 #define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
122 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
123 
124 /*
125  * DDR Setup
126  */
127 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
128 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
129 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
130 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
131 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
132 				| DDRCDR_PZ_LOZ \
133 				| DDRCDR_NZ_LOZ \
134 				| DDRCDR_ODT \
135 				| DDRCDR_Q_DRN)
136 				/* 0x7b880001 */
137 /*
138  * Manually set up DDR parameters
139  * consist of two chips HY5PS12621BFP-C4 from HYNIX
140  */
141 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
142 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
143 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
144 				| CSCONFIG_ODT_RD_NEVER \
145 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
146 				| CSCONFIG_ROW_BIT_13 \
147 				| CSCONFIG_COL_BIT_10)
148 				/* 0x80010102 */
149 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
150 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
151 				| (0 << TIMING_CFG0_WRT_SHIFT) \
152 				| (0 << TIMING_CFG0_RRT_SHIFT) \
153 				| (0 << TIMING_CFG0_WWT_SHIFT) \
154 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
155 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
156 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
157 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
158 				/* 0x00220802 */
159 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
160 				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
161 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
162 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
163 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
164 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
165 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
166 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
167 				/* 0x27256222 */
168 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
169 				| (4 << TIMING_CFG2_CPO_SHIFT) \
170 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
171 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
172 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
173 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
174 				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
175 				/* 0x121048c5 */
176 #define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
177 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
178 				/* 0x03600100 */
179 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
180 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
181 				| SDRAM_CFG_DBW_32)
182 				/* 0x43080000 */
183 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
184 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
185 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
186 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
187 #define CONFIG_SYS_DDR_MODE2	0x00000000
188 
189 /*
190  * Memory test
191  */
192 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
193 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
194 #define CONFIG_SYS_MEMTEST_END		0x00140000
195 
196 /*
197  * The reserved memory
198  */
199 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
200 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
201 
202 /*
203  * Initial RAM Base Address Setup
204  */
205 #define CONFIG_SYS_INIT_RAM_LOCK	1
206 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
207 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
208 #define CONFIG_SYS_GBL_DATA_OFFSET	\
209 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
210 
211 /*
212  * Local Bus Configuration & Clock Setup
213  */
214 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
215 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
216 #define CONFIG_SYS_LBC_LBCR		0x00040000
217 #define CONFIG_FSL_ELBC		1
218 
219 /*
220  * FLASH on the Local Bus
221  */
222 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
223 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
224 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
225 
226 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
227 #define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
228 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
229 
230 					/* Window base at flash base */
231 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
233 
234 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
235 					| BR_PS_16	/* 16 bit port */ \
236 					| BR_MS_GPCM	/* MSEL = GPCM */ \
237 					| BR_V)		/* valid */
238 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
239 					| OR_UPM_XAM \
240 					| OR_GPCM_CSNT \
241 					| OR_GPCM_ACS_DIV2 \
242 					| OR_GPCM_XACS \
243 					| OR_GPCM_SCY_15 \
244 					| OR_GPCM_TRLX_SET \
245 					| OR_GPCM_EHTR_SET \
246 					| OR_GPCM_EAD)
247 
248 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
249 /* 127 64KB sectors and 8 8KB top sectors per device */
250 #define CONFIG_SYS_MAX_FLASH_SECT	135
251 
252 #undef CONFIG_SYS_FLASH_CHECKSUM
253 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
254 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
255 
256 /*
257  * NAND Flash on the Local Bus
258  */
259 
260 #ifdef CONFIG_NAND_SPL
261 #define CONFIG_SYS_NAND_BASE		0xFFF00000
262 #else
263 #define CONFIG_SYS_NAND_BASE		0xE0600000
264 #endif
265 
266 #define CONFIG_MTD_DEVICE
267 #define CONFIG_MTD_PARTITION
268 #define CONFIG_CMD_MTDPARTS
269 #define MTDIDS_DEFAULT			"nand0=e0600000.flash"
270 #define MTDPARTS_DEFAULT		\
271 	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
272 
273 #define CONFIG_SYS_MAX_NAND_DEVICE	1
274 #define CONFIG_MTD_NAND_VERIFY_WRITE	1
275 #define CONFIG_CMD_NAND			1
276 #define CONFIG_NAND_FSL_ELBC		1
277 #define CONFIG_SYS_NAND_BLOCK_SIZE	16384
278 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
279 
280 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
281 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
282 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
283 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
284 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
285 
286 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
287 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
288 				| BR_PS_8		/* 8 bit port */ \
289 				| BR_MS_FCM		/* MSEL = FCM */ \
290 				| BR_V)			/* valid */
291 #define CONFIG_SYS_NAND_OR_PRELIM	\
292 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
293 				| OR_FCM_CSCT \
294 				| OR_FCM_CST \
295 				| OR_FCM_CHT \
296 				| OR_FCM_SCY_1 \
297 				| OR_FCM_TRLX \
298 				| OR_FCM_EHTR)
299 				/* 0xFFFF8396 */
300 
301 #ifdef CONFIG_NAND_U_BOOT
302 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
303 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
304 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
305 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
306 #else
307 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
308 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
309 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
310 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
311 #endif
312 
313 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
314 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
315 
316 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
317 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
318 
319 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
320 	!defined(CONFIG_NAND_SPL)
321 #define CONFIG_SYS_RAMBOOT
322 #else
323 #undef CONFIG_SYS_RAMBOOT
324 #endif
325 
326 /*
327  * Serial Port
328  */
329 #define CONFIG_CONS_INDEX	1
330 #define CONFIG_SYS_NS16550
331 #define CONFIG_SYS_NS16550_SERIAL
332 #define CONFIG_SYS_NS16550_REG_SIZE	1
333 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
334 
335 #define CONFIG_SYS_BAUDRATE_TABLE  \
336 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
337 
338 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
339 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
340 
341 /* Use the HUSH parser */
342 #define CONFIG_SYS_HUSH_PARSER
343 
344 /* Pass open firmware flat tree */
345 #define CONFIG_OF_LIBFDT	1
346 #define CONFIG_OF_BOARD_SETUP	1
347 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
348 
349 /* I2C */
350 #define CONFIG_HARD_I2C		/* I2C with hardware support */
351 #define CONFIG_FSL_I2C
352 #define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave addr */
353 #define CONFIG_SYS_I2C_SLAVE		0x7F
354 #define CONFIG_SYS_I2C_NOPROBES		{0x51} /* Don't probe these addrs */
355 #define CONFIG_SYS_I2C_OFFSET		0x3000
356 #define CONFIG_SYS_I2C2_OFFSET		0x3100
357 
358 /*
359  * Board info - revision and where boot from
360  */
361 #define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
362 
363 /*
364  * Config on-board RTC
365  */
366 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
367 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
368 
369 /*
370  * General PCI
371  * Addresses are mapped 1-1.
372  */
373 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
374 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
375 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
376 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
377 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
378 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
379 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
380 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
381 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
382 
383 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
384 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
385 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
386 
387 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
388 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
389 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
390 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
391 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
392 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
393 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
394 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
395 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
396 
397 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
398 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
399 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
400 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
401 #define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
402 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
403 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
404 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
405 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
406 
407 #define CONFIG_PCI
408 #define CONFIG_PCIE
409 
410 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
411 
412 #define CONFIG_EEPRO100
413 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
414 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
415 
416 #define CONFIG_HAS_FSL_DR_USB
417 #define CONFIG_SYS_SCCR_USBDRCM		3
418 
419 #define CONFIG_CMD_USB
420 #define CONFIG_USB_STORAGE
421 #define CONFIG_USB_EHCI
422 #define CONFIG_USB_EHCI_FSL
423 #define CONFIG_USB_PHY_TYPE	"utmi"
424 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
425 
426 /*
427  * TSEC
428  */
429 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
430 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
431 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
432 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
433 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
434 
435 /*
436  * TSEC ethernet configuration
437  */
438 #define CONFIG_MII		1 /* MII PHY management */
439 #define CONFIG_TSEC1		1
440 #define CONFIG_TSEC1_NAME	"eTSEC0"
441 #define CONFIG_TSEC2		1
442 #define CONFIG_TSEC2_NAME	"eTSEC1"
443 #define TSEC1_PHY_ADDR		0
444 #define TSEC2_PHY_ADDR		1
445 #define TSEC1_PHYIDX		0
446 #define TSEC2_PHYIDX		0
447 #define TSEC1_FLAGS		TSEC_GIGABIT
448 #define TSEC2_FLAGS		TSEC_GIGABIT
449 
450 /* Options are: eTSEC[0-1] */
451 #define CONFIG_ETHPRIME		"eTSEC1"
452 
453 /*
454  * SATA
455  */
456 #define CONFIG_LIBATA
457 #define CONFIG_FSL_SATA
458 
459 #define CONFIG_SYS_SATA_MAX_DEVICE	2
460 #define CONFIG_SATA1
461 #define CONFIG_SYS_SATA1_OFFSET	0x18000
462 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
463 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
464 #define CONFIG_SATA2
465 #define CONFIG_SYS_SATA2_OFFSET	0x19000
466 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
467 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
468 
469 #ifdef CONFIG_FSL_SATA
470 #define CONFIG_LBA48
471 #define CONFIG_CMD_SATA
472 #define CONFIG_DOS_PARTITION
473 #define CONFIG_CMD_EXT2
474 #endif
475 
476 /*
477  * Environment
478  */
479 #if defined(CONFIG_NAND_U_BOOT)
480 	#define CONFIG_ENV_IS_IN_NAND	1
481 	#define CONFIG_ENV_OFFSET		(512 * 1024)
482 	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
483 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
484 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
485 	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
486 	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
487 						 CONFIG_ENV_RANGE)
488 #elif !defined(CONFIG_SYS_RAMBOOT)
489 	#define CONFIG_ENV_IS_IN_FLASH	1
490 	#define CONFIG_ENV_ADDR		\
491 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
492 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
493 	#define CONFIG_ENV_SIZE		0x2000
494 #else
495 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
496 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
497 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
498 	#define CONFIG_ENV_SIZE		0x2000
499 #endif
500 
501 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
502 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
503 
504 /*
505  * BOOTP options
506  */
507 #define CONFIG_BOOTP_BOOTFILESIZE
508 #define CONFIG_BOOTP_BOOTPATH
509 #define CONFIG_BOOTP_GATEWAY
510 #define CONFIG_BOOTP_HOSTNAME
511 
512 /*
513  * Command line configuration.
514  */
515 #include <config_cmd_default.h>
516 
517 #define CONFIG_CMD_PING
518 #define CONFIG_CMD_I2C
519 #define CONFIG_CMD_MII
520 #define CONFIG_CMD_DATE
521 #define CONFIG_CMD_PCI
522 
523 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
524     #undef CONFIG_CMD_SAVEENV
525     #undef CONFIG_CMD_LOADS
526 #endif
527 
528 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
529 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
530 
531 #undef CONFIG_WATCHDOG		/* watchdog disabled */
532 
533 /*
534  * Miscellaneous configurable options
535  */
536 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
537 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
538 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
539 
540 #if defined(CONFIG_CMD_KGDB)
541 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
542 #else
543 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
544 #endif
545 
546 				/* Print Buffer Size */
547 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
548 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
549 				/* Boot Argument Buffer Size */
550 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
551 #define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
552 
553 /*
554  * For booting Linux, the board info and command line data
555  * have to be in the first 256 MB of memory, since this is
556  * the maximum mapped by the Linux kernel during initialization.
557  */
558 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
559 
560 /*
561  * Core HID Setup
562  */
563 #define CONFIG_SYS_HID0_INIT	0x000000000
564 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
565 				 HID0_ENABLE_INSTRUCTION_CACHE | \
566 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
567 #define CONFIG_SYS_HID2		HID2_HBE
568 
569 /*
570  * MMU Setup
571  */
572 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
573 
574 /* DDR: cache cacheable */
575 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
576 				| BATL_PP_RW \
577 				| BATL_MEMCOHERENCE)
578 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
579 				| BATU_BL_128M \
580 				| BATU_VS \
581 				| BATU_VP)
582 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
583 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
584 
585 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
586 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
587 				| BATL_PP_RW \
588 				| BATL_CACHEINHIBIT \
589 				| BATL_GUARDEDSTORAGE)
590 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
591 				| BATU_BL_8M \
592 				| BATU_VS \
593 				| BATU_VP)
594 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
595 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
596 
597 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
598 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
599 				| BATL_PP_RW \
600 				| BATL_MEMCOHERENCE)
601 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
602 				| BATU_BL_32M \
603 				| BATU_VS \
604 				| BATU_VP)
605 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
606 				| BATL_PP_RW \
607 				| BATL_CACHEINHIBIT \
608 				| BATL_GUARDEDSTORAGE)
609 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
610 
611 /* Stack in dcache: cacheable, no memory coherence */
612 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
613 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
614 				| BATU_BL_128K \
615 				| BATU_VS \
616 				| BATU_VP)
617 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
618 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
619 
620 /* PCI MEM space: cacheable */
621 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
622 				| BATL_PP_RW \
623 				| BATL_MEMCOHERENCE)
624 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
625 				| BATU_BL_256M \
626 				| BATU_VS \
627 				| BATU_VP)
628 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
629 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
630 
631 /* PCI MMIO space: cache-inhibit and guarded */
632 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
633 				| BATL_PP_RW \
634 				| BATL_CACHEINHIBIT \
635 				| BATL_GUARDEDSTORAGE)
636 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
637 				| BATU_BL_256M \
638 				| BATU_VS \
639 				| BATU_VP)
640 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
641 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
642 
643 #define CONFIG_SYS_IBAT6L	0
644 #define CONFIG_SYS_IBAT6U	0
645 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
646 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
647 
648 #define CONFIG_SYS_IBAT7L	0
649 #define CONFIG_SYS_IBAT7U	0
650 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
651 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
652 
653 #if defined(CONFIG_CMD_KGDB)
654 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
655 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
656 #endif
657 
658 /*
659  * Environment Configuration
660  */
661 
662 #define CONFIG_ENV_OVERWRITE
663 
664 #if defined(CONFIG_TSEC_ENET)
665 #define CONFIG_HAS_ETH0
666 #define CONFIG_HAS_ETH1
667 #endif
668 
669 #define CONFIG_BAUDRATE 115200
670 
671 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
672 
673 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
674 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
675 
676 #define CONFIG_EXTRA_ENV_SETTINGS					\
677 	"netdev=eth0\0"							\
678 	"consoledev=ttyS0\0"						\
679 	"ramdiskaddr=1000000\0"						\
680 	"ramdiskfile=ramfs.83xx\0"					\
681 	"fdtaddr=780000\0"						\
682 	"fdtfile=mpc8315erdb.dtb\0"					\
683 	"usb_phy_type=utmi\0"						\
684 	""
685 
686 #define CONFIG_NFSBOOTCOMMAND						\
687 	"setenv bootargs root=/dev/nfs rw "				\
688 		"nfsroot=$serverip:$rootpath "				\
689 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
690 							"$netdev:off "	\
691 		"console=$consoledev,$baudrate $othbootargs;"		\
692 	"tftp $loadaddr $bootfile;"					\
693 	"tftp $fdtaddr $fdtfile;"					\
694 	"bootm $loadaddr - $fdtaddr"
695 
696 #define CONFIG_RAMBOOTCOMMAND						\
697 	"setenv bootargs root=/dev/ram rw "				\
698 		"console=$consoledev,$baudrate $othbootargs;"		\
699 	"tftp $ramdiskaddr $ramdiskfile;"				\
700 	"tftp $loadaddr $bootfile;"					\
701 	"tftp $fdtaddr $fdtfile;"					\
702 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
703 
704 
705 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
706 
707 #endif	/* __CONFIG_H */
708