1 /* 2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 13 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 14 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 15 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 16 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 17 18 #ifndef CONFIG_SYS_MONITOR_BASE 19 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 20 #endif 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_E300 1 /* E300 family */ 26 #define CONFIG_MPC831x 1 /* MPC831x CPU family */ 27 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ 28 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ 29 30 /* 31 * System Clock Setup 32 */ 33 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 34 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 35 36 /* 37 * Hardware Reset Configuration Word 38 * if CLKIN is 66.66MHz, then 39 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz 40 */ 41 #define CONFIG_SYS_HRCW_LOW (\ 42 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 43 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 44 HRCWL_SVCOD_DIV_2 |\ 45 HRCWL_CSB_TO_CLKIN_2X1 |\ 46 HRCWL_CORE_TO_CSB_3X1) 47 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 48 HRCWH_PCI_HOST |\ 49 HRCWH_PCI1_ARBITER_ENABLE |\ 50 HRCWH_CORE_ENABLE |\ 51 HRCWH_BOOTSEQ_DISABLE |\ 52 HRCWH_SW_WATCHDOG_DISABLE |\ 53 HRCWH_TSEC1M_IN_RGMII |\ 54 HRCWH_TSEC2M_IN_RGMII |\ 55 HRCWH_BIG_ENDIAN |\ 56 HRCWH_LALE_NORMAL) 57 58 #ifdef CONFIG_NAND_SPL 59 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 60 HRCWH_FROM_0XFFF00100 |\ 61 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 62 HRCWH_RL_EXT_NAND) 63 #else 64 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 65 HRCWH_FROM_0X00000100 |\ 66 HRCWH_ROM_LOC_LOCAL_16BIT |\ 67 HRCWH_RL_EXT_LEGACY) 68 #endif 69 70 /* 71 * System IO Config 72 */ 73 #define CONFIG_SYS_SICRH 0x00000000 74 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ 75 76 #define CONFIG_HWCONFIG 77 78 /* 79 * IMMR new address 80 */ 81 #define CONFIG_SYS_IMMR 0xE0000000 82 83 /* 84 * Arbiter Setup 85 */ 86 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 87 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 88 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 89 90 /* 91 * DDR Setup 92 */ 93 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 95 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 96 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 97 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 98 | DDRCDR_PZ_LOZ \ 99 | DDRCDR_NZ_LOZ \ 100 | DDRCDR_ODT \ 101 | DDRCDR_Q_DRN) 102 /* 0x7b880001 */ 103 /* 104 * Manually set up DDR parameters 105 * consist of two chips HY5PS12621BFP-C4 from HYNIX 106 */ 107 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 108 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 109 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 110 | CSCONFIG_ODT_RD_NEVER \ 111 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 112 | CSCONFIG_ROW_BIT_13 \ 113 | CSCONFIG_COL_BIT_10) 114 /* 0x80010102 */ 115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 116 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 117 | (0 << TIMING_CFG0_WRT_SHIFT) \ 118 | (0 << TIMING_CFG0_RRT_SHIFT) \ 119 | (0 << TIMING_CFG0_WWT_SHIFT) \ 120 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 121 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 122 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 123 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 124 /* 0x00220802 */ 125 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 126 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 127 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 128 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 129 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 130 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 131 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 132 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 133 /* 0x27256222 */ 134 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 135 | (4 << TIMING_CFG2_CPO_SHIFT) \ 136 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 137 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 138 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 139 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 140 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 141 /* 0x121048c5 */ 142 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 143 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 144 /* 0x03600100 */ 145 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 147 | SDRAM_CFG_DBW_32) 148 /* 0x43080000 */ 149 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 150 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 151 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 152 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 153 #define CONFIG_SYS_DDR_MODE2 0x00000000 154 155 /* 156 * Memory test 157 */ 158 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 159 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 160 #define CONFIG_SYS_MEMTEST_END 0x00140000 161 162 /* 163 * The reserved memory 164 */ 165 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 166 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 167 168 /* 169 * Initial RAM Base Address Setup 170 */ 171 #define CONFIG_SYS_INIT_RAM_LOCK 1 172 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 173 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 174 #define CONFIG_SYS_GBL_DATA_OFFSET \ 175 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 176 177 /* 178 * Local Bus Configuration & Clock Setup 179 */ 180 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 181 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 182 #define CONFIG_SYS_LBC_LBCR 0x00040000 183 #define CONFIG_FSL_ELBC 1 184 185 /* 186 * FLASH on the Local Bus 187 */ 188 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 189 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 190 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 191 192 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 193 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 194 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 195 196 /* Window base at flash base */ 197 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 198 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 199 200 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 201 | BR_PS_16 /* 16 bit port */ \ 202 | BR_MS_GPCM /* MSEL = GPCM */ \ 203 | BR_V) /* valid */ 204 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 205 | OR_UPM_XAM \ 206 | OR_GPCM_CSNT \ 207 | OR_GPCM_ACS_DIV2 \ 208 | OR_GPCM_XACS \ 209 | OR_GPCM_SCY_15 \ 210 | OR_GPCM_TRLX_SET \ 211 | OR_GPCM_EHTR_SET \ 212 | OR_GPCM_EAD) 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 215 /* 127 64KB sectors and 8 8KB top sectors per device */ 216 #define CONFIG_SYS_MAX_FLASH_SECT 135 217 218 #undef CONFIG_SYS_FLASH_CHECKSUM 219 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 221 222 /* 223 * NAND Flash on the Local Bus 224 */ 225 226 #ifdef CONFIG_NAND_SPL 227 #define CONFIG_SYS_NAND_BASE 0xFFF00000 228 #else 229 #define CONFIG_SYS_NAND_BASE 0xE0600000 230 #endif 231 232 #define CONFIG_MTD_DEVICE 233 #define CONFIG_MTD_PARTITION 234 235 #define CONFIG_SYS_MAX_NAND_DEVICE 1 236 #define CONFIG_NAND_FSL_ELBC 1 237 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 238 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 239 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 241 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 242 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 243 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 244 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 245 246 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 247 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 248 | BR_PS_8 /* 8 bit port */ \ 249 | BR_MS_FCM /* MSEL = FCM */ \ 250 | BR_V) /* valid */ 251 #define CONFIG_SYS_NAND_OR_PRELIM \ 252 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 253 | OR_FCM_CSCT \ 254 | OR_FCM_CST \ 255 | OR_FCM_CHT \ 256 | OR_FCM_SCY_1 \ 257 | OR_FCM_TRLX \ 258 | OR_FCM_EHTR) 259 /* 0xFFFF8396 */ 260 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 263 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 264 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 265 266 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 267 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 268 269 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 270 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 271 272 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ 273 !defined(CONFIG_NAND_SPL) 274 #define CONFIG_SYS_RAMBOOT 275 #else 276 #undef CONFIG_SYS_RAMBOOT 277 #endif 278 279 /* 280 * Serial Port 281 */ 282 #define CONFIG_SYS_NS16550_SERIAL 283 #define CONFIG_SYS_NS16550_REG_SIZE 1 284 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 285 286 #define CONFIG_SYS_BAUDRATE_TABLE \ 287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 288 289 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 290 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 291 292 /* I2C */ 293 #define CONFIG_SYS_I2C 294 #define CONFIG_SYS_I2C_FSL 295 #define CONFIG_SYS_FSL_I2C_SPEED 400000 296 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 297 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 298 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 299 300 /* 301 * Board info - revision and where boot from 302 */ 303 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 304 305 /* 306 * Config on-board RTC 307 */ 308 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 309 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 310 311 /* 312 * General PCI 313 * Addresses are mapped 1-1. 314 */ 315 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 316 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 317 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 319 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 320 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 321 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 322 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 323 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 324 325 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 326 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 327 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 328 329 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 330 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 331 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 332 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 333 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 334 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 335 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 336 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 337 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 338 339 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 340 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 341 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 342 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 343 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 344 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 345 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 346 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 347 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 348 349 #define CONFIG_PCI_INDIRECT_BRIDGE 350 #define CONFIG_PCIE 351 352 #define CONFIG_EEPRO100 353 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 354 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 355 356 #define CONFIG_HAS_FSL_DR_USB 357 #define CONFIG_SYS_SCCR_USBDRCM 3 358 359 #define CONFIG_USB_EHCI_FSL 360 #define CONFIG_USB_PHY_TYPE "utmi" 361 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 362 363 /* 364 * TSEC 365 */ 366 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 367 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 368 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 369 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 370 371 /* 372 * TSEC ethernet configuration 373 */ 374 #define CONFIG_MII 1 /* MII PHY management */ 375 #define CONFIG_TSEC1 1 376 #define CONFIG_TSEC1_NAME "eTSEC0" 377 #define CONFIG_TSEC2 1 378 #define CONFIG_TSEC2_NAME "eTSEC1" 379 #define TSEC1_PHY_ADDR 0 380 #define TSEC2_PHY_ADDR 1 381 #define TSEC1_PHYIDX 0 382 #define TSEC2_PHYIDX 0 383 #define TSEC1_FLAGS TSEC_GIGABIT 384 #define TSEC2_FLAGS TSEC_GIGABIT 385 386 /* Options are: eTSEC[0-1] */ 387 #define CONFIG_ETHPRIME "eTSEC1" 388 389 /* 390 * SATA 391 */ 392 #define CONFIG_SYS_SATA_MAX_DEVICE 2 393 #define CONFIG_SATA1 394 #define CONFIG_SYS_SATA1_OFFSET 0x18000 395 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 396 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 397 #define CONFIG_SATA2 398 #define CONFIG_SYS_SATA2_OFFSET 0x19000 399 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 400 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 401 402 #ifdef CONFIG_FSL_SATA 403 #define CONFIG_LBA48 404 #endif 405 406 /* 407 * Environment 408 */ 409 #if !defined(CONFIG_SYS_RAMBOOT) 410 #define CONFIG_ENV_ADDR \ 411 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 412 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 413 #define CONFIG_ENV_SIZE 0x2000 414 #else 415 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 416 #define CONFIG_ENV_SIZE 0x2000 417 #endif 418 419 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 420 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 421 422 /* 423 * BOOTP options 424 */ 425 #define CONFIG_BOOTP_BOOTFILESIZE 426 427 /* 428 * Command line configuration. 429 */ 430 431 #undef CONFIG_WATCHDOG /* watchdog disabled */ 432 433 /* 434 * Miscellaneous configurable options 435 */ 436 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 437 438 /* 439 * For booting Linux, the board info and command line data 440 * have to be in the first 256 MB of memory, since this is 441 * the maximum mapped by the Linux kernel during initialization. 442 */ 443 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 444 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 445 446 /* 447 * Core HID Setup 448 */ 449 #define CONFIG_SYS_HID0_INIT 0x000000000 450 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 451 HID0_ENABLE_INSTRUCTION_CACHE | \ 452 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 453 #define CONFIG_SYS_HID2 HID2_HBE 454 455 /* 456 * MMU Setup 457 */ 458 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 459 460 /* DDR: cache cacheable */ 461 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 462 | BATL_PP_RW \ 463 | BATL_MEMCOHERENCE) 464 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 465 | BATU_BL_128M \ 466 | BATU_VS \ 467 | BATU_VP) 468 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 469 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 470 471 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 472 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 473 | BATL_PP_RW \ 474 | BATL_CACHEINHIBIT \ 475 | BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 477 | BATU_BL_8M \ 478 | BATU_VS \ 479 | BATU_VP) 480 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 481 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 482 483 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 484 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 485 | BATL_PP_RW \ 486 | BATL_MEMCOHERENCE) 487 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 488 | BATU_BL_32M \ 489 | BATU_VS \ 490 | BATU_VP) 491 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 492 | BATL_PP_RW \ 493 | BATL_CACHEINHIBIT \ 494 | BATL_GUARDEDSTORAGE) 495 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 496 497 /* Stack in dcache: cacheable, no memory coherence */ 498 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 499 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ 500 | BATU_BL_128K \ 501 | BATU_VS \ 502 | BATU_VP) 503 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 504 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 505 506 /* PCI MEM space: cacheable */ 507 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ 508 | BATL_PP_RW \ 509 | BATL_MEMCOHERENCE) 510 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ 511 | BATU_BL_256M \ 512 | BATU_VS \ 513 | BATU_VP) 514 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 515 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 516 517 /* PCI MMIO space: cache-inhibit and guarded */ 518 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ 519 | BATL_PP_RW \ 520 | BATL_CACHEINHIBIT \ 521 | BATL_GUARDEDSTORAGE) 522 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ 523 | BATU_BL_256M \ 524 | BATU_VS \ 525 | BATU_VP) 526 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 527 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 528 529 #define CONFIG_SYS_IBAT6L 0 530 #define CONFIG_SYS_IBAT6U 0 531 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 532 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 533 534 #define CONFIG_SYS_IBAT7L 0 535 #define CONFIG_SYS_IBAT7U 0 536 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 537 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 538 539 #if defined(CONFIG_CMD_KGDB) 540 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 541 #endif 542 543 /* 544 * Environment Configuration 545 */ 546 547 #define CONFIG_ENV_OVERWRITE 548 549 #if defined(CONFIG_TSEC_ENET) 550 #define CONFIG_HAS_ETH0 551 #define CONFIG_HAS_ETH1 552 #endif 553 554 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 555 556 #define CONFIG_EXTRA_ENV_SETTINGS \ 557 "netdev=eth0\0" \ 558 "consoledev=ttyS0\0" \ 559 "ramdiskaddr=1000000\0" \ 560 "ramdiskfile=ramfs.83xx\0" \ 561 "fdtaddr=780000\0" \ 562 "fdtfile=mpc8315erdb.dtb\0" \ 563 "usb_phy_type=utmi\0" \ 564 "" 565 566 #define CONFIG_NFSBOOTCOMMAND \ 567 "setenv bootargs root=/dev/nfs rw " \ 568 "nfsroot=$serverip:$rootpath " \ 569 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 570 "$netdev:off " \ 571 "console=$consoledev,$baudrate $othbootargs;" \ 572 "tftp $loadaddr $bootfile;" \ 573 "tftp $fdtaddr $fdtfile;" \ 574 "bootm $loadaddr - $fdtaddr" 575 576 #define CONFIG_RAMBOOTCOMMAND \ 577 "setenv bootargs root=/dev/ram rw " \ 578 "console=$consoledev,$baudrate $othbootargs;" \ 579 "tftp $ramdiskaddr $ramdiskfile;" \ 580 "tftp $loadaddr $bootfile;" \ 581 "tftp $fdtaddr $fdtfile;" \ 582 "bootm $loadaddr $ramdiskaddr $fdtaddr" 583 584 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 585 586 #endif /* __CONFIG_H */ 587