1 /*
2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_SYS_GENERIC_BOARD
13 #define CONFIG_DISPLAY_BOARDINFO
14 
15 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
16 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
17 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
18 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
19 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
20 
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE	0xFE000000
23 #endif
24 
25 #ifndef CONFIG_SYS_MONITOR_BASE
26 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
27 #endif
28 
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_E300		1 /* E300 family */
33 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
34 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
35 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
36 
37 /*
38  * System Clock Setup
39  */
40 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
41 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
42 
43 /*
44  * Hardware Reset Configuration Word
45  * if CLKIN is 66.66MHz, then
46  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
47  */
48 #define CONFIG_SYS_HRCW_LOW (\
49 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
50 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
51 	HRCWL_SVCOD_DIV_2 |\
52 	HRCWL_CSB_TO_CLKIN_2X1 |\
53 	HRCWL_CORE_TO_CSB_3X1)
54 #define CONFIG_SYS_HRCW_HIGH_BASE (\
55 	HRCWH_PCI_HOST |\
56 	HRCWH_PCI1_ARBITER_ENABLE |\
57 	HRCWH_CORE_ENABLE |\
58 	HRCWH_BOOTSEQ_DISABLE |\
59 	HRCWH_SW_WATCHDOG_DISABLE |\
60 	HRCWH_TSEC1M_IN_RGMII |\
61 	HRCWH_TSEC2M_IN_RGMII |\
62 	HRCWH_BIG_ENDIAN |\
63 	HRCWH_LALE_NORMAL)
64 
65 #ifdef CONFIG_NAND_SPL
66 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
67 		       HRCWH_FROM_0XFFF00100 |\
68 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
69 		       HRCWH_RL_EXT_NAND)
70 #else
71 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
72 		       HRCWH_FROM_0X00000100 |\
73 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
74 		       HRCWH_RL_EXT_LEGACY)
75 #endif
76 
77 /*
78  * System IO Config
79  */
80 #define CONFIG_SYS_SICRH		0x00000000
81 #define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
82 
83 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
84 #define CONFIG_HWCONFIG
85 
86 /*
87  * IMMR new address
88  */
89 #define CONFIG_SYS_IMMR		0xE0000000
90 
91 /*
92  * Arbiter Setup
93  */
94 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
95 #define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
96 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
97 
98 /*
99  * DDR Setup
100  */
101 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
102 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
104 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
105 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
106 				| DDRCDR_PZ_LOZ \
107 				| DDRCDR_NZ_LOZ \
108 				| DDRCDR_ODT \
109 				| DDRCDR_Q_DRN)
110 				/* 0x7b880001 */
111 /*
112  * Manually set up DDR parameters
113  * consist of two chips HY5PS12621BFP-C4 from HYNIX
114  */
115 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
116 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
117 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
118 				| CSCONFIG_ODT_RD_NEVER \
119 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
120 				| CSCONFIG_ROW_BIT_13 \
121 				| CSCONFIG_COL_BIT_10)
122 				/* 0x80010102 */
123 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
124 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
125 				| (0 << TIMING_CFG0_WRT_SHIFT) \
126 				| (0 << TIMING_CFG0_RRT_SHIFT) \
127 				| (0 << TIMING_CFG0_WWT_SHIFT) \
128 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
129 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
130 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
131 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
132 				/* 0x00220802 */
133 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
134 				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
135 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
136 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
137 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
138 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
139 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
140 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
141 				/* 0x27256222 */
142 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
143 				| (4 << TIMING_CFG2_CPO_SHIFT) \
144 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
145 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
146 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
147 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
148 				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
149 				/* 0x121048c5 */
150 #define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
151 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
152 				/* 0x03600100 */
153 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
154 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
155 				| SDRAM_CFG_DBW_32)
156 				/* 0x43080000 */
157 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
158 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
159 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
160 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
161 #define CONFIG_SYS_DDR_MODE2	0x00000000
162 
163 /*
164  * Memory test
165  */
166 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
167 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
168 #define CONFIG_SYS_MEMTEST_END		0x00140000
169 
170 /*
171  * The reserved memory
172  */
173 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
174 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
175 
176 /*
177  * Initial RAM Base Address Setup
178  */
179 #define CONFIG_SYS_INIT_RAM_LOCK	1
180 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
181 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
182 #define CONFIG_SYS_GBL_DATA_OFFSET	\
183 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
184 
185 /*
186  * Local Bus Configuration & Clock Setup
187  */
188 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
189 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
190 #define CONFIG_SYS_LBC_LBCR		0x00040000
191 #define CONFIG_FSL_ELBC		1
192 
193 /*
194  * FLASH on the Local Bus
195  */
196 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
197 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
198 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
199 
200 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
201 #define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
202 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
203 
204 					/* Window base at flash base */
205 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
206 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
207 
208 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
209 					| BR_PS_16	/* 16 bit port */ \
210 					| BR_MS_GPCM	/* MSEL = GPCM */ \
211 					| BR_V)		/* valid */
212 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
213 					| OR_UPM_XAM \
214 					| OR_GPCM_CSNT \
215 					| OR_GPCM_ACS_DIV2 \
216 					| OR_GPCM_XACS \
217 					| OR_GPCM_SCY_15 \
218 					| OR_GPCM_TRLX_SET \
219 					| OR_GPCM_EHTR_SET \
220 					| OR_GPCM_EAD)
221 
222 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
223 /* 127 64KB sectors and 8 8KB top sectors per device */
224 #define CONFIG_SYS_MAX_FLASH_SECT	135
225 
226 #undef CONFIG_SYS_FLASH_CHECKSUM
227 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
228 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
229 
230 /*
231  * NAND Flash on the Local Bus
232  */
233 
234 #ifdef CONFIG_NAND_SPL
235 #define CONFIG_SYS_NAND_BASE		0xFFF00000
236 #else
237 #define CONFIG_SYS_NAND_BASE		0xE0600000
238 #endif
239 
240 #define CONFIG_MTD_DEVICE
241 #define CONFIG_MTD_PARTITION
242 #define CONFIG_CMD_MTDPARTS
243 #define MTDIDS_DEFAULT			"nand0=e0600000.flash"
244 #define MTDPARTS_DEFAULT		\
245 	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
246 
247 #define CONFIG_SYS_MAX_NAND_DEVICE	1
248 #define CONFIG_CMD_NAND			1
249 #define CONFIG_NAND_FSL_ELBC		1
250 #define CONFIG_SYS_NAND_BLOCK_SIZE	16384
251 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
252 
253 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
254 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
255 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
256 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
257 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
258 
259 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
260 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
261 				| BR_PS_8		/* 8 bit port */ \
262 				| BR_MS_FCM		/* MSEL = FCM */ \
263 				| BR_V)			/* valid */
264 #define CONFIG_SYS_NAND_OR_PRELIM	\
265 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
266 				| OR_FCM_CSCT \
267 				| OR_FCM_CST \
268 				| OR_FCM_CHT \
269 				| OR_FCM_SCY_1 \
270 				| OR_FCM_TRLX \
271 				| OR_FCM_EHTR)
272 				/* 0xFFFF8396 */
273 
274 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
275 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
276 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
277 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
278 
279 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
280 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
281 
282 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
283 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
284 
285 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
286 	!defined(CONFIG_NAND_SPL)
287 #define CONFIG_SYS_RAMBOOT
288 #else
289 #undef CONFIG_SYS_RAMBOOT
290 #endif
291 
292 /*
293  * Serial Port
294  */
295 #define CONFIG_CONS_INDEX	1
296 #define CONFIG_SYS_NS16550
297 #define CONFIG_SYS_NS16550_SERIAL
298 #define CONFIG_SYS_NS16550_REG_SIZE	1
299 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
300 
301 #define CONFIG_SYS_BAUDRATE_TABLE  \
302 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
303 
304 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
305 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
306 
307 /* Use the HUSH parser */
308 #define CONFIG_SYS_HUSH_PARSER
309 
310 /* Pass open firmware flat tree */
311 #define CONFIG_OF_LIBFDT	1
312 #define CONFIG_OF_BOARD_SETUP	1
313 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
314 
315 /* I2C */
316 #define CONFIG_SYS_I2C
317 #define CONFIG_SYS_I2C_FSL
318 #define CONFIG_SYS_FSL_I2C_SPEED	400000
319 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
320 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
321 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
322 
323 /*
324  * Board info - revision and where boot from
325  */
326 #define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
327 
328 /*
329  * Config on-board RTC
330  */
331 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
332 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
333 
334 /*
335  * General PCI
336  * Addresses are mapped 1-1.
337  */
338 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
339 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
340 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
341 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
342 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
343 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
344 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
345 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
346 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
347 
348 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
349 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
350 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
351 
352 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
353 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
354 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
355 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
356 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
357 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
358 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
359 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
360 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
361 
362 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
363 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
364 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
365 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
366 #define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
367 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
368 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
369 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
370 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
371 
372 #define CONFIG_PCI
373 #define CONFIG_PCI_INDIRECT_BRIDGE
374 #define CONFIG_PCIE
375 
376 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
377 
378 #define CONFIG_EEPRO100
379 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
380 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
381 
382 #define CONFIG_HAS_FSL_DR_USB
383 #define CONFIG_SYS_SCCR_USBDRCM		3
384 
385 #define CONFIG_CMD_USB
386 #define CONFIG_USB_STORAGE
387 #define CONFIG_USB_EHCI
388 #define CONFIG_USB_EHCI_FSL
389 #define CONFIG_USB_PHY_TYPE	"utmi"
390 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
391 
392 /*
393  * TSEC
394  */
395 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
396 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
397 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
398 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
399 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
400 
401 /*
402  * TSEC ethernet configuration
403  */
404 #define CONFIG_MII		1 /* MII PHY management */
405 #define CONFIG_TSEC1		1
406 #define CONFIG_TSEC1_NAME	"eTSEC0"
407 #define CONFIG_TSEC2		1
408 #define CONFIG_TSEC2_NAME	"eTSEC1"
409 #define TSEC1_PHY_ADDR		0
410 #define TSEC2_PHY_ADDR		1
411 #define TSEC1_PHYIDX		0
412 #define TSEC2_PHYIDX		0
413 #define TSEC1_FLAGS		TSEC_GIGABIT
414 #define TSEC2_FLAGS		TSEC_GIGABIT
415 
416 /* Options are: eTSEC[0-1] */
417 #define CONFIG_ETHPRIME		"eTSEC1"
418 
419 /*
420  * SATA
421  */
422 #define CONFIG_LIBATA
423 #define CONFIG_FSL_SATA
424 
425 #define CONFIG_SYS_SATA_MAX_DEVICE	2
426 #define CONFIG_SATA1
427 #define CONFIG_SYS_SATA1_OFFSET	0x18000
428 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
429 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
430 #define CONFIG_SATA2
431 #define CONFIG_SYS_SATA2_OFFSET	0x19000
432 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
433 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
434 
435 #ifdef CONFIG_FSL_SATA
436 #define CONFIG_LBA48
437 #define CONFIG_CMD_SATA
438 #define CONFIG_DOS_PARTITION
439 #define CONFIG_CMD_EXT2
440 #endif
441 
442 /*
443  * Environment
444  */
445 #if !defined(CONFIG_SYS_RAMBOOT)
446 	#define CONFIG_ENV_IS_IN_FLASH	1
447 	#define CONFIG_ENV_ADDR		\
448 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
449 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
450 	#define CONFIG_ENV_SIZE		0x2000
451 #else
452 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
453 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
454 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
455 	#define CONFIG_ENV_SIZE		0x2000
456 #endif
457 
458 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
459 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
460 
461 /*
462  * BOOTP options
463  */
464 #define CONFIG_BOOTP_BOOTFILESIZE
465 #define CONFIG_BOOTP_BOOTPATH
466 #define CONFIG_BOOTP_GATEWAY
467 #define CONFIG_BOOTP_HOSTNAME
468 
469 /*
470  * Command line configuration.
471  */
472 #define CONFIG_CMD_PING
473 #define CONFIG_CMD_I2C
474 #define CONFIG_CMD_MII
475 #define CONFIG_CMD_DATE
476 #define CONFIG_CMD_PCI
477 
478 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
479 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
480 
481 #undef CONFIG_WATCHDOG		/* watchdog disabled */
482 
483 /*
484  * Miscellaneous configurable options
485  */
486 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
487 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
488 
489 #if defined(CONFIG_CMD_KGDB)
490 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
491 #else
492 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
493 #endif
494 
495 				/* Print Buffer Size */
496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
497 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
498 				/* Boot Argument Buffer Size */
499 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
500 
501 /*
502  * For booting Linux, the board info and command line data
503  * have to be in the first 256 MB of memory, since this is
504  * the maximum mapped by the Linux kernel during initialization.
505  */
506 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
507 
508 /*
509  * Core HID Setup
510  */
511 #define CONFIG_SYS_HID0_INIT	0x000000000
512 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
513 				 HID0_ENABLE_INSTRUCTION_CACHE | \
514 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
515 #define CONFIG_SYS_HID2		HID2_HBE
516 
517 /*
518  * MMU Setup
519  */
520 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
521 
522 /* DDR: cache cacheable */
523 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
524 				| BATL_PP_RW \
525 				| BATL_MEMCOHERENCE)
526 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
527 				| BATU_BL_128M \
528 				| BATU_VS \
529 				| BATU_VP)
530 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
531 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
532 
533 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
534 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
535 				| BATL_PP_RW \
536 				| BATL_CACHEINHIBIT \
537 				| BATL_GUARDEDSTORAGE)
538 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
539 				| BATU_BL_8M \
540 				| BATU_VS \
541 				| BATU_VP)
542 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
543 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
544 
545 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
546 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
547 				| BATL_PP_RW \
548 				| BATL_MEMCOHERENCE)
549 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
550 				| BATU_BL_32M \
551 				| BATU_VS \
552 				| BATU_VP)
553 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
554 				| BATL_PP_RW \
555 				| BATL_CACHEINHIBIT \
556 				| BATL_GUARDEDSTORAGE)
557 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
558 
559 /* Stack in dcache: cacheable, no memory coherence */
560 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
561 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
562 				| BATU_BL_128K \
563 				| BATU_VS \
564 				| BATU_VP)
565 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
566 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
567 
568 /* PCI MEM space: cacheable */
569 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
570 				| BATL_PP_RW \
571 				| BATL_MEMCOHERENCE)
572 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
573 				| BATU_BL_256M \
574 				| BATU_VS \
575 				| BATU_VP)
576 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
577 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
578 
579 /* PCI MMIO space: cache-inhibit and guarded */
580 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
581 				| BATL_PP_RW \
582 				| BATL_CACHEINHIBIT \
583 				| BATL_GUARDEDSTORAGE)
584 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
585 				| BATU_BL_256M \
586 				| BATU_VS \
587 				| BATU_VP)
588 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
589 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
590 
591 #define CONFIG_SYS_IBAT6L	0
592 #define CONFIG_SYS_IBAT6U	0
593 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
594 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
595 
596 #define CONFIG_SYS_IBAT7L	0
597 #define CONFIG_SYS_IBAT7U	0
598 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
599 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
600 
601 #if defined(CONFIG_CMD_KGDB)
602 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
603 #endif
604 
605 /*
606  * Environment Configuration
607  */
608 
609 #define CONFIG_ENV_OVERWRITE
610 
611 #if defined(CONFIG_TSEC_ENET)
612 #define CONFIG_HAS_ETH0
613 #define CONFIG_HAS_ETH1
614 #endif
615 
616 #define CONFIG_BAUDRATE 115200
617 
618 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
619 
620 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
621 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
622 
623 #define CONFIG_EXTRA_ENV_SETTINGS					\
624 	"netdev=eth0\0"							\
625 	"consoledev=ttyS0\0"						\
626 	"ramdiskaddr=1000000\0"						\
627 	"ramdiskfile=ramfs.83xx\0"					\
628 	"fdtaddr=780000\0"						\
629 	"fdtfile=mpc8315erdb.dtb\0"					\
630 	"usb_phy_type=utmi\0"						\
631 	""
632 
633 #define CONFIG_NFSBOOTCOMMAND						\
634 	"setenv bootargs root=/dev/nfs rw "				\
635 		"nfsroot=$serverip:$rootpath "				\
636 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
637 							"$netdev:off "	\
638 		"console=$consoledev,$baudrate $othbootargs;"		\
639 	"tftp $loadaddr $bootfile;"					\
640 	"tftp $fdtaddr $fdtfile;"					\
641 	"bootm $loadaddr - $fdtaddr"
642 
643 #define CONFIG_RAMBOOTCOMMAND						\
644 	"setenv bootargs root=/dev/ram rw "				\
645 		"console=$consoledev,$baudrate $othbootargs;"		\
646 	"tftp $ramdiskaddr $ramdiskfile;"				\
647 	"tftp $loadaddr $bootfile;"					\
648 	"tftp $fdtaddr $fdtfile;"					\
649 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
650 
651 
652 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
653 
654 #endif	/* __CONFIG_H */
655