1 /*
2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #ifndef __CONFIG_H
26 #define __CONFIG_H
27 
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
32 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
33 
34 #ifdef CONFIG_NAND_U_BOOT
35 #define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
36 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
37 #ifdef CONFIG_NAND_SPL
38 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
39 #endif /* CONFIG_NAND_SPL */
40 #endif /* CONFIG_NAND_U_BOOT */
41 
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE	0xFE000000
44 #endif
45 
46 #ifndef CONFIG_SYS_MONITOR_BASE
47 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
48 #endif
49 
50 /*
51  * High Level Configuration Options
52  */
53 #define CONFIG_E300		1 /* E300 family */
54 #define CONFIG_MPC83xx		1 /* MPC83xx family */
55 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
56 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
57 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
58 
59 /*
60  * System Clock Setup
61  */
62 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
63 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
64 
65 /*
66  * Hardware Reset Configuration Word
67  * if CLKIN is 66.66MHz, then
68  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
69  */
70 #define CONFIG_SYS_HRCW_LOW (\
71 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
72 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
73 	HRCWL_SVCOD_DIV_2 |\
74 	HRCWL_CSB_TO_CLKIN_2X1 |\
75 	HRCWL_CORE_TO_CSB_3X1)
76 #define CONFIG_SYS_HRCW_HIGH_BASE (\
77 	HRCWH_PCI_HOST |\
78 	HRCWH_PCI1_ARBITER_ENABLE |\
79 	HRCWH_CORE_ENABLE |\
80 	HRCWH_BOOTSEQ_DISABLE |\
81 	HRCWH_SW_WATCHDOG_DISABLE |\
82 	HRCWH_TSEC1M_IN_RGMII |\
83 	HRCWH_TSEC2M_IN_RGMII |\
84 	HRCWH_BIG_ENDIAN |\
85 	HRCWH_LALE_NORMAL)
86 
87 #ifdef CONFIG_NAND_SPL
88 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
89 		       HRCWH_FROM_0XFFF00100 |\
90 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
91 		       HRCWH_RL_EXT_NAND)
92 #else
93 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
94 		       HRCWH_FROM_0X00000100 |\
95 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
96 		       HRCWH_RL_EXT_LEGACY)
97 #endif
98 
99 /*
100  * System IO Config
101  */
102 #define CONFIG_SYS_SICRH		0x00000000
103 #define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
104 
105 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
106 #define CONFIG_HWCONFIG
107 
108 /*
109  * IMMR new address
110  */
111 #define CONFIG_SYS_IMMR		0xE0000000
112 
113 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
114 #define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
115 #endif
116 
117 /*
118  * Arbiter Setup
119  */
120 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
121 #define CONFIG_SYS_ACR_RPTCNT		3 /* Arbiter repeat count is 4 */
122 #define CONFIG_SYS_SPCR_TSECEP		3 /* eTSEC emergency priority is highest */
123 
124 /*
125  * DDR Setup
126  */
127 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
128 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
129 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
130 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
131 #define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
132 				| DDRCDR_PZ_LOZ \
133 				| DDRCDR_NZ_LOZ \
134 				| DDRCDR_ODT \
135 				| DDRCDR_Q_DRN )
136 				/* 0x7b880001 */
137 /*
138  * Manually set up DDR parameters
139  * consist of two chips HY5PS12621BFP-C4 from HYNIX
140  */
141 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
142 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
143 #define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
144 				| 0x00010000  /* ODT_WR to CSn */ \
145 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
146 				/* 0x80010102 */
147 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
148 #define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
149 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
150 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
151 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
152 				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
153 				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
154 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
155 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
156 				/* 0x00220802 */
157 #define CONFIG_SYS_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
158 				| ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
159 				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
160 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
161 				| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
162 				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
163 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
164 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
165 				/* 0x27256222 */
166 #define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
167 				| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
168 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
169 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
170 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
171 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
172 				| ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
173 				/* 0x121048c5 */
174 #define CONFIG_SYS_DDR_INTERVAL	( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
175 				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
176 				/* 0x03600100 */
177 #define CONFIG_SYS_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
178 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
179 				| SDRAM_CFG_32_BE )
180 				/* 0x43080000 */
181 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
182 #define CONFIG_SYS_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
183 				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
184 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
185 #define CONFIG_SYS_DDR_MODE2		0x00000000
186 
187 /*
188  * Memory test
189  */
190 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
191 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
192 #define CONFIG_SYS_MEMTEST_END		0x00140000
193 
194 /*
195  * The reserved memory
196  */
197 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
198 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
199 
200 /*
201  * Initial RAM Base Address Setup
202  */
203 #define CONFIG_SYS_INIT_RAM_LOCK	1
204 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
205 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
206 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
207 
208 /*
209  * Local Bus Configuration & Clock Setup
210  */
211 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
212 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
213 #define CONFIG_SYS_LBC_LBCR		0x00040000
214 #define CONFIG_FSL_ELBC		1
215 
216 /*
217  * FLASH on the Local Bus
218  */
219 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
220 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
221 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
222 
223 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
224 #define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
225 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
226 
227 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
228 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
229 
230 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
231 				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
232 				| BR_V )		/* valid */
233 #define CONFIG_SYS_NOR_OR_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
234 				| OR_UPM_XAM \
235 				| OR_GPCM_CSNT \
236 				| OR_GPCM_ACS_DIV2 \
237 				| OR_GPCM_XACS \
238 				| OR_GPCM_SCY_15 \
239 				| OR_GPCM_TRLX \
240 				| OR_GPCM_EHTR \
241 				| OR_GPCM_EAD )
242 
243 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
244 #define CONFIG_SYS_MAX_FLASH_SECT	135 /* 127 64KB sectors and 8 8KB top sectors per device */
245 
246 #undef CONFIG_SYS_FLASH_CHECKSUM
247 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
248 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
249 
250 /*
251  * NAND Flash on the Local Bus
252  */
253 
254 #ifdef CONFIG_NAND_SPL
255 #define CONFIG_SYS_NAND_BASE		0xFFF00000
256 #else
257 #define CONFIG_SYS_NAND_BASE		0xE0600000
258 #endif
259 
260 #define CONFIG_MTD_DEVICE
261 #define CONFIG_MTD_PARTITION
262 #define CONFIG_CMD_MTDPARTS
263 #define MTDIDS_DEFAULT			"nand0=e0600000.flash"
264 #define MTDPARTS_DEFAULT 		\
265 	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
266 
267 #define CONFIG_SYS_MAX_NAND_DEVICE	1
268 #define CONFIG_MTD_NAND_VERIFY_WRITE	1
269 #define CONFIG_CMD_NAND			1
270 #define CONFIG_NAND_FSL_ELBC		1
271 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
272 
273 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
274 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
275 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
276 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
277 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
278 
279 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
280 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
281 				| BR_PS_8		/* Port Size = 8 bit */ \
282 				| BR_MS_FCM		/* MSEL = FCM */ \
283 				| BR_V )		/* valid */
284 #define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFF8000	/* length 32K */ \
285 				| OR_FCM_CSCT \
286 				| OR_FCM_CST \
287 				| OR_FCM_CHT \
288 				| OR_FCM_SCY_1 \
289 				| OR_FCM_TRLX \
290 				| OR_FCM_EHTR )
291 				/* 0xFFFF8396 */
292 
293 #ifdef CONFIG_NAND_U_BOOT
294 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
295 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
296 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
297 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
298 #else
299 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
300 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
301 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
302 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
303 #endif
304 
305 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
306 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
307 
308 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
309 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
310 
311 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
312 	!defined(CONFIG_NAND_SPL)
313 #define CONFIG_SYS_RAMBOOT
314 #else
315 #undef CONFIG_SYS_RAMBOOT
316 #endif
317 
318 /*
319  * Serial Port
320  */
321 #define CONFIG_CONS_INDEX	1
322 #define CONFIG_SYS_NS16550
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE	1
325 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
326 
327 #define CONFIG_SYS_BAUDRATE_TABLE  \
328 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
329 
330 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
331 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
332 
333 /* Use the HUSH parser */
334 #define CONFIG_SYS_HUSH_PARSER
335 #ifdef CONFIG_SYS_HUSH_PARSER
336 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
337 #endif
338 
339 /* Pass open firmware flat tree */
340 #define CONFIG_OF_LIBFDT	1
341 #define CONFIG_OF_BOARD_SETUP	1
342 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
343 
344 /* I2C */
345 #define CONFIG_HARD_I2C		/* I2C with hardware support */
346 #define CONFIG_FSL_I2C
347 #define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
348 #define CONFIG_SYS_I2C_SLAVE		0x7F
349 #define CONFIG_SYS_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
350 #define CONFIG_SYS_I2C_OFFSET		0x3000
351 #define CONFIG_SYS_I2C2_OFFSET		0x3100
352 
353 /*
354  * Board info - revision and where boot from
355  */
356 #define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
357 
358 /*
359  * Config on-board RTC
360  */
361 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
362 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
363 
364 /*
365  * General PCI
366  * Addresses are mapped 1-1.
367  */
368 #define CONFIG_SYS_PCI_MEM_BASE	0x80000000
369 #define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
370 #define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
371 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
372 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
373 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
374 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
375 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
376 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
377 
378 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
379 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
380 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
381 
382 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
383 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
384 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
385 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
386 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
387 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
388 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
389 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
390 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
391 
392 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
393 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
394 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
395 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
396 #define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
397 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
398 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
399 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
400 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
401 
402 #define CONFIG_PCI
403 #define CONFIG_PCIE
404 
405 #define CONFIG_NET_MULTI
406 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
407 
408 #define CONFIG_EEPRO100
409 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
410 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
411 
412 #ifndef CONFIG_NET_MULTI
413 #define CONFIG_NET_MULTI	1
414 #endif
415 
416 #define CONFIG_HAS_FSL_DR_USB
417 #define CONFIG_SYS_SCCR_USBDRCM		3
418 
419 #define CONFIG_CMD_USB
420 #define CONFIG_USB_STORAGE
421 #define CONFIG_USB_EHCI
422 #define CONFIG_USB_EHCI_FSL
423 #define CONFIG_USB_PHY_TYPE 	"utmi"
424 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
425 
426 /*
427  * TSEC
428  */
429 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
430 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
431 #define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
432 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
433 #define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
434 
435 /*
436  * TSEC ethernet configuration
437  */
438 #define CONFIG_MII		1 /* MII PHY management */
439 #define CONFIG_TSEC1		1
440 #define CONFIG_TSEC1_NAME	"eTSEC0"
441 #define CONFIG_TSEC2		1
442 #define CONFIG_TSEC2_NAME	"eTSEC1"
443 #define TSEC1_PHY_ADDR		0
444 #define TSEC2_PHY_ADDR		1
445 #define TSEC1_PHYIDX		0
446 #define TSEC2_PHYIDX		0
447 #define TSEC1_FLAGS		TSEC_GIGABIT
448 #define TSEC2_FLAGS		TSEC_GIGABIT
449 
450 /* Options are: eTSEC[0-1] */
451 #define CONFIG_ETHPRIME		"eTSEC1"
452 
453 /*
454  * SATA
455  */
456 #define CONFIG_LIBATA
457 #define CONFIG_FSL_SATA
458 
459 #define CONFIG_SYS_SATA_MAX_DEVICE	2
460 #define CONFIG_SATA1
461 #define CONFIG_SYS_SATA1_OFFSET	0x18000
462 #define CONFIG_SYS_SATA1		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
463 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
464 #define CONFIG_SATA2
465 #define CONFIG_SYS_SATA2_OFFSET	0x19000
466 #define CONFIG_SYS_SATA2		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
467 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
468 
469 #ifdef CONFIG_FSL_SATA
470 #define CONFIG_LBA48
471 #define CONFIG_CMD_SATA
472 #define CONFIG_DOS_PARTITION
473 #define CONFIG_CMD_EXT2
474 #endif
475 
476 /*
477  * Environment
478  */
479 #if defined(CONFIG_NAND_U_BOOT)
480 	#define CONFIG_ENV_IS_IN_NAND	1
481 	#define CONFIG_ENV_OFFSET		(512 * 1024)
482 	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
483 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
484 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
485 	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
486 	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
487 						 CONFIG_ENV_RANGE)
488 #elif !defined(CONFIG_SYS_RAMBOOT)
489 	#define CONFIG_ENV_IS_IN_FLASH	1
490 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
491 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
492 	#define CONFIG_ENV_SIZE		0x2000
493 #else
494 	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
495 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
496 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
497 	#define CONFIG_ENV_SIZE		0x2000
498 #endif
499 
500 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
501 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
502 
503 /*
504  * BOOTP options
505  */
506 #define CONFIG_BOOTP_BOOTFILESIZE
507 #define CONFIG_BOOTP_BOOTPATH
508 #define CONFIG_BOOTP_GATEWAY
509 #define CONFIG_BOOTP_HOSTNAME
510 
511 /*
512  * Command line configuration.
513  */
514 #include <config_cmd_default.h>
515 
516 #define CONFIG_CMD_PING
517 #define CONFIG_CMD_I2C
518 #define CONFIG_CMD_MII
519 #define CONFIG_CMD_DATE
520 #define CONFIG_CMD_PCI
521 
522 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
523     #undef CONFIG_CMD_SAVEENV
524     #undef CONFIG_CMD_LOADS
525 #endif
526 
527 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
528 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
529 
530 #undef CONFIG_WATCHDOG		/* watchdog disabled */
531 
532 /*
533  * Miscellaneous configurable options
534  */
535 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
536 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
537 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
538 
539 #if defined(CONFIG_CMD_KGDB)
540 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
541 #else
542 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
543 #endif
544 
545 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
546 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
547 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
548 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
549 
550 /*
551  * For booting Linux, the board info and command line data
552  * have to be in the first 256 MB of memory, since this is
553  * the maximum mapped by the Linux kernel during initialization.
554  */
555 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20) /* Initial Memory map for Linux */
556 
557 /*
558  * Core HID Setup
559  */
560 #define CONFIG_SYS_HID0_INIT	0x000000000
561 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
562 				 HID0_ENABLE_INSTRUCTION_CACHE | \
563 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
564 #define CONFIG_SYS_HID2		HID2_HBE
565 
566 /*
567  * MMU Setup
568  */
569 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
570 
571 /* DDR: cache cacheable */
572 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
573 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
574 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
575 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
576 
577 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
578 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
579 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
580 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
581 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
582 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
583 
584 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
585 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
586 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
587 				 BATU_VS | BATU_VP)
588 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
589 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
590 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
591 
592 /* Stack in dcache: cacheable, no memory coherence */
593 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
594 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
595 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
596 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
597 
598 /* PCI MEM space: cacheable */
599 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
600 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
601 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
602 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
603 
604 /* PCI MMIO space: cache-inhibit and guarded */
605 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
606 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
607 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
608 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
609 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
610 
611 #define CONFIG_SYS_IBAT6L	0
612 #define CONFIG_SYS_IBAT6U	0
613 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
614 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
615 
616 #define CONFIG_SYS_IBAT7L	0
617 #define CONFIG_SYS_IBAT7U	0
618 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
619 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
620 
621 #if defined(CONFIG_CMD_KGDB)
622 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
623 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
624 #endif
625 
626 /*
627  * Environment Configuration
628  */
629 
630 #define CONFIG_ENV_OVERWRITE
631 
632 #if defined(CONFIG_TSEC_ENET)
633 #define CONFIG_HAS_ETH0
634 #define CONFIG_HAS_ETH1
635 #endif
636 
637 #define CONFIG_BAUDRATE 115200
638 
639 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
640 
641 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
642 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
643 
644 #define CONFIG_EXTRA_ENV_SETTINGS					\
645    "netdev=eth0\0"							\
646    "consoledev=ttyS0\0"							\
647    "ramdiskaddr=1000000\0"						\
648    "ramdiskfile=ramfs.83xx\0"						\
649    "fdtaddr=780000\0"							\
650    "fdtfile=mpc8315erdb.dtb\0"						\
651    "usb_phy_type=utmi\0"						\
652    ""
653 
654 #define CONFIG_NFSBOOTCOMMAND						\
655    "setenv bootargs root=/dev/nfs rw "					\
656       "nfsroot=$serverip:$rootpath "					\
657       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
658       "console=$consoledev,$baudrate $othbootargs;"			\
659    "tftp $loadaddr $bootfile;"						\
660    "tftp $fdtaddr $fdtfile;"						\
661    "bootm $loadaddr - $fdtaddr"
662 
663 #define CONFIG_RAMBOOTCOMMAND						\
664    "setenv bootargs root=/dev/ram rw "					\
665       "console=$consoledev,$baudrate $othbootargs;"			\
666    "tftp $ramdiskaddr $ramdiskfile;"					\
667    "tftp $loadaddr $bootfile;"						\
668    "tftp $fdtaddr $fdtfile;"						\
669    "bootm $loadaddr $ramdiskaddr $fdtaddr"
670 
671 
672 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
673 
674 #endif	/* __CONFIG_H */
675