1 /*
2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_DISPLAY_BOARDINFO
13 
14 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
15 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
16 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
17 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
18 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
19 
20 #ifndef CONFIG_SYS_TEXT_BASE
21 #define CONFIG_SYS_TEXT_BASE	0xFE000000
22 #endif
23 
24 #ifndef CONFIG_SYS_MONITOR_BASE
25 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
26 #endif
27 
28 /*
29  * High Level Configuration Options
30  */
31 #define CONFIG_E300		1 /* E300 family */
32 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
33 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
34 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
35 
36 /*
37  * System Clock Setup
38  */
39 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
40 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
41 
42 /*
43  * Hardware Reset Configuration Word
44  * if CLKIN is 66.66MHz, then
45  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
46  */
47 #define CONFIG_SYS_HRCW_LOW (\
48 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
49 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
50 	HRCWL_SVCOD_DIV_2 |\
51 	HRCWL_CSB_TO_CLKIN_2X1 |\
52 	HRCWL_CORE_TO_CSB_3X1)
53 #define CONFIG_SYS_HRCW_HIGH_BASE (\
54 	HRCWH_PCI_HOST |\
55 	HRCWH_PCI1_ARBITER_ENABLE |\
56 	HRCWH_CORE_ENABLE |\
57 	HRCWH_BOOTSEQ_DISABLE |\
58 	HRCWH_SW_WATCHDOG_DISABLE |\
59 	HRCWH_TSEC1M_IN_RGMII |\
60 	HRCWH_TSEC2M_IN_RGMII |\
61 	HRCWH_BIG_ENDIAN |\
62 	HRCWH_LALE_NORMAL)
63 
64 #ifdef CONFIG_NAND_SPL
65 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
66 		       HRCWH_FROM_0XFFF00100 |\
67 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
68 		       HRCWH_RL_EXT_NAND)
69 #else
70 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
71 		       HRCWH_FROM_0X00000100 |\
72 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
73 		       HRCWH_RL_EXT_LEGACY)
74 #endif
75 
76 /*
77  * System IO Config
78  */
79 #define CONFIG_SYS_SICRH		0x00000000
80 #define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
81 
82 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
83 #define CONFIG_HWCONFIG
84 
85 /*
86  * IMMR new address
87  */
88 #define CONFIG_SYS_IMMR		0xE0000000
89 
90 /*
91  * Arbiter Setup
92  */
93 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
94 #define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
95 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
96 
97 /*
98  * DDR Setup
99  */
100 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
101 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
102 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
104 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
105 				| DDRCDR_PZ_LOZ \
106 				| DDRCDR_NZ_LOZ \
107 				| DDRCDR_ODT \
108 				| DDRCDR_Q_DRN)
109 				/* 0x7b880001 */
110 /*
111  * Manually set up DDR parameters
112  * consist of two chips HY5PS12621BFP-C4 from HYNIX
113  */
114 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
115 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
116 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
117 				| CSCONFIG_ODT_RD_NEVER \
118 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
119 				| CSCONFIG_ROW_BIT_13 \
120 				| CSCONFIG_COL_BIT_10)
121 				/* 0x80010102 */
122 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
123 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
124 				| (0 << TIMING_CFG0_WRT_SHIFT) \
125 				| (0 << TIMING_CFG0_RRT_SHIFT) \
126 				| (0 << TIMING_CFG0_WWT_SHIFT) \
127 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
128 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
129 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
130 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
131 				/* 0x00220802 */
132 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
133 				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
134 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
135 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
136 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
137 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
138 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
139 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
140 				/* 0x27256222 */
141 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
142 				| (4 << TIMING_CFG2_CPO_SHIFT) \
143 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
144 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
145 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
146 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
147 				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
148 				/* 0x121048c5 */
149 #define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
150 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
151 				/* 0x03600100 */
152 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
153 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
154 				| SDRAM_CFG_DBW_32)
155 				/* 0x43080000 */
156 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
157 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
158 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
159 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
160 #define CONFIG_SYS_DDR_MODE2	0x00000000
161 
162 /*
163  * Memory test
164  */
165 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
166 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
167 #define CONFIG_SYS_MEMTEST_END		0x00140000
168 
169 /*
170  * The reserved memory
171  */
172 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
173 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
174 
175 /*
176  * Initial RAM Base Address Setup
177  */
178 #define CONFIG_SYS_INIT_RAM_LOCK	1
179 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
180 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
181 #define CONFIG_SYS_GBL_DATA_OFFSET	\
182 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 
184 /*
185  * Local Bus Configuration & Clock Setup
186  */
187 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
188 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
189 #define CONFIG_SYS_LBC_LBCR		0x00040000
190 #define CONFIG_FSL_ELBC		1
191 
192 /*
193  * FLASH on the Local Bus
194  */
195 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
196 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
197 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
198 
199 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
200 #define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
201 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
202 
203 					/* Window base at flash base */
204 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
205 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
206 
207 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
208 					| BR_PS_16	/* 16 bit port */ \
209 					| BR_MS_GPCM	/* MSEL = GPCM */ \
210 					| BR_V)		/* valid */
211 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
212 					| OR_UPM_XAM \
213 					| OR_GPCM_CSNT \
214 					| OR_GPCM_ACS_DIV2 \
215 					| OR_GPCM_XACS \
216 					| OR_GPCM_SCY_15 \
217 					| OR_GPCM_TRLX_SET \
218 					| OR_GPCM_EHTR_SET \
219 					| OR_GPCM_EAD)
220 
221 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
222 /* 127 64KB sectors and 8 8KB top sectors per device */
223 #define CONFIG_SYS_MAX_FLASH_SECT	135
224 
225 #undef CONFIG_SYS_FLASH_CHECKSUM
226 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
227 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
228 
229 /*
230  * NAND Flash on the Local Bus
231  */
232 
233 #ifdef CONFIG_NAND_SPL
234 #define CONFIG_SYS_NAND_BASE		0xFFF00000
235 #else
236 #define CONFIG_SYS_NAND_BASE		0xE0600000
237 #endif
238 
239 #define CONFIG_MTD_DEVICE
240 #define CONFIG_MTD_PARTITION
241 #define CONFIG_CMD_MTDPARTS
242 #define MTDIDS_DEFAULT			"nand0=e0600000.flash"
243 #define MTDPARTS_DEFAULT		\
244 	"mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
245 
246 #define CONFIG_SYS_MAX_NAND_DEVICE	1
247 #define CONFIG_CMD_NAND			1
248 #define CONFIG_NAND_FSL_ELBC		1
249 #define CONFIG_SYS_NAND_BLOCK_SIZE	16384
250 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
251 
252 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
253 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
254 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
255 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
256 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
257 
258 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
259 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
260 				| BR_PS_8		/* 8 bit port */ \
261 				| BR_MS_FCM		/* MSEL = FCM */ \
262 				| BR_V)			/* valid */
263 #define CONFIG_SYS_NAND_OR_PRELIM	\
264 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
265 				| OR_FCM_CSCT \
266 				| OR_FCM_CST \
267 				| OR_FCM_CHT \
268 				| OR_FCM_SCY_1 \
269 				| OR_FCM_TRLX \
270 				| OR_FCM_EHTR)
271 				/* 0xFFFF8396 */
272 
273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
277 
278 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
279 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
280 
281 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
282 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
283 
284 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
285 	!defined(CONFIG_NAND_SPL)
286 #define CONFIG_SYS_RAMBOOT
287 #else
288 #undef CONFIG_SYS_RAMBOOT
289 #endif
290 
291 /*
292  * Serial Port
293  */
294 #define CONFIG_CONS_INDEX	1
295 #define CONFIG_SYS_NS16550_SERIAL
296 #define CONFIG_SYS_NS16550_REG_SIZE	1
297 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
298 
299 #define CONFIG_SYS_BAUDRATE_TABLE  \
300 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
301 
302 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
303 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
304 
305 /* I2C */
306 #define CONFIG_SYS_I2C
307 #define CONFIG_SYS_I2C_FSL
308 #define CONFIG_SYS_FSL_I2C_SPEED	400000
309 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
310 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
311 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
312 
313 /*
314  * Board info - revision and where boot from
315  */
316 #define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
317 
318 /*
319  * Config on-board RTC
320  */
321 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
322 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
323 
324 /*
325  * General PCI
326  * Addresses are mapped 1-1.
327  */
328 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
329 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
330 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
331 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
332 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
333 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
334 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
335 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
336 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
337 
338 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
339 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
340 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
341 
342 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
343 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
344 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
345 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
346 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
347 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
348 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
349 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
350 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
351 
352 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
353 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
354 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
355 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
356 #define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
357 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
358 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
359 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
360 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
361 
362 #define CONFIG_PCI
363 #define CONFIG_PCI_INDIRECT_BRIDGE
364 #define CONFIG_PCIE
365 
366 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
367 
368 #define CONFIG_EEPRO100
369 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
370 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
371 
372 #define CONFIG_HAS_FSL_DR_USB
373 #define CONFIG_SYS_SCCR_USBDRCM		3
374 
375 #define CONFIG_USB_EHCI
376 #define CONFIG_USB_EHCI_FSL
377 #define CONFIG_USB_PHY_TYPE	"utmi"
378 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
379 
380 /*
381  * TSEC
382  */
383 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
384 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
385 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
386 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
387 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
388 
389 /*
390  * TSEC ethernet configuration
391  */
392 #define CONFIG_MII		1 /* MII PHY management */
393 #define CONFIG_TSEC1		1
394 #define CONFIG_TSEC1_NAME	"eTSEC0"
395 #define CONFIG_TSEC2		1
396 #define CONFIG_TSEC2_NAME	"eTSEC1"
397 #define TSEC1_PHY_ADDR		0
398 #define TSEC2_PHY_ADDR		1
399 #define TSEC1_PHYIDX		0
400 #define TSEC2_PHYIDX		0
401 #define TSEC1_FLAGS		TSEC_GIGABIT
402 #define TSEC2_FLAGS		TSEC_GIGABIT
403 
404 /* Options are: eTSEC[0-1] */
405 #define CONFIG_ETHPRIME		"eTSEC1"
406 
407 /*
408  * SATA
409  */
410 #define CONFIG_LIBATA
411 #define CONFIG_FSL_SATA
412 
413 #define CONFIG_SYS_SATA_MAX_DEVICE	2
414 #define CONFIG_SATA1
415 #define CONFIG_SYS_SATA1_OFFSET	0x18000
416 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
417 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
418 #define CONFIG_SATA2
419 #define CONFIG_SYS_SATA2_OFFSET	0x19000
420 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
421 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
422 
423 #ifdef CONFIG_FSL_SATA
424 #define CONFIG_LBA48
425 #define CONFIG_CMD_SATA
426 #define CONFIG_DOS_PARTITION
427 #endif
428 
429 /*
430  * Environment
431  */
432 #if !defined(CONFIG_SYS_RAMBOOT)
433 	#define CONFIG_ENV_IS_IN_FLASH	1
434 	#define CONFIG_ENV_ADDR		\
435 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
436 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
437 	#define CONFIG_ENV_SIZE		0x2000
438 #else
439 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
440 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
441 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
442 	#define CONFIG_ENV_SIZE		0x2000
443 #endif
444 
445 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
446 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
447 
448 /*
449  * BOOTP options
450  */
451 #define CONFIG_BOOTP_BOOTFILESIZE
452 #define CONFIG_BOOTP_BOOTPATH
453 #define CONFIG_BOOTP_GATEWAY
454 #define CONFIG_BOOTP_HOSTNAME
455 
456 /*
457  * Command line configuration.
458  */
459 #define CONFIG_CMD_DATE
460 #define CONFIG_CMD_PCI
461 
462 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
463 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
464 
465 #undef CONFIG_WATCHDOG		/* watchdog disabled */
466 
467 /*
468  * Miscellaneous configurable options
469  */
470 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
471 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
472 
473 #if defined(CONFIG_CMD_KGDB)
474 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
475 #else
476 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
477 #endif
478 
479 				/* Print Buffer Size */
480 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
481 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
482 				/* Boot Argument Buffer Size */
483 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
484 
485 /*
486  * For booting Linux, the board info and command line data
487  * have to be in the first 256 MB of memory, since this is
488  * the maximum mapped by the Linux kernel during initialization.
489  */
490 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
491 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
492 
493 /*
494  * Core HID Setup
495  */
496 #define CONFIG_SYS_HID0_INIT	0x000000000
497 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
498 				 HID0_ENABLE_INSTRUCTION_CACHE | \
499 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
500 #define CONFIG_SYS_HID2		HID2_HBE
501 
502 /*
503  * MMU Setup
504  */
505 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
506 
507 /* DDR: cache cacheable */
508 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
509 				| BATL_PP_RW \
510 				| BATL_MEMCOHERENCE)
511 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
512 				| BATU_BL_128M \
513 				| BATU_VS \
514 				| BATU_VP)
515 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
516 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
517 
518 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
519 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
520 				| BATL_PP_RW \
521 				| BATL_CACHEINHIBIT \
522 				| BATL_GUARDEDSTORAGE)
523 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
524 				| BATU_BL_8M \
525 				| BATU_VS \
526 				| BATU_VP)
527 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
528 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
529 
530 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
531 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
532 				| BATL_PP_RW \
533 				| BATL_MEMCOHERENCE)
534 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
535 				| BATU_BL_32M \
536 				| BATU_VS \
537 				| BATU_VP)
538 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
539 				| BATL_PP_RW \
540 				| BATL_CACHEINHIBIT \
541 				| BATL_GUARDEDSTORAGE)
542 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
543 
544 /* Stack in dcache: cacheable, no memory coherence */
545 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
546 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
547 				| BATU_BL_128K \
548 				| BATU_VS \
549 				| BATU_VP)
550 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
551 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
552 
553 /* PCI MEM space: cacheable */
554 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
555 				| BATL_PP_RW \
556 				| BATL_MEMCOHERENCE)
557 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
558 				| BATU_BL_256M \
559 				| BATU_VS \
560 				| BATU_VP)
561 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
562 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
563 
564 /* PCI MMIO space: cache-inhibit and guarded */
565 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
566 				| BATL_PP_RW \
567 				| BATL_CACHEINHIBIT \
568 				| BATL_GUARDEDSTORAGE)
569 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
570 				| BATU_BL_256M \
571 				| BATU_VS \
572 				| BATU_VP)
573 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
574 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
575 
576 #define CONFIG_SYS_IBAT6L	0
577 #define CONFIG_SYS_IBAT6U	0
578 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
579 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
580 
581 #define CONFIG_SYS_IBAT7L	0
582 #define CONFIG_SYS_IBAT7U	0
583 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
584 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
585 
586 #if defined(CONFIG_CMD_KGDB)
587 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
588 #endif
589 
590 /*
591  * Environment Configuration
592  */
593 
594 #define CONFIG_ENV_OVERWRITE
595 
596 #if defined(CONFIG_TSEC_ENET)
597 #define CONFIG_HAS_ETH0
598 #define CONFIG_HAS_ETH1
599 #endif
600 
601 #define CONFIG_BAUDRATE 115200
602 
603 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
604 
605 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
606 
607 #define CONFIG_EXTRA_ENV_SETTINGS					\
608 	"netdev=eth0\0"							\
609 	"consoledev=ttyS0\0"						\
610 	"ramdiskaddr=1000000\0"						\
611 	"ramdiskfile=ramfs.83xx\0"					\
612 	"fdtaddr=780000\0"						\
613 	"fdtfile=mpc8315erdb.dtb\0"					\
614 	"usb_phy_type=utmi\0"						\
615 	""
616 
617 #define CONFIG_NFSBOOTCOMMAND						\
618 	"setenv bootargs root=/dev/nfs rw "				\
619 		"nfsroot=$serverip:$rootpath "				\
620 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
621 							"$netdev:off "	\
622 		"console=$consoledev,$baudrate $othbootargs;"		\
623 	"tftp $loadaddr $bootfile;"					\
624 	"tftp $fdtaddr $fdtfile;"					\
625 	"bootm $loadaddr - $fdtaddr"
626 
627 #define CONFIG_RAMBOOTCOMMAND						\
628 	"setenv bootargs root=/dev/ram rw "				\
629 		"console=$consoledev,$baudrate $othbootargs;"		\
630 	"tftp $ramdiskaddr $ramdiskfile;"				\
631 	"tftp $loadaddr $bootfile;"					\
632 	"tftp $fdtaddr $fdtfile;"					\
633 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
634 
635 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
636 
637 #endif	/* __CONFIG_H */
638