1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 #undef DEBUG 29 30 /* 31 * High Level Configuration Options 32 */ 33 #define CONFIG_E300 1 /* E300 family */ 34 #define CONFIG_MPC83XX 1 /* MPC83xx family */ 35 #define CONFIG_MPC831X 1 /* MPC831x CPU family */ 36 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ 37 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ 38 39 /* 40 * System Clock Setup 41 */ 42 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 43 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 44 45 /* 46 * Hardware Reset Configuration Word 47 * if CLKIN is 66.66MHz, then 48 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz 49 */ 50 #define CFG_HRCW_LOW (\ 51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 53 HRCWL_SVCOD_DIV_2 |\ 54 HRCWL_CSB_TO_CLKIN_2X1 |\ 55 HRCWL_CORE_TO_CSB_3X1) 56 #define CFG_HRCW_HIGH (\ 57 HRCWH_PCI_HOST |\ 58 HRCWH_PCI1_ARBITER_ENABLE |\ 59 HRCWH_CORE_ENABLE |\ 60 HRCWH_FROM_0X00000100 |\ 61 HRCWH_BOOTSEQ_DISABLE |\ 62 HRCWH_SW_WATCHDOG_DISABLE |\ 63 HRCWH_ROM_LOC_LOCAL_16BIT |\ 64 HRCWH_RL_EXT_LEGACY |\ 65 HRCWH_TSEC1M_IN_RGMII |\ 66 HRCWH_TSEC2M_IN_RGMII |\ 67 HRCWH_BIG_ENDIAN |\ 68 HRCWH_LALE_NORMAL) 69 70 /* 71 * System IO Config 72 */ 73 #define CFG_SICRH 0x00000000 74 #define CFG_SICRL 0x00000000 /* 3.3V, no delay */ 75 76 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 77 78 /* 79 * IMMR new address 80 */ 81 #define CFG_IMMR 0xE0000000 82 83 /* 84 * Arbiter Setup 85 */ 86 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 87 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 88 #define CFG_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 89 90 /* 91 * DDR Setup 92 */ 93 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 94 #define CFG_SDRAM_BASE CFG_DDR_BASE 95 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 96 #define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 97 #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 98 | DDRCDR_PZ_LOZ \ 99 | DDRCDR_NZ_LOZ \ 100 | DDRCDR_ODT \ 101 | DDRCDR_Q_DRN ) 102 /* 0x7b880001 */ 103 /* 104 * Manually set up DDR parameters 105 * consist of two chips HY5PS12621BFP-C4 from HYNIX 106 */ 107 #define CFG_DDR_SIZE 128 /* MB */ 108 #define CFG_DDR_CS0_BNDS 0x00000007 109 #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ 110 | 0x00010000 /* ODT_WR to CSn */ \ 111 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 112 /* 0x80010102 */ 113 #define CFG_DDR_TIMING_3 0x00000000 114 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 115 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 116 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 117 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 118 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 119 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 120 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 121 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 122 /* 0x00220802 */ 123 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 124 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 125 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 126 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 127 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ 128 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ 129 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 130 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 131 /* 0x39356222 */ 132 #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 133 | ( 4 << TIMING_CFG2_CPO_SHIFT ) \ 134 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 135 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 136 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 137 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 138 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 139 /* 0x121048c7 */ 140 #define CFG_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 141 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 142 /* 0x03600100 */ 143 #define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ 144 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 145 | SDRAM_CFG_32_BE ) 146 /* 0x43080000 */ 147 #define CFG_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 148 #define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ 149 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 150 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 151 #define CFG_DDR_MODE2 0x00000000 152 153 /* 154 * Memory test 155 */ 156 #undef CFG_DRAM_TEST /* memory test, takes time */ 157 #define CFG_MEMTEST_START 0x00040000 /* memtest region */ 158 #define CFG_MEMTEST_END 0x00140000 159 160 /* 161 * The reserved memory 162 */ 163 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 164 165 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 166 #define CFG_RAMBOOT 167 #else 168 #undef CFG_RAMBOOT 169 #endif 170 171 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 172 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 173 174 /* 175 * Initial RAM Base Address Setup 176 */ 177 #define CFG_INIT_RAM_LOCK 1 178 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 179 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 180 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 181 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 182 183 /* 184 * Local Bus Configuration & Clock Setup 185 */ 186 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) 187 #define CFG_LBC_LBCR 0x00040000 188 189 /* 190 * FLASH on the Local Bus 191 */ 192 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 193 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 194 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 195 196 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 197 #define CFG_FLASH_SIZE 8 /* FLASH size is 8M */ 198 199 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 200 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ 201 202 #define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ 203 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ 204 | BR_V ) /* valid */ 205 #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ 206 | OR_UPM_XAM \ 207 | OR_GPCM_CSNT \ 208 | OR_GPCM_ACS_0b11 \ 209 | OR_GPCM_XACS \ 210 | OR_GPCM_SCY_15 \ 211 | OR_GPCM_TRLX \ 212 | OR_GPCM_EHTR \ 213 | OR_GPCM_EAD ) 214 215 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 216 #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */ 217 218 #undef CFG_FLASH_CHECKSUM 219 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 220 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 221 222 /* 223 * NAND Flash on the Local Bus 224 */ 225 #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ 226 #define CFG_MAX_NAND_DEVICE 1 227 #define NAND_MAX_CHIPS 1 228 #define CONFIG_MTD_NAND_VERIFY_WRITE 229 230 #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ 231 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 232 | BR_PS_8 /* Port Size = 8 bit */ \ 233 | BR_MS_FCM /* MSEL = FCM */ \ 234 | BR_V ) /* valid */ 235 #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 236 | OR_FCM_CSCT \ 237 | OR_FCM_CST \ 238 | OR_FCM_CHT \ 239 | OR_FCM_SCY_1 \ 240 | OR_FCM_TRLX \ 241 | OR_FCM_EHTR ) 242 /* 0xFFFF8396 */ 243 244 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 245 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 246 247 /* 248 * Serial Port 249 */ 250 #define CONFIG_CONS_INDEX 1 251 #undef CONFIG_SERIAL_SOFTWARE_FIFO 252 #define CFG_NS16550 253 #define CFG_NS16550_SERIAL 254 #define CFG_NS16550_REG_SIZE 1 255 #define CFG_NS16550_CLK get_bus_freq(0) 256 257 #define CFG_BAUDRATE_TABLE \ 258 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 259 260 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 261 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 262 263 /* Use the HUSH parser */ 264 #define CFG_HUSH_PARSER 265 #ifdef CFG_HUSH_PARSER 266 #define CFG_PROMPT_HUSH_PS2 "> " 267 #endif 268 269 /* Pass open firmware flat tree */ 270 #define CONFIG_OF_LIBFDT 1 271 #define CONFIG_OF_BOARD_SETUP 1 272 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 273 274 /* I2C */ 275 #define CONFIG_HARD_I2C /* I2C with hardware support */ 276 #define CONFIG_FSL_I2C 277 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 278 #define CFG_I2C_SLAVE 0x7F 279 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 280 #define CFG_I2C_OFFSET 0x3000 281 #define CFG_I2C2_OFFSET 0x3100 282 283 /* 284 * Board info - revision and where boot from 285 */ 286 #define CFG_I2C_PCF8574A_ADDR 0x39 287 288 /* 289 * Config on-board RTC 290 */ 291 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 292 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 293 294 /* 295 * General PCI 296 * Addresses are mapped 1-1. 297 */ 298 #define CFG_PCI_MEM_BASE 0x80000000 299 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE 300 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ 301 #define CFG_PCI_MMIO_BASE 0x90000000 302 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE 303 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ 304 #define CFG_PCI_IO_BASE 0xE0300000 305 #define CFG_PCI_IO_PHYS 0xE0300000 306 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ 307 308 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE 309 #define CFG_PCI_SLV_MEM_BUS 0x00000000 310 #define CFG_PCI_SLV_MEM_SIZE 0x80000000 311 312 #define CONFIG_PCI 313 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ 314 315 #define CONFIG_NET_MULTI 316 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 317 318 #define CONFIG_EEPRO100 319 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 320 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 321 322 #ifndef CONFIG_NET_MULTI 323 #define CONFIG_NET_MULTI 1 324 #endif 325 326 /* 327 * TSEC 328 */ 329 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 330 #define CFG_TSEC1_OFFSET 0x24000 331 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 332 #define CFG_TSEC2_OFFSET 0x25000 333 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 334 335 /* 336 * TSEC ethernet configuration 337 */ 338 #define CONFIG_MII 1 /* MII PHY management */ 339 #define CONFIG_TSEC1 1 340 #define CONFIG_TSEC1_NAME "eTSEC0" 341 #define CONFIG_TSEC2 1 342 #define CONFIG_TSEC2_NAME "eTSEC1" 343 #define TSEC1_PHY_ADDR 0 344 #define TSEC2_PHY_ADDR 1 345 #define TSEC1_PHYIDX 0 346 #define TSEC2_PHYIDX 0 347 #define TSEC1_FLAGS TSEC_GIGABIT 348 #define TSEC2_FLAGS TSEC_GIGABIT 349 350 /* Options are: eTSEC[0-1] */ 351 #define CONFIG_ETHPRIME "eTSEC1" 352 353 /* 354 * Environment 355 */ 356 #ifndef CFG_RAMBOOT 357 #define CFG_ENV_IS_IN_FLASH 1 358 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 359 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 360 #define CFG_ENV_SIZE 0x2000 361 #else 362 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 363 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 364 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 365 #define CFG_ENV_SIZE 0x2000 366 #endif 367 368 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 369 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 370 371 /* 372 * BOOTP options 373 */ 374 #define CONFIG_BOOTP_BOOTFILESIZE 375 #define CONFIG_BOOTP_BOOTPATH 376 #define CONFIG_BOOTP_GATEWAY 377 #define CONFIG_BOOTP_HOSTNAME 378 379 /* 380 * Command line configuration. 381 */ 382 #include <config_cmd_default.h> 383 384 #define CONFIG_CMD_PING 385 #define CONFIG_CMD_I2C 386 #define CONFIG_CMD_MII 387 #define CONFIG_CMD_DATE 388 #define CONFIG_CMD_PCI 389 390 #if defined(CFG_RAMBOOT) 391 #undef CONFIG_CMD_ENV 392 #undef CONFIG_CMD_LOADS 393 #endif 394 395 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 396 397 #undef CONFIG_WATCHDOG /* watchdog disabled */ 398 399 /* 400 * Miscellaneous configurable options 401 */ 402 #define CFG_LONGHELP /* undef to save memory */ 403 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 404 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 405 406 #if defined(CONFIG_CMD_KGDB) 407 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 408 #else 409 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 410 #endif 411 412 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 413 #define CFG_MAXARGS 16 /* max number of command args */ 414 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 415 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 416 417 /* 418 * For booting Linux, the board info and command line data 419 * have to be in the first 8 MB of memory, since this is 420 * the maximum mapped by the Linux kernel during initialization. 421 */ 422 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 423 424 /* 425 * Core HID Setup 426 */ 427 #define CFG_HID0_INIT 0x000000000 428 #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 429 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 430 #define CFG_HID2 HID2_HBE 431 432 /* 433 * MMU Setup 434 */ 435 436 /* DDR: cache cacheable */ 437 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 438 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) 439 #define CFG_DBAT0L CFG_IBAT0L 440 #define CFG_DBAT0U CFG_IBAT0U 441 442 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 443 #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ 444 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 445 #define CFG_IBAT1U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 446 #define CFG_DBAT1L CFG_IBAT1L 447 #define CFG_DBAT1U CFG_IBAT1U 448 449 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 450 #define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 451 #define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) 452 #define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ 453 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 454 #define CFG_DBAT2U CFG_IBAT2U 455 456 /* Stack in dcache: cacheable, no memory coherence */ 457 #define CFG_IBAT3L (CFG_INIT_RAM_ADDR | BATL_PP_10) 458 #define CFG_IBAT3U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 459 #define CFG_DBAT3L CFG_IBAT3L 460 #define CFG_DBAT3U CFG_IBAT3U 461 462 /* PCI MEM space: cacheable */ 463 #define CFG_IBAT4L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 464 #define CFG_IBAT4U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 465 #define CFG_DBAT4L CFG_IBAT4L 466 #define CFG_DBAT4U CFG_IBAT4U 467 468 /* PCI MMIO space: cache-inhibit and guarded */ 469 #define CFG_IBAT5L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ 470 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 471 #define CFG_IBAT5U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 472 #define CFG_DBAT5L CFG_IBAT5L 473 #define CFG_DBAT5U CFG_IBAT5U 474 475 #define CFG_IBAT6L 0 476 #define CFG_IBAT6U 0 477 #define CFG_DBAT6L CFG_IBAT6L 478 #define CFG_DBAT6U CFG_IBAT6U 479 480 #define CFG_IBAT7L 0 481 #define CFG_IBAT7U 0 482 #define CFG_DBAT7L CFG_IBAT7L 483 #define CFG_DBAT7U CFG_IBAT7U 484 485 /* 486 * Internal Definitions 487 * 488 * Boot Flags 489 */ 490 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 491 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 492 493 #if defined(CONFIG_CMD_KGDB) 494 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 495 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 496 #endif 497 498 /* 499 * Environment Configuration 500 */ 501 502 #define CONFIG_ENV_OVERWRITE 503 504 #if defined(CONFIG_TSEC_ENET) 505 #define CONFIG_HAS_ETH0 506 #define CONFIG_ETHADDR 04:00:00:00:00:0A 507 #define CONFIG_HAS_ETH1 508 #define CONFIG_ETH1ADDR 04:00:00:00:00:0B 509 #endif 510 511 #define CONFIG_BAUDRATE 115200 512 513 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 514 515 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 516 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 517 518 #define CONFIG_EXTRA_ENV_SETTINGS \ 519 "netdev=eth0\0" \ 520 "consoledev=ttyS0\0" \ 521 "ramdiskaddr=1000000\0" \ 522 "ramdiskfile=ramfs.83xx\0" \ 523 "fdtaddr=400000\0" \ 524 "fdtfile=mpc8315erdb.dtb\0" \ 525 "" 526 527 #define CONFIG_NFSBOOTCOMMAND \ 528 "setenv bootargs root=/dev/nfs rw " \ 529 "nfsroot=$serverip:$rootpath " \ 530 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 531 "console=$consoledev,$baudrate $othbootargs;" \ 532 "tftp $loadaddr $bootfile;" \ 533 "tftp $fdtaddr $fdtfile;" \ 534 "bootm $loadaddr - $fdtaddr" 535 536 #define CONFIG_RAMBOOTCOMMAND \ 537 "setenv bootargs root=/dev/ram rw " \ 538 "console=$consoledev,$baudrate $othbootargs;" \ 539 "tftp $ramdiskaddr $ramdiskfile;" \ 540 "tftp $loadaddr $bootfile;" \ 541 "tftp $fdtaddr $fdtfile;" \ 542 "bootm $loadaddr $ramdiskaddr $fdtaddr" 543 544 545 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 546 547 #endif /* __CONFIG_H */ 548