1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83XX 1 34 #define CONFIG_MPC831X 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #define CONFIG_PCI 39 #define CONFIG_83XX_GENERIC_PCI 40 41 #define CONFIG_MISC_INIT_R 42 43 /* 44 * On-board devices 45 * 46 * TSEC1 is VSC switch 47 * TSEC2 is SoC TSEC 48 */ 49 #define CONFIG_VSC7385_ENET 50 #define CONFIG_TSEC2 51 52 #ifdef CFG_66MHZ 53 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 54 #elif defined(CFG_33MHZ) 55 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 56 #else 57 #error Unknown oscillator frequency. 58 #endif 59 60 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 61 62 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 63 64 #define CFG_IMMR 0xE0000000 65 66 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 67 #define CONFIG_DEFAULT_IMMR CFG_IMMR 68 #endif 69 70 #define CFG_MEMTEST_START 0x00001000 71 #define CFG_MEMTEST_END 0x07f00000 72 73 /* Early revs of this board will lock up hard when attempting 74 * to access the PMC registers, unless a JTAG debugger is 75 * connected, or some resistor modifications are made. 76 */ 77 #define CFG_8313ERDB_BROKEN_PMC 1 78 79 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 80 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 81 82 /* 83 * Device configurations 84 */ 85 86 /* Vitesse 7385 */ 87 88 #ifdef CONFIG_VSC7385_ENET 89 90 #define CONFIG_TSEC1 91 92 /* The flash address and size of the VSC7385 firmware image */ 93 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 94 #define CONFIG_VSC7385_IMAGE_SIZE 8192 95 96 #endif 97 98 /* 99 * DDR Setup 100 */ 101 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 102 #define CFG_SDRAM_BASE CFG_DDR_BASE 103 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 104 105 /* 106 * Manually set up DDR parameters, as this board does not 107 * seem to have the SPD connected to I2C. 108 */ 109 #define CFG_DDR_SIZE 128 /* MB */ 110 #define CFG_DDR_CONFIG ( CSCONFIG_EN \ 111 | 0x00010000 /* TODO */ \ 112 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 113 /* 0x80010102 */ 114 115 #define CFG_DDR_TIMING_3 0x00000000 116 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 117 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 118 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 119 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 120 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 121 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 122 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 123 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 124 /* 0x00220802 */ 125 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 126 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 127 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 128 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 129 | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 130 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 131 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 132 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 133 /* 0x3835a322 */ 134 #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 135 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 136 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 137 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 138 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 139 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 140 | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 141 /* 0x129048c6 */ /* P9-45,may need tuning */ 142 #define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 143 | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 144 /* 0x05100500 */ 145 #if defined(CONFIG_DDR_2T_TIMING) 146 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 147 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 148 | SDRAM_CFG_2T_EN \ 149 | SDRAM_CFG_DBW_32 ) 150 #else 151 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 152 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 153 | SDRAM_CFG_32_BE ) 154 /* 0x43080000 */ 155 #endif 156 #define CFG_SDRAM_CFG2 0x00401000; 157 /* set burst length to 8 for 32-bit data path */ 158 #define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 159 | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 160 /* 0x44480632 */ 161 #define CFG_DDR_MODE_2 0x8000C000; 162 163 #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 164 /*0x02000000*/ 165 #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 166 | DDRCDR_PZ_NOMZ \ 167 | DDRCDR_NZ_NOMZ \ 168 | DDRCDR_M_ODR ) 169 170 /* 171 * FLASH on the Local Bus 172 */ 173 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 174 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 175 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 176 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 177 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 178 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 179 180 #define CFG_NOR_BR_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 181 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 182 BR_V) /* valid */ 183 #define CFG_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ 184 | OR_GPCM_XACS \ 185 | OR_GPCM_SCY_9 \ 186 | OR_GPCM_EHTR \ 187 | OR_GPCM_EAD ) 188 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 189 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 190 #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 191 192 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 193 #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 194 195 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 196 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 197 198 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 199 200 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) && !defined(CONFIG_NAND_SPL) 201 #define CFG_RAMBOOT 202 #endif 203 204 #define CFG_INIT_RAM_LOCK 1 205 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 206 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 207 208 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 209 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 210 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 211 212 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 213 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 214 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 215 216 /* 217 * Local Bus LCRR and LBCR regs 218 */ 219 #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 220 #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ 221 | (0xFF << LBCR_BMT_SHIFT) \ 222 | 0xF ) /* 0x0004ff0f */ 223 224 #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 225 226 /* drivers/mtd/nand/nand.c */ 227 #ifdef CONFIG_NAND_SPL 228 #define CFG_NAND_BASE 0xFFF00000 229 #else 230 #define CFG_NAND_BASE 0xE2800000 231 #endif 232 233 #define CFG_MAX_NAND_DEVICE 1 234 #define NAND_MAX_CHIPS 1 235 #define CONFIG_MTD_NAND_VERIFY_WRITE 236 #define CONFIG_CMD_NAND 1 237 #define CONFIG_NAND_FSL_ELBC 1 238 #define CFG_NAND_BLOCK_SIZE 16384 239 240 #define CFG_NAND_U_BOOT_SIZE (512 << 10) 241 #define CFG_NAND_U_BOOT_DST 0x00100000 242 #define CFG_NAND_U_BOOT_START 0x00100100 243 #define CFG_NAND_U_BOOT_OFFS 16384 244 #define CFG_NAND_U_BOOT_RELOC 0x00010000 245 246 #define CFG_NAND_BR_PRELIM ( CFG_NAND_BASE \ 247 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 248 | BR_PS_8 /* Port Size = 8 bit */ \ 249 | BR_MS_FCM /* MSEL = FCM */ \ 250 | BR_V ) /* valid */ 251 #define CFG_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ 252 | OR_FCM_CSCT \ 253 | OR_FCM_CST \ 254 | OR_FCM_CHT \ 255 | OR_FCM_SCY_1 \ 256 | OR_FCM_TRLX \ 257 | OR_FCM_EHTR ) 258 /* 0xFFFF8396 */ 259 260 #ifdef CONFIG_NAND_U_BOOT 261 #define CFG_BR0_PRELIM CFG_NAND_BR_PRELIM 262 #define CFG_OR0_PRELIM CFG_NAND_OR_PRELIM 263 #define CFG_BR1_PRELIM CFG_NOR_BR_PRELIM 264 #define CFG_OR1_PRELIM CFG_NOR_OR_PRELIM 265 #else 266 #define CFG_BR0_PRELIM CFG_NOR_BR_PRELIM 267 #define CFG_OR0_PRELIM CFG_NOR_OR_PRELIM 268 #define CFG_BR1_PRELIM CFG_NAND_BR_PRELIM 269 #define CFG_OR1_PRELIM CFG_NAND_OR_PRELIM 270 #endif 271 272 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 273 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 274 275 #define CFG_NAND_LBLAWBAR_PRELIM CFG_LBLAWBAR1_PRELIM 276 #define CFG_NAND_LBLAWAR_PRELIM CFG_LBLAWAR1_PRELIM 277 278 /* local bus read write buffer mapping */ 279 #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 280 #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 281 #define CFG_LBLAWBAR3_PRELIM 0xFA000000 282 #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 283 284 /* Vitesse 7385 */ 285 286 #define CFG_VSC7385_BASE 0xF0000000 287 288 #ifdef CONFIG_VSC7385_ENET 289 290 #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 291 #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 292 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ 293 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 294 295 #endif 296 297 /* pass open firmware flat tree */ 298 #define CONFIG_OF_LIBFDT 1 299 #define CONFIG_OF_BOARD_SETUP 1 300 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 301 302 /* 303 * Serial Port 304 */ 305 #define CONFIG_CONS_INDEX 1 306 #define CFG_NS16550 307 #define CFG_NS16550_SERIAL 308 #define CFG_NS16550_REG_SIZE 1 309 310 #define CFG_BAUDRATE_TABLE \ 311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 312 313 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 314 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 315 316 /* Use the HUSH parser */ 317 #define CFG_HUSH_PARSER 318 #define CFG_PROMPT_HUSH_PS2 "> " 319 320 /* I2C */ 321 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 322 #define CONFIG_FSL_I2C 323 #define CONFIG_I2C_MULTI_BUS 324 #define CONFIG_I2C_CMD_TREE 325 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 326 #define CFG_I2C_SLAVE 0x7F 327 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 328 #define CFG_I2C_OFFSET 0x3000 329 #define CFG_I2C2_OFFSET 0x3100 330 331 /* 332 * General PCI 333 * Addresses are mapped 1-1. 334 */ 335 #define CFG_PCI1_MEM_BASE 0x80000000 336 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 337 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 338 #define CFG_PCI1_MMIO_BASE 0x90000000 339 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 340 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 341 #define CFG_PCI1_IO_BASE 0x00000000 342 #define CFG_PCI1_IO_PHYS 0xE2000000 343 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 344 345 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 346 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 347 348 /* 349 * TSEC 350 */ 351 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 352 353 #define CONFIG_NET_MULTI 354 #define CONFIG_GMII /* MII PHY management */ 355 356 #ifdef CONFIG_TSEC1 357 #define CONFIG_HAS_ETH0 358 #define CONFIG_TSEC1_NAME "TSEC0" 359 #define CFG_TSEC1_OFFSET 0x24000 360 #define TSEC1_PHY_ADDR 0x1c 361 #define TSEC1_FLAGS TSEC_GIGABIT 362 #define TSEC1_PHYIDX 0 363 #endif 364 365 #ifdef CONFIG_TSEC2 366 #define CONFIG_HAS_ETH1 367 #define CONFIG_TSEC2_NAME "TSEC1" 368 #define CFG_TSEC2_OFFSET 0x25000 369 #define TSEC2_PHY_ADDR 4 370 #define TSEC2_FLAGS TSEC_GIGABIT 371 #define TSEC2_PHYIDX 0 372 #endif 373 374 375 /* Options are: TSEC[0-1] */ 376 #define CONFIG_ETHPRIME "TSEC1" 377 378 /* 379 * Configure on-board RTC 380 */ 381 #define CONFIG_RTC_DS1337 382 #define CFG_I2C_RTC_ADDR 0x68 383 384 /* 385 * Environment 386 */ 387 #if defined(CONFIG_NAND_U_BOOT) 388 #define CFG_ENV_IS_IN_NAND 1 389 #define CFG_ENV_OFFSET (512 * 1024) 390 #define CFG_ENV_SECT_SIZE CFG_NAND_BLOCK_SIZE 391 #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE 392 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE 393 #define CFG_ENV_RANGE (CFG_ENV_SECT_SIZE * 4) 394 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_RANGE) 395 #elif !defined(CFG_RAMBOOT) 396 #define CFG_ENV_IS_IN_FLASH 1 397 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 398 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 399 #define CFG_ENV_SIZE 0x2000 400 401 /* Address and size of Redundant Environment Sector */ 402 #else 403 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 404 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 405 #define CFG_ENV_SIZE 0x2000 406 #endif 407 408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 409 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 410 411 /* 412 * BOOTP options 413 */ 414 #define CONFIG_BOOTP_BOOTFILESIZE 415 #define CONFIG_BOOTP_BOOTPATH 416 #define CONFIG_BOOTP_GATEWAY 417 #define CONFIG_BOOTP_HOSTNAME 418 419 420 /* 421 * Command line configuration. 422 */ 423 #include <config_cmd_default.h> 424 425 #define CONFIG_CMD_PING 426 #define CONFIG_CMD_DHCP 427 #define CONFIG_CMD_I2C 428 #define CONFIG_CMD_MII 429 #define CONFIG_CMD_DATE 430 #define CONFIG_CMD_PCI 431 432 #if defined(CFG_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 433 #undef CONFIG_CMD_ENV 434 #undef CONFIG_CMD_LOADS 435 #endif 436 437 #define CONFIG_CMDLINE_EDITING 1 438 439 440 /* 441 * Miscellaneous configurable options 442 */ 443 #define CFG_LONGHELP /* undef to save memory */ 444 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 445 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 446 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 447 448 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 449 #define CFG_MAXARGS 16 /* max number of command args */ 450 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 451 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 452 453 /* 454 * For booting Linux, the board info and command line data 455 * have to be in the first 8 MB of memory, since this is 456 * the maximum mapped by the Linux kernel during initialization. 457 */ 458 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 459 460 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 461 462 #ifdef CFG_66MHZ 463 464 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 465 /* 0x62040000 */ 466 #define CFG_HRCW_LOW (\ 467 0x20000000 /* reserved, must be set */ |\ 468 HRCWL_DDRCM |\ 469 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 470 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 471 HRCWL_CSB_TO_CLKIN_2X1 |\ 472 HRCWL_CORE_TO_CSB_2X1) 473 474 #define CFG_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 475 476 #elif defined(CFG_33MHZ) 477 478 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 479 /* 0x65040000 */ 480 #define CFG_HRCW_LOW (\ 481 0x20000000 /* reserved, must be set */ |\ 482 HRCWL_DDRCM |\ 483 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 484 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 485 HRCWL_CSB_TO_CLKIN_5X1 |\ 486 HRCWL_CORE_TO_CSB_2X1) 487 488 #define CFG_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 489 490 #endif 491 492 #define CFG_HRCW_HIGH_BASE (\ 493 HRCWH_PCI_HOST |\ 494 HRCWH_PCI1_ARBITER_ENABLE |\ 495 HRCWH_CORE_ENABLE |\ 496 HRCWH_BOOTSEQ_DISABLE |\ 497 HRCWH_SW_WATCHDOG_DISABLE |\ 498 HRCWH_TSEC1M_IN_RGMII |\ 499 HRCWH_TSEC2M_IN_RGMII |\ 500 HRCWH_BIG_ENDIAN) 501 502 #ifdef CONFIG_NAND_SPL 503 #define CFG_HRCW_HIGH (CFG_HRCW_HIGH_BASE |\ 504 HRCWH_FROM_0XFFF00100 |\ 505 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 506 HRCWH_RL_EXT_NAND) 507 #else 508 #define CFG_HRCW_HIGH (CFG_HRCW_HIGH_BASE |\ 509 HRCWH_FROM_0X00000100 |\ 510 HRCWH_ROM_LOC_LOCAL_16BIT |\ 511 HRCWH_RL_EXT_LEGACY) 512 #endif 513 514 /* System IO Config */ 515 #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 516 #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 517 518 #define CFG_HID0_INIT 0x000000000 519 #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 520 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 521 522 #define CFG_HID2 HID2_HBE 523 524 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 525 526 /* DDR @ 0x00000000 */ 527 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) 528 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 529 530 /* PCI @ 0x80000000 */ 531 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) 532 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 533 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 534 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 535 536 /* PCI2 not supported on 8313 */ 537 #define CFG_IBAT3L (0) 538 #define CFG_IBAT3U (0) 539 #define CFG_IBAT4L (0) 540 #define CFG_IBAT4U (0) 541 542 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 543 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 544 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 545 546 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 547 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) 548 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 549 550 #define CFG_IBAT7L (0) 551 #define CFG_IBAT7U (0) 552 553 #define CFG_DBAT0L CFG_IBAT0L 554 #define CFG_DBAT0U CFG_IBAT0U 555 #define CFG_DBAT1L CFG_IBAT1L 556 #define CFG_DBAT1U CFG_IBAT1U 557 #define CFG_DBAT2L CFG_IBAT2L 558 #define CFG_DBAT2U CFG_IBAT2U 559 #define CFG_DBAT3L CFG_IBAT3L 560 #define CFG_DBAT3U CFG_IBAT3U 561 #define CFG_DBAT4L CFG_IBAT4L 562 #define CFG_DBAT4U CFG_IBAT4U 563 #define CFG_DBAT5L CFG_IBAT5L 564 #define CFG_DBAT5U CFG_IBAT5U 565 #define CFG_DBAT6L CFG_IBAT6L 566 #define CFG_DBAT6U CFG_IBAT6U 567 #define CFG_DBAT7L CFG_IBAT7L 568 #define CFG_DBAT7U CFG_IBAT7U 569 570 /* 571 * Internal Definitions 572 * 573 * Boot Flags 574 */ 575 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 576 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 577 578 /* 579 * Environment Configuration 580 */ 581 #define CONFIG_ENV_OVERWRITE 582 583 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 584 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 585 586 #define CONFIG_IPADDR 10.0.0.2 587 #define CONFIG_SERVERIP 10.0.0.1 588 #define CONFIG_GATEWAYIP 10.0.0.1 589 #define CONFIG_NETMASK 255.0.0.0 590 #define CONFIG_NETDEV eth1 591 592 #define CONFIG_HOSTNAME mpc8313erdb 593 #define CONFIG_ROOTPATH /nfs/root/path 594 #define CONFIG_BOOTFILE uImage 595 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 596 #define CONFIG_FDTFILE mpc8313erdb.dtb 597 598 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 599 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 600 #define CONFIG_BAUDRATE 115200 601 602 #define XMK_STR(x) #x 603 #define MK_STR(x) XMK_STR(x) 604 605 #define CONFIG_EXTRA_ENV_SETTINGS \ 606 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 607 "ethprime=TSEC1\0" \ 608 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 609 "tftpflash=tftpboot $loadaddr $uboot; " \ 610 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 611 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 612 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 613 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 614 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 615 "fdtaddr=400000\0" \ 616 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 617 "console=ttyS0\0" \ 618 "setbootargs=setenv bootargs " \ 619 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 620 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 621 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 622 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 623 624 #define CONFIG_NFSBOOTCOMMAND \ 625 "setenv rootdev /dev/nfs;" \ 626 "run setbootargs;" \ 627 "run setipargs;" \ 628 "tftp $loadaddr $bootfile;" \ 629 "tftp $fdtaddr $fdtfile;" \ 630 "bootm $loadaddr - $fdtaddr" 631 632 #define CONFIG_RAMBOOTCOMMAND \ 633 "setenv rootdev /dev/ram;" \ 634 "run setbootargs;" \ 635 "tftp $ramdiskaddr $ramdiskfile;" \ 636 "tftp $loadaddr $bootfile;" \ 637 "tftp $fdtaddr $fdtfile;" \ 638 "bootm $loadaddr $ramdiskaddr $fdtaddr" 639 640 #undef MK_STR 641 #undef XMK_STR 642 643 #endif /* __CONFIG_H */ 644