1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 19 #define CONFIG_MPC831x 1 20 #define CONFIG_MPC8313 1 21 #define CONFIG_MPC8313ERDB 1 22 23 #ifdef CONFIG_NAND 24 #define CONFIG_SPL_INIT_MINIMAL 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 28 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_NS16550_MIN_FUNCTIONS 31 #endif 32 33 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 34 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 35 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 36 #define CONFIG_SPL_PAD_TO 0x4000 37 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44 45 #ifdef CONFIG_SPL_BUILD 46 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 47 #endif 48 49 #endif /* CONFIG_NAND */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xFE000000 53 #endif 54 55 #ifndef CONFIG_SYS_MONITOR_BASE 56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 57 #endif 58 59 #define CONFIG_PCI 60 #define CONFIG_PCI_INDIRECT_BRIDGE 61 #define CONFIG_FSL_ELBC 1 62 63 #define CONFIG_MISC_INIT_R 64 65 /* 66 * On-board devices 67 * 68 * TSEC1 is VSC switch 69 * TSEC2 is SoC TSEC 70 */ 71 #define CONFIG_VSC7385_ENET 72 #define CONFIG_TSEC2 73 74 #ifdef CONFIG_SYS_66MHZ 75 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 76 #elif defined(CONFIG_SYS_33MHZ) 77 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 78 #else 79 #error Unknown oscillator frequency. 80 #endif 81 82 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 83 84 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 85 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 86 87 #define CONFIG_SYS_IMMR 0xE0000000 88 89 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 90 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91 #endif 92 93 #define CONFIG_SYS_MEMTEST_START 0x00001000 94 #define CONFIG_SYS_MEMTEST_END 0x07f00000 95 96 /* Early revs of this board will lock up hard when attempting 97 * to access the PMC registers, unless a JTAG debugger is 98 * connected, or some resistor modifications are made. 99 */ 100 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 101 102 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 103 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 104 105 /* 106 * Device configurations 107 */ 108 109 /* Vitesse 7385 */ 110 111 #ifdef CONFIG_VSC7385_ENET 112 113 #define CONFIG_TSEC1 114 115 /* The flash address and size of the VSC7385 firmware image */ 116 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 117 #define CONFIG_VSC7385_IMAGE_SIZE 8192 118 119 #endif 120 121 /* 122 * DDR Setup 123 */ 124 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 126 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 127 128 /* 129 * Manually set up DDR parameters, as this board does not 130 * seem to have the SPD connected to I2C. 131 */ 132 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 133 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 134 | CSCONFIG_ODT_RD_NEVER \ 135 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 136 | CSCONFIG_ROW_BIT_13 \ 137 | CSCONFIG_COL_BIT_10) 138 /* 0x80010102 */ 139 140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 141 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 142 | (0 << TIMING_CFG0_WRT_SHIFT) \ 143 | (0 << TIMING_CFG0_RRT_SHIFT) \ 144 | (0 << TIMING_CFG0_WWT_SHIFT) \ 145 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 146 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 147 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 148 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 149 /* 0x00220802 */ 150 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 151 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 152 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 153 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 154 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 155 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 156 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 157 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 158 /* 0x3835a322 */ 159 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 160 | (5 << TIMING_CFG2_CPO_SHIFT) \ 161 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 162 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 163 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 164 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 165 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 166 /* 0x129048c6 */ /* P9-45,may need tuning */ 167 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 168 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 169 /* 0x05100500 */ 170 #if defined(CONFIG_DDR_2T_TIMING) 171 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 172 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 173 | SDRAM_CFG_DBW_32 \ 174 | SDRAM_CFG_2T_EN) 175 /* 0x43088000 */ 176 #else 177 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 178 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 179 | SDRAM_CFG_DBW_32) 180 /* 0x43080000 */ 181 #endif 182 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 183 /* set burst length to 8 for 32-bit data path */ 184 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 185 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 186 /* 0x44480632 */ 187 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 188 189 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 190 /*0x02000000*/ 191 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 192 | DDRCDR_PZ_NOMZ \ 193 | DDRCDR_NZ_NOMZ \ 194 | DDRCDR_M_ODR) 195 196 /* 197 * FLASH on the Local Bus 198 */ 199 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 200 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 201 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 202 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 203 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 204 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 205 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 206 207 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 208 | BR_PS_16 /* 16 bit port */ \ 209 | BR_MS_GPCM /* MSEL = GPCM */ \ 210 | BR_V) /* valid */ 211 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 212 | OR_GPCM_XACS \ 213 | OR_GPCM_SCY_9 \ 214 | OR_GPCM_EHTR \ 215 | OR_GPCM_EAD) 216 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 217 /* window base at flash base */ 218 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 219 /* 16 MB window size */ 220 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 221 222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 224 225 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 226 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 227 228 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 229 !defined(CONFIG_SPL_BUILD) 230 #define CONFIG_SYS_RAMBOOT 231 #endif 232 233 #define CONFIG_SYS_INIT_RAM_LOCK 1 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 235 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 236 237 #define CONFIG_SYS_GBL_DATA_OFFSET \ 238 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 240 241 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 242 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 243 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 244 245 /* 246 * Local Bus LCRR and LBCR regs 247 */ 248 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 249 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 250 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 251 | (0xFF << LBCR_BMT_SHIFT) \ 252 | 0xF) /* 0x0004ff0f */ 253 254 /* LB refresh timer prescal, 266MHz/32 */ 255 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 256 257 /* drivers/mtd/nand/nand.c */ 258 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 259 #define CONFIG_SYS_NAND_BASE 0xFFF00000 260 #else 261 #define CONFIG_SYS_NAND_BASE 0xE2800000 262 #endif 263 264 #define CONFIG_MTD_DEVICE 265 #define CONFIG_MTD_PARTITION 266 #define CONFIG_CMD_MTDPARTS 267 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 268 #define MTDPARTS_DEFAULT \ 269 "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" 270 271 #define CONFIG_SYS_MAX_NAND_DEVICE 1 272 #define CONFIG_CMD_NAND 1 273 #define CONFIG_NAND_FSL_ELBC 1 274 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 275 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 276 277 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 278 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 279 | BR_PS_8 /* 8 bit port */ \ 280 | BR_MS_FCM /* MSEL = FCM */ \ 281 | BR_V) /* valid */ 282 #define CONFIG_SYS_NAND_OR_PRELIM \ 283 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 284 | OR_FCM_CSCT \ 285 | OR_FCM_CST \ 286 | OR_FCM_CHT \ 287 | OR_FCM_SCY_1 \ 288 | OR_FCM_TRLX \ 289 | OR_FCM_EHTR) 290 /* 0xFFFF8396 */ 291 292 #ifdef CONFIG_NAND 293 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 294 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 295 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 296 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 297 #else 298 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 299 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 300 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 301 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 302 #endif 303 304 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 305 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 306 307 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 308 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 309 310 /* local bus write LED / read status buffer (BCSR) mapping */ 311 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 312 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 313 /* map at 0xFA000000 on LCS3 */ 314 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 315 | BR_PS_8 /* 8 bit port */ \ 316 | BR_MS_GPCM /* MSEL = GPCM */ \ 317 | BR_V) /* valid */ 318 /* 0xFA000801 */ 319 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 320 | OR_GPCM_CSNT \ 321 | OR_GPCM_ACS_DIV2 \ 322 | OR_GPCM_XACS \ 323 | OR_GPCM_SCY_15 \ 324 | OR_GPCM_TRLX_SET \ 325 | OR_GPCM_EHTR_SET \ 326 | OR_GPCM_EAD) 327 /* 0xFFFF8FF7 */ 328 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 329 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 330 331 /* Vitesse 7385 */ 332 333 #ifdef CONFIG_VSC7385_ENET 334 335 /* VSC7385 Base address on LCS2 */ 336 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 337 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 338 339 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 340 | BR_PS_8 /* 8 bit port */ \ 341 | BR_MS_GPCM /* MSEL = GPCM */ \ 342 | BR_V) /* valid */ 343 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 344 | OR_GPCM_CSNT \ 345 | OR_GPCM_XACS \ 346 | OR_GPCM_SCY_15 \ 347 | OR_GPCM_SETA \ 348 | OR_GPCM_TRLX_SET \ 349 | OR_GPCM_EHTR_SET \ 350 | OR_GPCM_EAD) 351 /* 0xFFFE09FF */ 352 353 /* Access window base at VSC7385 base */ 354 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 355 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 356 357 #endif 358 359 #define CONFIG_MPC83XX_GPIO 1 360 361 /* 362 * Serial Port 363 */ 364 #define CONFIG_CONS_INDEX 1 365 #define CONFIG_SYS_NS16550_SERIAL 366 #define CONFIG_SYS_NS16550_REG_SIZE 1 367 368 #define CONFIG_SYS_BAUDRATE_TABLE \ 369 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 370 371 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 372 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 373 374 /* I2C */ 375 #define CONFIG_SYS_I2C 376 #define CONFIG_SYS_I2C_FSL 377 #define CONFIG_SYS_FSL_I2C_SPEED 400000 378 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 380 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 381 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 382 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 383 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 384 385 /* 386 * General PCI 387 * Addresses are mapped 1-1. 388 */ 389 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 390 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 391 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 392 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 393 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 394 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 395 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 396 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 397 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 398 399 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 400 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 401 402 /* 403 * TSEC 404 */ 405 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 406 407 #define CONFIG_GMII /* MII PHY management */ 408 409 #ifdef CONFIG_TSEC1 410 #define CONFIG_HAS_ETH0 411 #define CONFIG_TSEC1_NAME "TSEC0" 412 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 413 #define TSEC1_PHY_ADDR 0x1c 414 #define TSEC1_FLAGS TSEC_GIGABIT 415 #define TSEC1_PHYIDX 0 416 #endif 417 418 #ifdef CONFIG_TSEC2 419 #define CONFIG_HAS_ETH1 420 #define CONFIG_TSEC2_NAME "TSEC1" 421 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 422 #define TSEC2_PHY_ADDR 4 423 #define TSEC2_FLAGS TSEC_GIGABIT 424 #define TSEC2_PHYIDX 0 425 #endif 426 427 /* Options are: TSEC[0-1] */ 428 #define CONFIG_ETHPRIME "TSEC1" 429 430 /* 431 * Configure on-board RTC 432 */ 433 #define CONFIG_RTC_DS1337 434 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 435 436 /* 437 * Environment 438 */ 439 #if defined(CONFIG_NAND) 440 #define CONFIG_ENV_IS_IN_NAND 1 441 #define CONFIG_ENV_OFFSET (512 * 1024) 442 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 443 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 444 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 445 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 446 #define CONFIG_ENV_OFFSET_REDUND \ 447 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 448 #elif !defined(CONFIG_SYS_RAMBOOT) 449 #define CONFIG_ENV_IS_IN_FLASH 1 450 #define CONFIG_ENV_ADDR \ 451 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 452 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 453 #define CONFIG_ENV_SIZE 0x2000 454 455 /* Address and size of Redundant Environment Sector */ 456 #else 457 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 459 #define CONFIG_ENV_SIZE 0x2000 460 #endif 461 462 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 463 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 464 465 /* 466 * BOOTP options 467 */ 468 #define CONFIG_BOOTP_BOOTFILESIZE 469 #define CONFIG_BOOTP_BOOTPATH 470 #define CONFIG_BOOTP_GATEWAY 471 #define CONFIG_BOOTP_HOSTNAME 472 473 /* 474 * Command line configuration. 475 */ 476 #define CONFIG_CMD_DATE 477 #define CONFIG_CMD_PCI 478 479 #define CONFIG_CMDLINE_EDITING 1 480 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 481 482 /* 483 * Miscellaneous configurable options 484 */ 485 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 486 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 487 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 488 489 /* Print Buffer Size */ 490 #define CONFIG_SYS_PBSIZE \ 491 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 492 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 493 /* Boot Argument Buffer Size */ 494 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 495 496 /* 497 * For booting Linux, the board info and command line data 498 * have to be in the first 256 MB of memory, since this is 499 * the maximum mapped by the Linux kernel during initialization. 500 */ 501 /* Initial Memory map for Linux*/ 502 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 503 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 504 505 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 506 507 #ifdef CONFIG_SYS_66MHZ 508 509 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 510 /* 0x62040000 */ 511 #define CONFIG_SYS_HRCW_LOW (\ 512 0x20000000 /* reserved, must be set */ |\ 513 HRCWL_DDRCM |\ 514 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 515 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 516 HRCWL_CSB_TO_CLKIN_2X1 |\ 517 HRCWL_CORE_TO_CSB_2X1) 518 519 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 520 521 #elif defined(CONFIG_SYS_33MHZ) 522 523 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 524 /* 0x65040000 */ 525 #define CONFIG_SYS_HRCW_LOW (\ 526 0x20000000 /* reserved, must be set */ |\ 527 HRCWL_DDRCM |\ 528 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 529 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 530 HRCWL_CSB_TO_CLKIN_5X1 |\ 531 HRCWL_CORE_TO_CSB_2X1) 532 533 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 534 535 #endif 536 537 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 538 HRCWH_PCI_HOST |\ 539 HRCWH_PCI1_ARBITER_ENABLE |\ 540 HRCWH_CORE_ENABLE |\ 541 HRCWH_BOOTSEQ_DISABLE |\ 542 HRCWH_SW_WATCHDOG_DISABLE |\ 543 HRCWH_TSEC1M_IN_RGMII |\ 544 HRCWH_TSEC2M_IN_RGMII |\ 545 HRCWH_BIG_ENDIAN) 546 547 #ifdef CONFIG_NAND 548 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 549 HRCWH_FROM_0XFFF00100 |\ 550 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 551 HRCWH_RL_EXT_NAND) 552 #else 553 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 554 HRCWH_FROM_0X00000100 |\ 555 HRCWH_ROM_LOC_LOCAL_16BIT |\ 556 HRCWH_RL_EXT_LEGACY) 557 #endif 558 559 /* System IO Config */ 560 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 561 /* Enable Internal USB Phy and GPIO on LCD Connector */ 562 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 563 564 #define CONFIG_SYS_HID0_INIT 0x000000000 565 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 566 HID0_ENABLE_INSTRUCTION_CACHE | \ 567 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 568 569 #define CONFIG_SYS_HID2 HID2_HBE 570 571 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 572 573 /* DDR @ 0x00000000 */ 574 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 575 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 576 | BATU_BL_256M \ 577 | BATU_VS \ 578 | BATU_VP) 579 580 /* PCI @ 0x80000000 */ 581 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 582 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 583 | BATU_BL_256M \ 584 | BATU_VS \ 585 | BATU_VP) 586 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 587 | BATL_PP_RW \ 588 | BATL_CACHEINHIBIT \ 589 | BATL_GUARDEDSTORAGE) 590 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 591 | BATU_BL_256M \ 592 | BATU_VS \ 593 | BATU_VP) 594 595 /* PCI2 not supported on 8313 */ 596 #define CONFIG_SYS_IBAT3L (0) 597 #define CONFIG_SYS_IBAT3U (0) 598 #define CONFIG_SYS_IBAT4L (0) 599 #define CONFIG_SYS_IBAT4U (0) 600 601 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 602 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 603 | BATL_PP_RW \ 604 | BATL_CACHEINHIBIT \ 605 | BATL_GUARDEDSTORAGE) 606 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 607 | BATU_BL_256M \ 608 | BATU_VS \ 609 | BATU_VP) 610 611 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 612 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 613 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 614 615 #define CONFIG_SYS_IBAT7L (0) 616 #define CONFIG_SYS_IBAT7U (0) 617 618 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 619 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 620 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 621 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 622 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 623 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 624 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 625 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 626 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 627 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 628 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 629 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 630 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 631 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 632 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 633 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 634 635 /* 636 * Environment Configuration 637 */ 638 #define CONFIG_ENV_OVERWRITE 639 640 #define CONFIG_NETDEV "eth1" 641 642 #define CONFIG_HOSTNAME mpc8313erdb 643 #define CONFIG_ROOTPATH "/nfs/root/path" 644 #define CONFIG_BOOTFILE "uImage" 645 /* U-Boot image on TFTP server */ 646 #define CONFIG_UBOOTPATH "u-boot.bin" 647 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 648 649 /* default location for tftp and bootm */ 650 #define CONFIG_LOADADDR 800000 651 #define CONFIG_BAUDRATE 115200 652 653 #define CONFIG_EXTRA_ENV_SETTINGS \ 654 "netdev=" CONFIG_NETDEV "\0" \ 655 "ethprime=TSEC1\0" \ 656 "uboot=" CONFIG_UBOOTPATH "\0" \ 657 "tftpflash=tftpboot $loadaddr $uboot; " \ 658 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 659 " +$filesize; " \ 660 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 661 " +$filesize; " \ 662 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 663 " $filesize; " \ 664 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 665 " +$filesize; " \ 666 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 667 " $filesize\0" \ 668 "fdtaddr=780000\0" \ 669 "fdtfile=" CONFIG_FDTFILE "\0" \ 670 "console=ttyS0\0" \ 671 "setbootargs=setenv bootargs " \ 672 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 673 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 674 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 675 "$netdev:off " \ 676 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 677 678 #define CONFIG_NFSBOOTCOMMAND \ 679 "setenv rootdev /dev/nfs;" \ 680 "run setbootargs;" \ 681 "run setipargs;" \ 682 "tftp $loadaddr $bootfile;" \ 683 "tftp $fdtaddr $fdtfile;" \ 684 "bootm $loadaddr - $fdtaddr" 685 686 #define CONFIG_RAMBOOTCOMMAND \ 687 "setenv rootdev /dev/ram;" \ 688 "run setbootargs;" \ 689 "tftp $ramdiskaddr $ramdiskfile;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr $ramdiskaddr $fdtaddr" 693 694 #endif /* __CONFIG_H */ 695